On 9/13/24 18:16, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-
DM163 is an emulated 8x8 LED matrix. This commit flips the image
horizontally so it's rendered the same way as on the hardware.
Signed-off-by: Inès Varhol
---
hw/display/dm163.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
index f92a
Key Changes Compared to Version 5:
In target_arch_sigtramp.h removed static const,
as there was a compile-time constant issue
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_signal.h
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
configs/targets/riscv64-bsd-user.mak | 4
1 file changed, 4 insertions(+)
create mode 100644 configs/targets/risc
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_cpu.h | 14 ++
1 file changed, 14 insertions(+)
di
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_sigtramp.h | 41 +++
1
shadow_bmap, iter_bmap and iter_dirty_pages are introduced
to satisfy the need for background sync.
Meanwhile, introduce enumeration of sync method.
Signed-off-by: Hyman Huang
---
include/exec/ramblock.h | 45 +
migration/ram.c | 6 ++
2 file
When VM is configured with huge memory, the current throttle logic
doesn't look like to scale, because migration_trigger_throttle()
is only called for each iteration, so it won't be invoked for a long
time if one iteration can take a long time.
The background sync and throttle aim to fix the above
Supply the migration_bitmap_sync function along with the
background argument. Introduce the sync_mode global variable
to track the sync mode and support background sync while
keeping backward compatibility.
Signed-off-by: Hyman Huang
---
include/exec/ram_addr.h | 107
The background sync watcher is used to detect that if the
iteration lasts a long time, if so, trigger the background
sync.
Signed-off-by: Hyman Huang
---
migration/ram.c| 110 +
migration/ram.h| 3 ++
migration/trace-events | 3 ++
3 fi
This is the first version for auto-converge refinements; refer to the
following link for details about the RFC version:
https://patchew.org/QEMU/cover.1725891841.git.yong.hu...@smartx.com/
This series introduces two refinements called "background sync" and
"responsive throttle," respectively.
1.
To enable the responsive throttle that will be implemented
in the next commit, introduce the cpu-responsive-throttle
parameter.
Signed-off-by: Hyman Huang
---
migration/migration-hmp-cmds.c | 8
migration/options.c| 20
migration/options.h|
The original migration information dirty-sync-count could
no longer reflect iteration count due to the introduction
of background synchronization in the next commit;
add the iteration count to compensate.
Signed-off-by: Hyman Huang
---
migration/migration-stats.h | 4
migration/migration.
Currently, the convergence algorithm determines that the migration
cannot converge according to the following principle:
The dirty pages generated in current iteration exceed a specific
percentage (throttle-trigger-threshold, 50 by default) of the number
of transmissions. Let's refer to this criter
From: Jinliang Zheng
Currently, object_initialize_with_type() calls object_class_property_init_all()
before initializing Object->properties. This may cause Object->properties to
still be NULL when we call object_property_add() on Object.
For exmaple, if we extend DEFINE_PROP_ARRAY() to a version
ping
Requesting for review on this patch series. The first 3 patches have
been merged by Daniel but the rest need to be reviewed. Thanks!
patch URL:
https://lore.kernel.org/qemu-devel/20240905195735.16911-1-dorjoychy...@gmail.com/T/#t
Regards,
Dorjoy
On Fri, Sep 06, 2024 at 01:57:32AM +0600, Dorjoy Chowdhury wrote:
> Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves[2]
> for stripped down TPM functionality like cryptographic attestation.
> The requests to and responses from NSM device are CBOR[3] encoded.
>
> This commit adds s
On Mon, Sep 16, 2024, 1:26 AM Michael S. Tsirkin wrote:
> On Fri, Sep 06, 2024 at 01:57:32AM +0600, Dorjoy Chowdhury wrote:
> > Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves[2]
> > for stripped down TPM functionality like cryptographic attestation.
> > The requests to and resp
On 9/12/24 2:29 AM, Alistair Francis wrote:
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers
On 9/12/24 2:29 AM, Alistair Francis wrote:
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1
Hi Peter, Alistair,
On 9/14/24 6:15 AM, Alistair Francis wrote:
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell wrote:
On Thu, 12 Sept 2024 at 06:30, Alistair Francis wrote:
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
Merge tag 'pull-testing-gdbstub-oct-1
On Mon, Sep 16, 2024 at 01:46:52AM +0600, Dorjoy Chowdhury wrote:
> > + len = cbor_serialize(root, response->iov_base, response->iov_len);
>
> As far as I can tell, all these also need to be switched to use
> iov_from_buf.
>
>
> Sorry I didn't understand this. The iovecs passed in
On Fri, Sep 06, 2024 at 01:57:32AM +0600, Dorjoy Chowdhury wrote:
> +const struct nsm_cmd nsm_cmds[] = {
> +{ "GetRandom", CBOR_ROOT_TYPE_STRING, handle_GetRandom },
> +{ "DescribeNSM", CBOR_ROOT_TYPE_STRING, handle_DescribeNSM },
> +{ "DescribePCR", CBOR_ROOT_TYPE_MAP, handle_D
The semantic change has been introduced by commit 5becdc0ab0 ("hostmem:
simplify the code for merge and dump properties") even it clarifies that
no senmatic change has been introduced. After the commit, the merge
property can be applied even the corresponding memory region isn't
initialized yet. Th
Hi,
On Thursday, September 12, 2024 3:24:27 PM GMT+5:30 Eugenio Perez Martin wrote:
> On Wed, Sep 11, 2024 at 9:36 PM Sahil wrote:
> > Hi,
> >
> > On Monday, September 9, 2024 6:04:45 PM GMT+5:30 Eugenio Perez Martin wrote:
> > > On Sun, Sep 8, 2024 at 9:47 PM Sahil wrote:
> > > > On Friday, Au
On 13/09/2024 19.26, Alex Bennée wrote:
The multiarch system tests output serial data which should be
redirected to the "output" chardev rather than echoed to the console.
Remove the unused EXTFLAGS variable while we are at it.
Signed-off-by: Alex Bennée
---
tests/tcg/s390x/Makefile.softmmu-
On 15/09/2024 21.58, Daniel Henrique Barboza wrote:
Hi Peter, Alistair,
On 9/14/24 6:15 AM, Alistair Francis wrote:
On Fri, Sep 13, 2024 at 8:37 PM Peter Maydell
wrote:
On Thu, 12 Sept 2024 at 06:30, Alistair Francis
wrote:
The following changes since commit
a4eb31c678400472de0b4915b915
Hi, I had already fixed it and sent a patchv6,
I will send another one with the other changes.
On Mon, 16 Sept, 2024, 5:51 am Daniel Henrique Barboza, <
dbarb...@ventanamicro.com> wrote:
>
>
> On 9/12/24 2:29 AM, Alistair Francis wrote:
> > From: Mark Corbin
> >
> > Implemented the 'setup_sigtr
On Sat, Sep 14, 2024 at 10:42:36 +0200, Markus Armbruster wrote:
> Peter Krempa writes:
>
> > This is a little off-topic:
> >
> > So I wanted to make libvirt use the new parameter to stay ahead
> > deprecation. I've applied this patch to qemu, dumped capabilities and
> > pretty much expected a bu
On 9/13/24 7:39 PM, Andrey Drobyshev wrote:
> Introduce Qcow2 runtime boolean option "discard-subclusters". This
> option influences discard alignment value (either cluster_size or
> subcluster_size) and essentially makes subcluster-based discard optional.
> We disable it by default.
>
> Also twe
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