Re: [Bug Report] smmuv3 event 0x10 report when running virtio-blk-pci

Hi Zhou, On Mon, Sep 9, 2024 at 3:22 PM Zhou Wang via wrote: > > Hi All, > > When I tested mainline qemu(commit 7b87a25f49), it reports smmuv3 event 0x10 > during kernel booting up. > > qemu command which I use is as below: > > qemu-system-aarch64 -machine > virt,kernel_irqchip=on,gic-version=3,

[PATCH v3 0/4] KVM: Dynamic sized memslots array

v3: - In kvm_get_free_slot(), avoid re-search when slots array grows [Juraj] v1: https://lore.kernel.org/r/20240904191635.3045606-1-pet...@redhat.com v2: https://lore.kernel.org/r/20240904223510.3519358-1-pet...@redhat.com This series make KVM memslots to be allocated dynamically in QEMU. It fix

[PATCH v3 2/4] KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT

Make the default max nr_slots a macro, it's only used when KVM reports nothing. Reviewed-by: David Hildenbrand Signed-off-by: Peter Xu --- accel/kvm/kvm-all.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c51a3f18db..2a2ee

[PATCH v3 1/4] KVM: Dynamic sized kvm memslots array

Zhiyi reported an infinite loop issue in VFIO use case. The cause of that was a separate discussion, however during that I found a regression of dirty sync slowness when profiling. Each KVMMemoryListerner maintains an array of kvm memslots. Currently it's statically allocated to be the max suppo

[PATCH v3 4/4] KVM: Rename KVMState->nr_slots to nr_slots_max

This value used to reflect the maximum supported memslots from KVM kernel. Rename it to be clearer. Reviewed-by: David Hildenbrand Signed-off-by: Peter Xu --- include/sysemu/kvm_int.h | 4 ++-- accel/kvm/kvm-all.c | 16 2 files changed, 10 insertions(+), 10 deletions(-)

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On 9/9/24 06:40, Philippe Mathieu-Daudé wrote: Hi, On 3/9/24 18:06, Peter Maydell wrote: This patchset removes the various Arm machines which we deprecated for the 9.0 release and are therefore allowed to remove for the 9.2 release:   akita, borzoi, cheetah, connex, mainstone, n800, n810,   spi

[PATCH v3 3/4] KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used

This will make all nr_slots counters to be named in the same manner. Reviewed-by: David Hildenbrand Signed-off-by: Peter Xu --- include/sysemu/kvm_int.h | 2 +- accel/kvm/kvm-all.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/sysemu/kvm_int.h b/include

Re: [PATCH v2 1/1] system: improve migration debug

On Thu, Sep 05, 2024 at 09:19:41PM +0200, Denis V. Lunev wrote: > Right now migration_throttle() tracepoint lacks very important > important information, i.e. no one could easily say how much the guest > is throttled. This makes difficult to debug guest quality of service > during migration. > > T

Re: [PATCH v9 0/5] Implement QATzip compression method

On Fri, Aug 30, 2024 at 04:27:17PM -0700, Yichen Wang wrote: > v9: > - Rebase changes on top of cec99171931ea79215c79661d33423ac84e63b6e; > - Address comments and add Review-by in commit messages; queued, thanks. -- Peter Xu

Re: [PULL 27/34] migration/multifd: Move nocomp code into multifd-nocomp.c

Peter Maydell writes: > On Wed, 4 Sept 2024 at 13:48, Fabiano Rosas wrote: >> >> In preparation for adding new payload types to multifd, move most of >> the no-compression code into multifd-nocomp.c. Let's try to keep a >> semblance of layering by not mixing general multifd control flow with >>

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On Mon, 9 Sept 2024 at 15:55, Guenter Roeck wrote: > > On 9/9/24 06:40, Philippe Mathieu-Daudé wrote: > > Hi, > > > > On 3/9/24 18:06, Peter Maydell wrote: > >> This patchset removes the various Arm machines which we deprecated > >> for the 9.0 release and are therefore allowed to remove for the 9

Re: [PATCH v2] aspeed: Deprecate the tacoma-bmc machine

On 9/9/24 04:20, Joel Stanley wrote: On Sat, 31 Aug 2024 at 05:41, Guenter Roeck wrote: On Fri, Aug 30, 2024 at 10:09:25AM +0200, Cédric Le Goater wrote: Hello, I solved the problem by adding support for IBM Bonnell (which instantiates the TPM chip through its devicetree file, similar to t

Re: [PATCH v11 08/11] vfio/migration: Implement VFIO migration protocol v2

On Mon, Sep 09, 2024 at 03:52:39PM +0300, Avihai Horon wrote: > > On 05/09/2024 21:31, Peter Xu wrote: > > External email: Use caution opening links or attachments > > > > > > On Thu, Sep 05, 2024 at 07:45:43PM +0300, Avihai Horon wrote: > > > > Does it also mean then that the currently reported

Re: [PATCH RFC V3 01/29] arm/virt,target/arm: Add new ARMCPU {socket,cluster,core,thread}-id property

On Wed, Sep 04, 2024 at 05:37:21PM +, Salil Mehta wrote: > Date: Wed, 4 Sep 2024 17:37:21 + > From: Salil Mehta > Subject: RE: [PATCH RFC V3 01/29] arm/virt,target/arm: Add new ARMCPU > {socket,cluster,core,thread}-id property > > Hi Zhao, > > > From: zhao1@intel.com > > Sent: We

Re: [RFC PATCH] tests/qtest: Don't parallelize migration-test

Peter Maydell writes: > The migration-test is a long-running test whose subtests all launch > at least two QEMU processes. This means that if for example the host > has 4 CPUs then 'make check' defaults to a parallelism of 5, and if > we launch 5 migration-tests in parallel then we will be runni

Re: [PATCH 2/2] hw/sd: Remove legacy sd_enable()

On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé wrote: > > sd_enable() was only used by omap_mmc_enable() which > got recently removed. Time to remove it. > > Since the SDState::enable boolean is now always %true, > we can remove it and simplify. > > Signed-off-by: Philippe Mathieu-Daudé >

Re: [PATCH 1/2] hw/sd: Remove legacy sd_set_cb()

On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé wrote: > > sd_set_cb() was only used by omap2_mmc_init() which > got recently removed. Time to remove it. For historical > background on the me_no_qdev_me_kill_mammoth_with_rocks > kludge, see commit 007d1dbf72 ("sd: Hide the qdev-but-not-quite

Re: [RFC PATCH] tests/qtest: Don't parallelize migration-test

On Mon, 9 Sept 2024 at 16:23, Alex Bennée wrote: > I guess one question is are we getting value from all the extra > migration tests? There certainly seem to be some sub-tests that are > slower than the others and I assume testing a small delta on the tests > before it. > > On s390x it seems the n

Re: [PATCH v2 03/17] migration/multifd: Zero p->flags before starting filling a packet

On Tue, Aug 27, 2024 at 07:54:22PM +0200, Maciej S. Szmigiero wrote: > From: "Maciej S. Szmigiero" > > This way there aren't stale flags there. > > p->flags can't contain SYNC to be sent at the next RAM packet since syncs > are now handled separately in multifd_send_thread. > > Signed-off-by: M

Re: [PATCH] block: support locking on change medium

Am 09.09.2024 um 16:25 hat Joelle van Dyne geschrieben: > On Mon, Sep 9, 2024 at 2:56 AM Kevin Wolf wrote: > > > > Am 09.09.2024 um 03:58 hat Joelle van Dyne geschrieben: > > > New optional argument for 'blockdev-change-medium' QAPI command to allow > > > the caller to specify if they wish to enab

Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo

On 9/9/24 00:18, LIU Zhiwei wrote: On 2024/9/5 11:34, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: +    if (info & CPUINFO_ZVE64X) { +    /* + * Get vlenb for Vector: vsetvli rd, x0, e64. + * VLMAX = LMUL * VLEN / SEW. + * The "vsetvli rd, x0, e64" me

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On 9/9/24 17:02, Peter Maydell wrote: On Mon, 9 Sept 2024 at 15:55, Guenter Roeck wrote: On 9/9/24 06:40, Philippe Mathieu-Daudé wrote: Hi, On 3/9/24 18:06, Peter Maydell wrote: This patchset removes the various Arm machines which we deprecated for the 9.0 release and are therefore allowed

Re: [PATCH v2] target/riscv32: Fix masking of physical address

On 9/9/24 01:32, Andrew Jones wrote: C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will be

Re: [PULL 00/10] Crypto fixes patches

On Mon, 9 Sept 2024 at 15:17, Daniel P. Berrangé wrote: > > The following changes since commit f2aee60305a1e40374b2fc1093e4d04404e780ee: > > Merge tag 'pull-request-2024-09-08' of https://gitlab.com/huth/qemu into > staging (2024-09-09 10:47:24 +0100) > > are available in the Git repository at:

Re: [PATCH trvivial] linux-user/syscall.c: replace function pointers for flock64 fcntl with macros

On 9/8/24 22:26, Michael Tokarev wrote: Why do you think this is an improvement? It just feels more natural, so to say. What was wrong with the function pointers? Not exactly wrong.  It just hurts my eyes when I see an address is taken of a function marked `inline` I'm certainly happy to

Re: [PATCH trvivial] linux-user/syscall.c: replace function pointers for flock64 fcntl with macros

On Mon, 9 Sept 2024 at 17:19, Richard Henderson wrote: > > On 9/8/24 22:26, Michael Tokarev wrote: > >> Why do you think this is an improvement? > > > > It just feels more natural, so to say. > > > >> What was wrong with the function pointers? > > > > Not exactly wrong. It just hurts my eyes when

[PATCH v2 10/29] target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 - target/arm/tcg/a64.decode | 12 +++ 2 files changed, 61 insertions(+), 91 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/trans

[PATCH v2 02/29] target/arm: Replace tcg_gen_dupi_vec with constants in translate-sve.c

Instead of copying a constant into a temporary with dupi, use a vector constant directly. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 128 + 1 file changed, 49 insertions(+), 79 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/

[PATCH v2 00/29] target/arm: AdvSIMD decodetree conversion, part 4

First post-9.1 queue flush. r~ Richard Henderson (29): target/arm: Replace tcg_gen_dupi_vec with constants in gengvec.c target/arm: Replace tcg_gen_dupi_vec with constants in translate-sve.c target/arm: Use cmpsel in gen_ushl_vec target/arm: Use cmpsel in gen_sshl_vec target/arm: Use tc

[PATCH v2 09/29] target/arm: Simplify do_reduction_op

Use simple shift and add instead of ctpop, ctz, shift and mask. Unlike SVE, there is no predicate to disable elements. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 40 +++--- 1 file changed, 13 insertions(+), 27 del

[PATCH v2 29/29] target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 160 +++-- target/arm/tcg/a64.decode | 30 +++ 2 files changed, 63 insertions(+), 127 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e6290e

[PATCH v2 14/29] target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr

Handle the two special cases within these new functions instead of higher in the call stack. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 5 + target/arm/tcg/gengvec.c| 19 +++ target/arm/tcg/translate-a64.c | 16

[PATCH v2 15/29] target/arm: Fix whitespace near gen_srshr64_i64

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 33c5084ea6..3abdc57202 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg

[PATCH v2 05/29] target/arm: Use tcg_gen_extract2_i64 for EXT

The extract2 tcg op performs the same operation as the do_ext64 function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 23 +++ 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/

[PATCH v2 28/29] target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 ++--- target/arm/tcg/a64.decode | 24 + 2 files changed, 186 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 77324e01

[PATCH v2 08/29] target/arm: Convert UZP, TRN, ZIP to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 158 ++--- target/arm/tcg/a64.decode | 9 ++ 2 files changed, 77 insertions(+), 90 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl

[PATCH v2 21/29] target/arm: Split out subroutines of handle_shri_with_rndacc

There isn't a lot of commonality along the different paths of handle_shri_with_rndacc. Split them out to separate functions, which will be usable during the decodetree conversion. Simplify 64-bit rounding operations to not require double-word arithmetic. Signed-off-by: Richard Henderson --- ta

[PATCH v2 25/29] target/arm: Convert VQSHL, VQSHLU to gvec

Signed-off-by: Richard Henderson --- target/arm/helper.h | 12 target/arm/tcg/translate.h | 7 ++ target/arm/tcg/gengvec.c| 36 +++ target/arm/tcg/neon_helper.c| 33 ++ target/arm/tcg/translate-neon.c | 110 +--- t

[PATCH v2 11/29] target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 ++--- target/arm/tcg/a64.decode | 14 +++ 2 files changed, 67 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran

[PATCH v2 13/29] target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 117 ++--- target/arm/tcg/a64.decode | 9 +++ 2 files changed, 59 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/trans

[PATCH v2 03/29] target/arm: Use cmpsel in gen_ushl_vec

Instead of cmp+and or cmp+andc, use cmpsel. This will be better for hosts that use predicate registers for cmp. Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/targe

[PATCH v2 20/29] target/arm: Push tcg_rnd into handle_shri_with_rndacc

We always pass the same value for round; compute it within common code. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 32 ++-- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl

[PATCH v2 19/29] target/arm: Convert SSHLL, USHLL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 81 -- target/arm/tcg/a64.decode | 8 2 files changed, 45 insertions(+), 44 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 740620074a.

[PATCH v2 27/29] target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 223 ++--- target/arm/tcg/a64.decode | 36 +- 2 files changed, 128 insertions(+), 131 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 791872

[PATCH v2 26/29] target/arm: Widen NeonGenNarrowEnvFn return to 64 bits

While these functions really do return a 32-bit value, widening the return type means that we need do less marshalling between TCG types. Remove NeonGenNarrowEnvFn typedef; add NeonGenOne64OpEnvFn. Signed-off-by: Richard Henderson --- target/arm/helper.h | 22 ++-- target/ar

[PATCH v2 04/29] target/arm: Use cmpsel in gen_sshl_vec

Instead of cmp+and or cmp+andc, use cmpsel. This will be better for hosts that use predicate registers for cmp. Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gen

[PATCH v2 18/29] target/arm: Use {, s}extract in handle_vec_simd_wshli

Combine the right shift with the extension via the tcg extract operations. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1225aac6

[PATCH v2 12/29] target/arm: Convert FMOVI (scalar, immediate) to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 74 -- target/arm/tcg/a64.decode | 4 ++ 2 files changed, 30 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transla

[PATCH v2 22/29] target/arm: Convert SHRN, RSHRN to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 95 +- target/arm/tcg/a64.decode | 8 +++ 2 files changed, 55 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f4deacd554..

[PATCH v2 16/29] target/arm: Convert handle_vec_simd_shri to decodetree

This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 86 +++--- target/arm/tcg/a64.decode | 63 - 2 files changed, 89 insertions(+), 60 deletions(-) d

[PATCH v2 24/29] target/arm: Convert handle_scalar_simd_shli to decodetree

This includes SHL and SLI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 +++--- target/arm/tcg/a64.decode | 4 2 files changed, 13 insertions(+), 35 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/trans

[PATCH v2 01/29] target/arm: Replace tcg_gen_dupi_vec with constants in gengvec.c

Instead of copying a constant into a temporary with dupi, use a vector constant directly. Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 43 ++-- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/gengvec.c b/target

[PATCH v2 17/29] target/arm: Convert handle_vec_simd_shli to decodetree

This includes SHL and SLI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 33 +++-- target/arm/tcg/a64.decode | 15 +++ 2 files changed, 18 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm

[PATCH v2 23/29] target/arm: Convert handle_scalar_simd_shri to decodetree

This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 - target/arm/tcg/a64.decode | 16 2 files changed, 86 insertions(+), 70 deletions(-) diff --git a/target/a

[PATCH v2 07/29] target/arm: Convert TBL, TBX to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 ++ target/arm/tcg/a64.decode | 4 +++ 2 files changed, 18 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl

[PATCH v2 06/29] target/arm: Convert EXT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 121 + target/arm/tcg/a64.decode | 5 ++ 2 files changed, 53 insertions(+), 73 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl

Re: [PATCH v2 05/17] thread-pool: Implement non-AIO (generic) pool support

Hi, Stefan, Maciej, Sorry to be slow on responding. On Tue, Sep 03, 2024 at 03:04:54PM -0400, Stefan Hajnoczi wrote: > On Tue, 3 Sept 2024 at 12:54, Maciej S. Szmigiero > wrote: > > > > On 3.09.2024 15:55, Stefan Hajnoczi wrote: > > > On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero > > > wrot

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

On Mon, Sep 09, 2024 at 05:45:35PM +0200, Philippe Mathieu-Daudé wrote: > On 9/9/24 17:02, Peter Maydell wrote: > > On Mon, 9 Sept 2024 at 15:55, Guenter Roeck wrote: > > > > > > On 9/9/24 06:40, Philippe Mathieu-Daudé wrote: > > > > Hi, > > > > > > > > On 3/9/24 18:06, Peter Maydell wrote: > >

Re: [PATCH for-9.2 00/53] arm: Drop deprecated boards

Hi Peter, On 9/9/24 15:44, Peter Maydell wrote: On Mon, 9 Sept 2024 at 14:41, Philippe Mathieu-Daudé wrote: Hi, On 3/9/24 18:06, Peter Maydell wrote: This patchset removes the various Arm machines which we deprecated for the 9.0 release and are therefore allowed to remove for the 9.2 releas

[PATCH v3 25/26] target/m68k: Make vmstate variables static

These need not be exported beyond cpu.c. Fix a typo in vmstate_fpu. Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 188afc57f8..fd6c227820 100644 --- a/target/m68k/cp

[PATCH v3 04/26] target/m68k: Keep FPSR up-to-date

Proper support for m68k exceptions will require testing the FPCR vs the FPSR for every instruction. As a step, do not keep FPSR bits in fp_status, but copy them back to the FPSR in every instruction. Since most of the FPSR must be updated on every insn, combine this with the existing helper_ftst

[PATCH v3 00/26] target/m68k: fpu improvements

Supercedes: 20240812004451.13711-1-richard.hender...@linaro.org ("[PATCH for-9.2 v2 0/4] target/m68k: Implement fmove.p") Changes for v3: - Implement FPSR.EXC. In particular, packed decimal sets a different inexact bit. - Lots of cleanup to the address/load/store translation, in order

[PATCH v3 26/26] target/m68k: Implement FPIAR

So far, this is only read-as-written. Signed-off-by: Richard Henderson --- target/m68k/cpu.h| 1 + target/m68k/cpu.c| 23 ++- target/m68k/helper.c | 14 -- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu

[PATCH v3 03/26] target/m68k: Restore fp rounding mode on vm load

Call cpu_m68k_set_fpcr to make sure softfloat internals are up-to-date with the restored FPCR. Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1d49f4cb23..4d70cd50b4 100644 --- a/target/m68k/cp

[PATCH v3 16/26] target/m68k: Remove env argument to gen_load_mode

Use the env pointer in DisasContext. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 31 --- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 938c650c78..a3452ace96 100644 --- a/targ

[PATCH v3 01/26] target/m68k: Always return a temporary from gen_lea_mode

Returning a raw areg does not preserve the value if the areg is subsequently modified. Fixes, e.g. "jsr (sp)", where the return address is pushed before the branch. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483 Signed-off-by: Richard Henderson Message-Id: <20240813000737.228470-1-

[PATCH v3 02/26] target/m68k: Add FPSR exception bit defines

Signed-off-by: Richard Henderson --- target/m68k/cpu.h| 21 + target/m68k/fpu_helper.c | 22 +++--- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index b5bbeedb7a..e8dd75d242 100644 --- a/target/m

[PATCH v3 10/26] target/m68k: Use g_assert_not_reached in gen_lea_mode and gen_ea_mode

The mode argument is extracted from 3 bits, and all cases are covered. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1ba1220b21..71dfa6d9a2 100644 ---

[PATCH v3 09/26] target/m68k: Merge gen_ea into SRC_EA and DEST_EA

This will enable further cleanups further down the call chain. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 24 ++-- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 003318163c..1ba1220b2

[PATCH v3 12/26] target/m68k: Move pre-dec/post-inc to gen_lea_mode

Move autoinc down the call chain so that it happens in one place, more or less. This unifies code from gen_ea_mode and gen_ea_mode_fp, as well as the by-hand autoinc from CAS, TAS, MOVES, and MAC. In FMOVE_FCR and FMOVEM, use delay_set_areg to update the value to be stored at the end of the insn.

[PATCH v3 19/26] target/m68k: Split gen_ea_mode_fp for load/store

Replace with gen_load_mode_fp and gen_store_mode_fp. Return bool for success from the new functions. Remove gen_ldst_fp and ea_what as unused. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 125 +--- 1 file changed, 65 insertions(+), 60 deletio

[PATCH v3 22/26] target/m68k: Merge gen_store_fp, gen_store_mode_fp

This enables the exceptions raised by the actual store to be reflected as a failure. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 107 1 file changed, 53 insertions(+), 54 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/

[PATCH v3 08/26] target/m68k: Introduce M68K_FEATURE_FPU_PACKED_DECIMAL

Set for 68020 and 68030, but does nothing so far. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 389cd1f364..b40c5b64fe 100644

[PATCH v3 13/26] target/m68k: Split gen_ea_mode for load/store

Replace with gen_load_mode and gen_store_mode. Return bool for success from gen_store_mode, which makes store_dummy unused. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 155 1 file changed, 76 insertions(+), 79 deletions(-) diff --git a

[PATCH v3 17/26] target/m68k: Remove env argument to gen_store_mode

Use the env pointer in DisasContext. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index a3452ace96..8a96b38682 100644 --- a/target/m68k/translate.c +++ b

[PATCH v3 18/26] target/m68k: Remove env argument to gen_ea_mode_fp

Use the env pointer in DisasContext. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 21 ++--- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 8a96b38682..5bfdf9aadf 100644 --- a/target/m68k/tr

[PATCH v3 07/26] target/m68k: Invoke update_fpsr for FMOVECR

This instruction sets CC and EXC bits just like any other. So far we do not properly emulate inexact for the various rom entries, but we can certainly update CC correctly. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k

[PATCH v3 06/26] softfloat: Set QEMU_NO_HARDFLOAT for m68k

Like ppc, m68k needs the complete set of exception flags for each instruction, which means that float_flag_inexact will never be set before each instruction. Thus the hardfloat path will not be used, so we improve things by compiling it out. Signed-off-by: Richard Henderson --- fpu/softfloat.c

[PATCH v3 05/26] target/m68k: Update FPSR.EXC

So far we've only been updating the AEXC byte. Update the EXC byte as well. Signed-off-by: Richard Henderson --- target/m68k/fpu_helper.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 56694418f2..0c8

[PATCH v3 24/26] tests/tcg/m68k: Add packed decimal tests

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tests/tcg/m68k/packeddecimal-1.c | 41 tests/tcg/m68k/packeddecimal-2.c | 46 tests/tcg/m68k/Makefile.target | 4 ++- 3 files changed, 90 insertions(+), 1 del

[PATCH v3 15/26] target/m68k: Remove env argument to gen_lea_mode

Use the env pointer in DisasContext. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 78a9358416..938c650c78 100644 --- a/target/m68k/

[PATCH v3 14/26] target/m68k: Remove env argument to gen_lea_indexed

Use the env pointer in DisasContext. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 2c0852ac3a..78a9358416 100644 --- a/target/m68k/translate

[PATCH v3 20/26] target/m68k: Move gen_addr_fault into gen_{load, store}_mode_fp

Move the exception to be raised into the helpers. This in preparation for raising other exceptions, and still wanting to return failure. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/m68k/transla

[PATCH v3 21/26] target/m68k: Merge gen_load_fp, gen_load_mode_fp

This enables the exceptions raised by the actual load to be reflected as a failure. Signed-off-by: Richard Henderson --- target/m68k/translate.c | 104 1 file changed, 51 insertions(+), 53 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/t

[PATCH v3 11/26] target/m68k: Use OS_UNSIZED in LEA, PEA, JMP

For LEA and PEA, while the manual says "size = (long)", it also says that the pre-decrement and post-increment addressing modes are illegal. For JMP, the manual says "unsized". OS_UNSIZED is the way to signal gen_lea_mode to reject those addressing modes. Signed-off-by: Richard Henderson --- ta

Re: [PATCH] hw/char/stm32l4x5_usart.c: Fix ACK and min access size

Hi, (Cc'ing Arnaud & Inès who are listed as maintainers) On 6/9/24 18:12, Peter Maydell wrote: On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote: These changes allow the official STM32L4xx HAL UART driver to function properly with the b-l475e-iot01a machine. Modifying USART_CR1 TE bit should

Re: [PATCH for-9.2 07/53] hw/arm/KConfig: Replace ZAURUS with ZAURUS_SCOOP

On 3/9/24 18:07, Peter Maydell wrote: The ZAURUS KConfig symbol used to do multiple things: * pull in the tc6393xb display device * pull in the Zaurus SCOOP GPIO device * pull in hw/block/nand.c code * pull in hw/block/ecc.c code and was used by multiple machine types in the Zaurus family

Re: [PATCH for-9.2 14/53] hw/timer/pxa2xx_timer: Remove use of pxa.h header

On 3/9/24 18:07, Peter Maydell wrote: pxa2xx_timer includes pxa.h, but it doesn't actually make use of any of the #defines, function prototypes or structs defined there. Remove the unnecessary include (we will shortly be removing the whole header file). Signed-off-by: Peter Maydell --- hw/tim

Re: [PATCH for-9.2 13/53] hw/arm: Remove STRONGARM->PXA2XX dependency

On 3/9/24 18:07, Peter Maydell wrote: Currently the STRONGARM KConfig symbol pulls in PXA2XX. Since we've now removed all the true uses of PXA2XX, we'd like to remove the PXA2XX symbol too. To permit that, make STRONGARM directly select the things it truly depends on: * pxa25x-timer * SSI Si

Re: [PATCH for-9.2 15/53] hw/arm: Remove pxa2xx.c

On 3/9/24 18:07, Peter Maydell wrote: All the callers of pxa270_init() and pxa255_init() have now been removed, so we can remove pxa2xx.c. This also removes the only uses of a lot of pxa2xx specific devices, which will be removed in subsequent commits. Signed-off-by: Peter Maydell --- include

Re: [PATCH for-9.2 17/53] hw/input: Remove pxa2xx_keypad

On 3/9/24 18:07, Peter Maydell wrote: Remove the pxa2xx-specific pxa2xx_keypad device. Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 12 -- hw/input/pxa2xx_keypad.c | 331 --- hw/input/meson.build | 1 - 3 files changed, 344 deletion

Re: [PATCH for-9.2 23/53] hw/timer: Remove pxa27x-timer

On 3/9/24 18:07, Peter Maydell wrote: The pxa27x-timer can be removed now we have removed the PXA2xx SoC models. The pxa25x-timer device must remain as it is still used by strongarm. Signed-off-by: Peter Maydell --- hw/timer/pxa2xx_timer.c | 24 1 file changed, 24 de

Re: [PATCH for-9.2 37/53] hw/arm: Remove omap2.c

On 3/9/24 18:07, Peter Maydell wrote: The users of the OMAP2 SoC emulation have been removed, so we can delete omap2.c. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h |8 - hw/arm/omap2.c| 2715 - hw/arm/meson.build|1 - 3

Re: [PATCH for-9.2 38/53] hw/gpio: Remove TYPE_OMAP2_GPIO

On 3/9/24 18:07, Peter Maydell wrote: We've removed the OMAP2 SoC, so we can remove the OMAP2 GPIO device. (The source file remains, as it also has the model of the OMAP1 GPIO device.) Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 8 - hw/gpio/omap_gpio.c | 557 ---

Re: [PATCH for-9.2 39/53] hw/char: Remove omap2_uart

On 3/9/24 18:07, Peter Maydell wrote: Remove the OMAP2 specific code from omap_uart.c. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 5 -- hw/char/omap_uart.c | 113 -- 2 files changed, 118 deletions(-) Reviewed-by: Philippe Mathieu-D

Re: [PATCH for-9.2 43/53] hw/misc: Remove omap_gpmc

On 3/9/24 18:07, Peter Maydell wrote: The omap_gpmc device is only in OMAP2, which we are removing. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 11 - hw/misc/omap_gpmc.c | 898 -- hw/misc/meson.build | 1 - 3 files changed, 910 de

Re: [PATCH for-9.2 42/53] hw/misc: Remove omap_sdrc device

On 3/9/24 18:07, Peter Maydell wrote: The omap_sdrc device is only in OMAP2, which we are removing. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 7 -- hw/misc/omap_sdrc.c | 167 -- hw/misc/meson.build | 1 - 3 files changed, 175 d

Re: [PATCH for-9.2 44/53] hw/timer: Remove omap_gptimer

On 3/9/24 18:07, Peter Maydell wrote: The omap_gptimer device is only in the OMAP2 SoC, which we are removing. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 8 - hw/timer/omap_gptimer.c | 512 hw/timer/meson.build| 1 - 3 files

Re: [PATCH for-9.2 45/53] hw/timer: Remove omap_synctimer

On 3/9/24 18:07, Peter Maydell wrote: Remove the omap_synctimer device, which is only in the OMAP2 SoC. Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 8 --- hw/timer/omap_synctimer.c | 110 -- hw/timer/meson.build | 1 - 3 files c

Re: [External] RE: [PATCH v5 01/13] meson: Introduce new instruction set enqcmd to the build system.

On Mon, Jul 15, 2024 at 8:02 AM Liu, Yuan1 wrote: > > > -Original Message- > > From: Yichen Wang > > Sent: Friday, July 12, 2024 5:53 AM > > To: Paolo Bonzini ; Marc-André Lureau > > ; Daniel P. Berrangé ; > > Thomas Huth ; Philippe Mathieu-Daudé > > ; Peter Xu ; Fabiano Rosas > > ; Eric

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