Hi,
I want to know if I understand it correctly.
```
static void nvme_aio_err(NvmeRequest *req, int ret)
{
uint16_t status = NVME_SUCCESS;
Error *local_err = NULL;
switch (req->cmd.opcode) {
case NVME_CMD_READ:
case NVME_CMD_RESV_REPORT:
status = NVME_UNRECOVERED_READ;
break;
case NVME_CMD_FLUSH
On Tue, Aug 27, 2024 at 7:40 PM Cédric Le Goater wrote:
>
> Hello Clément,
>
> On 7/15/24 10:46, Clément Chigot wrote:
> > The BookE decrementer stops at 0, meaning that it won't decremented
> > towards "negative" values.
> > However, the current logic is inverted: decr is updated solely when
> >
On 27.08.24 20:41, Peter Xu wrote:
On Tue, Aug 27, 2024 at 08:00:07PM +0200, David Hildenbrand wrote:
On 27.08.24 19:57, Peter Xu wrote:
On Tue, Aug 27, 2024 at 10:37:15AM +0200, David Hildenbrand wrote:
/* Called with ram_list.mutex held */
-static void dirty_memory_extend(ram_addr_t old_r
05.03.2024 16:52, Peter Maydell wrote:
From: Richard Henderson
If translation is disabled, the default memory type is Device, which
requires alignment checking. This is more optimally done early via
the MemOp given to the TCG memory operation.
Reviewed-by: Philippe Mathieu-Daudé
Reported-by:
On Aug 28 00:20, 卢长奇 wrote:
> Hi,
>
> I want to know if I understand it correctly.
>
> ```
> static void nvme_aio_err(NvmeRequest *req, int ret)
> {
> uint16_t status = NVME_SUCCESS;
> Error *local_err = NULL;
>
> switch (req->cmd.opcode) {
> case NVME_CMD_READ:
> case NVME_CMD_RESV_REPORT:
> st
On Tue, Aug 27, 2024 at 05:37:00PM GMT, Philippe Mathieu-Daudé wrote:
> Hi,
>
> (old patch)
>
> On 24/6/21 12:38, Gerd Hoffmann wrote:
> > With target-specific modules we can have multiple modules implementing
> > the same object. Therefore we have to check the target arch on lookup
> > to find
Hi,
> But I think unexpected access shouldn't be there in the 1st place,
> so guard looks pretty legit at this point.
> Lets see what Gerd finds out from edk2 point of view.
CPU eject happens /after/ SMM syncronisation, when CPUs are on their way
back into normal mode:
* The boot processor wi
error_report() is more appropriate for error situations. Replace fprintf with
error_report() and error_printf() as appropriate. Cosmetic. No functional
change.
CC: qemu-triv...@nongnu.org
CC: zhao1@intel.com
CC: arm...@redhat.com
Reviewed-by: Zhao Liu
Signed-off-by: Ani Sinha
---
accel/kvm/
replace fprintf() with error_report() in kvm_init()
refactor code in kvm_init() to move core vm creation operation to its
own function.
CC: qemu-triv...@nongnu.org
CC: qemu-devel@nongnu.org
CC: zhao1@intel.com
CC: pbonz...@redhat.com
CC: arm...@redhat.com
Ani Sinha (2):
kvm: replace fprint
Refactoring the core logic around KVM_CREATE_VM into its own separate function
so that it can be called from other functions in future patches. There is
no functional change in this patch.
CC: pbonz...@redhat.com
CC: zhao1@intel.com
CC: cfont...@suse.de
CC: arm...@redhat.com
CC: qemu-triv...@n
Quoting Nico Boehr (2024-08-26 14:08:20)
> There was a little hickup without the fixup to patch 2, but after Nina
> pushed the fixup, we did not observe any failures related to your
> changes in our CI. Thanks!
Peter, after a few CI runs, we unfortunately did find some issues with your
patch :-(
On 27/08/2024 09.05, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Mon, Aug 12, 2024 at 05:38:41PM +0200, Thomas Huth wrote:
On 24/07/2024 11.47, Daniel P. Berrangé wrote:
The current TLS session I/O APIs just return a synthetic errno
value on error, which has been translated from a
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically
On 27/08/2024 18:51, Michael Tokarev wrote:
27.08.2024 15:09, Mark Cave-Ayland wrote:
On 27/08/2024 11:02, Michael Tokarev wrote:
in many cases, is only included for crc32 function,
and in some of them, there's a comment saying that, but in
a different way. In one place (hw/net/rtl8139.c),
As reported by Peter, we might be leaking memory when removing the
highest RAMBlock (in the weird ram_addr_t space), and adding a new one.
We will fail to realize that we already allocated bitmaps for more
dirty memory blocks, and effectively discard the pointers to them.
Fix it by getting rid of
If you create a new timer before the timer lists have been
initialised then you will end up with an abort due to trying
to access an illegal timer list struct. Add an assert() for
the timer list being NON-null.
Signed-off-by: Ben Dooks
---
util/qemu-timer.c | 1 +
1 file changed, 1 insertion(+)
Key Changes Compared to Version 3:
Minor comment changes and all the patches
have been reviewed by Richard Henderson
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU regi
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
configs/targets/riscv64-bsd-user.mak | 4
1 file changed, 4 insertions(+)
create mode 100644 configs/targets/risc
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_cpu.h | 14 ++
1 file changed, 14 insertions(+)
di
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_signal.h
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_sigtramp.h | 42 +++
1
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Prasad Pandit
Hello,
* virsh(1) offers multiple options to initiate Postcopy migration:
1) virsh migrate --postcopy --postcopy-after-precopy
2) virsh migrate --postcopy + virsh migrate-postcopy
3) virsh migrate --postcopy --timeout --timeout-postcopy
When Postcopy migration
From: Prasad Pandit
QEMU threads use vhost_user_write/read calls to send
and receive request/reply messages from a vhost-user
device. When multiple threads communicate with the
same vhost-user device, they can receive each other's
messages, resulting in an erroneous state.
When fault_thread exit
From: Prasad Pandit
While starting a vhost device, updating iotlb entries
via 'vhost_device_iotlb_miss' may return an error.
qemu-kvm: vhost_device_iotlb_miss:
700871,700871: Fail to update device iotlb
Fail device start when such an error occurs.
Signed-off-by: Prasad Pandit
---
hw/vi
Although it gives `undefined symbol: qemu_plugin_scoreboard_free`. But
probably I messed something up...
On Tue, Aug 27, 2024, 14:59 Elisha Hollander
wrote:
> Oh nice, I didn't know that
>
> On Tue, Aug 27, 2024, 12:39 Alex Bennée wrote:
>
>> Elisha Hollander writes:
>>
>> > Signed-off-by: Eli
Manos Pitsidianakis writes:
> From: Paolo Bonzini
>
> This is needed for Rust support.
Just a note that b4 will fail to apply this as lore hasn't archived the
binary patch. However it applies fine manually.
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Elisha Hollander writes:
> Although it gives `undefined symbol: qemu_plugin_scoreboard_free`. But
> probably I messed something up...
Are you using an older QEMU? We should trigger an API warning if they
are mismatched but maybe thats not working.
>
> On Tue, Aug 27, 2024, 14:59 Elisha Hollande
Hi Peter,
On Tue, Aug 20, 2024 at 1:56 PM Peter Maydell wrote:
>
> On Tue, 20 Aug 2024 at 12:40, David Hildenbrand wrote:
> >
> > On 14.08.24 14:32, Juraj Marcin wrote:
> > > On Tue, Aug 13, 2024 at 6:37 PM Peter Maydell
> > > wrote:
> > >>
> > >> On Tue, 13 Aug 2024 at 16:39, Juraj Marcin wr
On 8/28/24 17:22, Michael Tokarev wrote:
05.03.2024 16:52, Peter Maydell wrote:
From: Richard Henderson
If translation is disabled, the default memory type is Device, which
requires alignment checking. This is more optimally done early via
the MemOp given to the TCG memory operation.
Reviewe
On Wed, Aug 28, 2024 at 03:39:14PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> QEMU threads use vhost_user_write/read calls to send
> and receive request/reply messages from a vhost-user
> device. When multiple threads communicate with the
> same vhost-user device, they can receive each
This addition will be necessary for some HVF related work to follow.
For HVF on ARM there exists a set of APIs in macOS 13 to be able to
adjust the IPA size for a given VM. This is useful as by default HVF
uses 36 bits as the IPA size, so to support guests with > 64GB of RAM
we'll need to reach for
This patch's main focus is to use the previously added
hvf_get_physical_address_range to inform VM creation
about the IPA size we need for the VM, so we can extend
the default 36b IPA size and support VMs with 64+GB of
RAM. This is done by freezing the memory map, computing
the highest GPA and then
This is preliminary work to split up hv_vm_create
logic per platform so we can support creating VMs
with > 64GB of RAM on Apple Silicon machines. This
is done via ARM HVF's hv_vm_config_create() (and
other APIs that modify this config that will be
coming in future patches). This should have no
beha
This patchsets focus is on lighting up the ability to create VMs with 64+GB
of RAM through using some new APIs introduced in macOS 13. Due to the IPA sizes
supported in macOS, the first version we can properly support this requirement
is macOS 15 as (if the hardware supports it also) the kernel add
Ani Sinha writes:
> error_report() is more appropriate for error situations. Replace fprintf with
> error_report() and error_printf() as appropriate. Cosmetic. No functional
> change.
Uh, I missed this last time around: the change is more than just
cosmetics! The error messages change, e.g. fro
Manos Pitsidianakis writes:
> Add rust feature in meson.build, configure, to prepare for adding Rust
> code in the followup commits.
>
> Signed-off-by: Manos Pitsidianakis
> ---
> MAINTAINERS | 5 +
> meson.build | 25 -
> Kconfig
28.08.2024 14:07, Richard Henderson wrote:
On 8/28/24 17:22, Michael Tokarev wrote:
05.03.2024 16:52, Peter Maydell wrote:
From: Richard Henderson
If translation is disabled, the default memory type is Device, which
requires alignment checking. This is more optimally done early via
the MemOp
On 8/28/24 10:16, Deepak Gupta wrote:
This should be handled by a CPU reset, which is still called for linux
user mode.
It is the right place for setting priv to PRV_U?
or you want me to place it elsewhere ?
Sure
for reset values of *envcfg, I can rely on `riscv_cpu_reset_hold`
Doing this i
On Tue, 27 Aug 2024 09:40:05 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> When inserting multiple dynamic capacity event records grouped via More flag,
> we should only trigger interrupt after the last record is inserted into the
> event log. Achieving the goal by letting cxl_event_insert
On Tue, 27 Aug 2024 09:40:04 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Per cxl spec r3.1, for multiple dynamic capacity event records grouped via
> the More flag, the last record in the sequence should clear the More flag.
>
> Before the change, the More flag of the event record is cl
On 8/1/24 22:30, Michael Kowal wrote:
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles
PHYP uses 8-byte writes to the 2nd doubleword of the OS context
line when dispatching an OS level virtual processor. This
support was not used by OPAL/Linux and so was never added.
Without this support, the XIVE code doesn't notice that
Manos Pitsidianakis writes:
> From: Paolo Bonzini
>
> Include the correct path and arguments to rustc in the native
> and cross files (native compilation is needed for procedural
> macros).
>
> Signed-off-by: Paolo Bonzini
> ---
> configure | 50 ++
The skip parameter specifies the number of bytes to be skipped from the current
FIFO head before the peek or pop operation.
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/util/fifo8.c b/util/fifo8.c
index 5faa814a
The fifo8_pop_buf() function will soon also be used for peek operations, so
rename
the function accordingly. Create a new fifo8_pop_buf() wrapper function that can
be used by existing callers.
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 8 +++-
1 file changed, 7 insertions(+), 1 dele
This is to emphasise that the function returns a pointer to the internal FIFO
buffer.
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/fifo8.c b/util/fifo8.c
index 1ffa19d900..61bce9d9a0 100644
--- a/util/fifo8.c
++
Pass the do_pop value from fifo8_peekpop_buf() to fifo8_peekpop_bufptr() to
allow peeks to the FIFO buffer, including adjusting the skip parameter to
handle the case where the internal FIFO buffer wraps around.
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 4 ++--
1 file changed, 2 insertio
This tests the Fifo8 implementation for basic operations as well as testing for
the correct *_bufptr() including handling wraparound of the internal FIFO
buffer.
Signed-off-by: Mark Cave-Ayland
---
tests/unit/meson.build | 1 +
tests/unit/test-fifo.c | 256
This is a wrapper function around fifo8_peekpop_buf() that allows the caller to
peek into FIFO, including handling the case where there is a wraparound of the
internal FIFO buffer.
Signed-off-by: Mark Cave-Ayland
---
include/qemu/fifo8.h | 14 ++
util/fifo8.c | 5 +
2 fi
The upcoming peek functionality will require passing a non-zero value to
fifo8_peekpop_bufptr().
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/fifo8.c b/util/fifo8.c
index 62d6430b05..efe0117b1f 100644
--- a/util/fif
This is something I've had lying around for a little while as a follow on from
Phil's recent work on Fifo8 with a few updates, but also adding the missing
fifo8_peek() and fifo8_peek_buf() functions along with some relevant tests.
The reason for sending this now is that there are couple of recent
Rather than operate on fifo->head directly, introduce a new head variable which
is
set to the value of fifo->head and use it instead. This is to allow future
adjustment of the head position within the internal FIFO buffer.
Signed-off-by: Mark Cave-Ayland
---
util/fifo8.c | 7 ---
1 file cha
This allows uses to peek the byte at the current head of the FIFO.
Signed-off-by: Mark Cave-Ayland
---
include/qemu/fifo8.h | 11 +++
util/fifo8.c | 6 ++
2 files changed, 17 insertions(+)
diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h
index d09984b146..4f768d4ee3
On Wed, Aug 28, 2024 at 07:11:44AM +0300, Manos Pitsidianakis wrote:
> From: Paolo Bonzini
>
> Include the correct path and arguments to rustc in the native
> and cross files (native compilation is needed for procedural
> macros).
>
> Signed-off-by: Paolo Bonzini
> ---
> configure | 50 +
On 8/26/24 20:50, Guenter Roeck wrote:
Hi,
On 8/26/24 02:58, Cédric Le Goater wrote:
Hello Guenter,
On 8/9/24 00:05, Guenter Roeck wrote:
Hi,
On Tue, Jun 25, 2024 at 09:08:30AM +0200, Cédric Le Goater wrote:
The tacoma-bmc machine was a board including an AST2600 SoC based BMC
and a withers
Intel changes it's specification quite often e.g. the location and size
of the BDSM register has change for gen 11 devices and later. This
causes our emulation to fail on those devices. So, it's impossible for
us to use a suitable default value for unknown devices. Instead of
returning a random ge
The BDSM register is mirrored into MMIO space at least for gen 11 and
later devices. Unfortunately, the Windows driver reads the register
value from MMIO space instead of PCI config space for those devices [1].
Therefore, we either have to keep a 1:1 mapping for the host and guest
address or we ha
We're soon going to add support for legacy mode to ElkhartLake and
TigerLake devices. Those are gen 11 and 12 devices. At the moment, all
devices identified by our igd_gen function do support legacy mode. This
won't change when adding our new devices of gen 11 and 12. Therefore, it
makes more sens
Hi,
Qemu has experimental support for GPU passthrough of Intels integrated graphic
devices. Unfortunately, Intel has changed some bits for their gen 11 devices
and later. To support these devices, we have to account for those changes. This
patch series adds the missing bits on the Qemu side.
I'v
Intel changed the location and size of the BDSM register for gen 11
devices and later. We have to adjust our emulation for these devices to
properly support them.
Signed-off-by: Corvin Köhne
---
hw/vfio/igd.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
The stolen memory is required for the GOP (EFI) driver and the Windows
driver. While the GOP driver seems to work with any stolen memory size,
the Windows driver will crash if the size doesn't match the size
allocated by the host BIOS. For that reason, it doesn't make sense to
overwrite the stolen
> On 28 Aug 2024, at 4:53 PM, Markus Armbruster wrote:
>
> Ani Sinha writes:
>
>> error_report() is more appropriate for error situations. Replace fprintf with
>> error_report() and error_printf() as appropriate. Cosmetic. No functional
>> change.
>
> Uh, I missed this last time around: the
We have to update the calculation of the stolen memory size because
we've seen devices using values of 0xf0 and above for the graphics mode
select field. The new calculation was taken from the linux kernel [1].
[1]
https://github.com/torvalds/linux/blob/7c626ce4bae1ac14f60076d00eafe71af30450ba/a
ElkhartLake and TigerLake devices were tested in legacy mode with Linux
and Windows VMs. Both are working properly. It's likely that other Intel
GPUs of gen 11 and 12 like IceLake device are working too. However,
we're only adding known good devices for now.
Signed-off-by: Corvin Köhne
---
hw/v
error_report() is more appropriate for error situations. Replace fprintf with
error_report() and error_printf() as appropriate. Some improvement in error
reporting also happens as a part of this change. For example:
From:
$ ./qemu-system-x86_64 --accel kvm
Could not access KVM kernel module: No su
This is already merged, but I have two comments - one improvement
and one bug which we should probably fix before release.
On Mon, Aug 05, 2024 at 10:31:26AM +1000, Richard Henderson wrote:
> From: Clément Léger
>
> In order to make it cleaner, split qemu_close_all_open_fd() logic into
> multipl
Peter Xu writes:
> On Tue, Aug 27, 2024 at 05:22:32PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Tue, Aug 27, 2024 at 04:17:59PM -0300, Fabiano Rosas wrote:
>> >> Peter Xu writes:
>> >>
>> >> > On Tue, Aug 27, 2024 at 03:54:51PM -0300, Fabiano Rosas wrote:
>> >> >> Peter Xu w
On 8/28/24 14:50, Corvin Köhne wrote:
On Wed, 2024-08-28 at 12:40 +0200, Corvin Köhne wrote:
On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote:
PS - please drop the confidential email warning signature when
posting
to public lists.
Sry for the noise. I can't drop it, so I'm going to
Manos Pitsidianakis writes:
> Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and
> provides some declaration macros for symbols visible to the rest of
> QEMU.
As mentioned on IRC I'm hitting a compilation error that bisects to this
commit:
[148/1010] Generating bindings
On Wed, Aug 28, 2024 at 02:33:59PM +0900, Akihiko Odaki wrote:
> On 2024/08/28 1:11, Peter Xu wrote:
> > On Tue, Aug 27, 2024 at 01:14:51PM +0900, Akihiko Odaki wrote:
> > > On 2024/08/27 4:42, Peter Xu wrote:
> > > > On Mon, Aug 26, 2024 at 06:10:25PM +0100, Peter Maydell wrote:
> > > > > On Mon,
On 28/08/2024 14:48, Daniel P. Berrangé wrote:
> This is already merged, but I have two comments - one improvement
> and one bug which we should probably fix before release.
>
> On Mon, Aug 05, 2024 at 10:31:26AM +1000, Richard Henderson wrote:
>> From: Clément Léger
>>
>> In order to make it
On Wed, Aug 28, 2024 at 10:04:47AM -0300, Fabiano Rosas wrote:
> We merged most of these things already. Now even if rpms show up at some
> point we still have to deal with not being able to build that code until
> then. Perhaps we could have a container that has all of these
> pre-installed just t
Manos Pitsidianakis writes:
> Rust crates, introduced from the next commit onwards, use the glib
> allocator API and need to know whether g_aligned_alloc etc are
> available.
>
> This commit adds a define in config_host_data that depends on glib
> version >= 2.72.
>
> Signed-off-by: Manos Pitsidi
Ani Sinha writes:
>> On 28 Aug 2024, at 4:53 PM, Markus Armbruster wrote:
>>
>> Ani Sinha writes:
>>
>>> error_report() is more appropriate for error situations. Replace fprintf
>>> with
>>> error_report() and error_printf() as appropriate. Cosmetic. No functional
>>> change.
>>
>> Uh, I mi
Manos Pitsidianakis writes:
> Hello everyone,
>
> This series adds:
>
> - build system support for the Rust compiler
> - a small Rust library, qemu-api, which includes bindings to QEMU's C
> interface generated with bindgen, and qemu-api-macros, a procedural
> macro library.
> - a proof of co
On Wed, 2024-08-28 at 12:40 +0200, Corvin Köhne wrote:
> On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote:
> >
> > PS - please drop the confidential email warning signature when
> > posting
> > to public lists.
> >
>
> Sry for the noise. I can't drop it, so I'm going to use another mail
On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote:
> CAUTION: External Email!!
> On Thu, 22 Aug 2024 13:08:29 +0200
> Corvin Köhne wrote:
>
> > The BDSM register is mirrored into MMIO space at least for gen 11
> > and
> > later devices. Unfortunately, the Windows driver reads the register
On 11.08.24 20:55, Michael Tokarev wrote:
12.07.2024 17:07, Fiona Ebner wrote:
Allow overlapping request by removing the assert that made it
impossible. There are only two callers:
1. block_copy_task_create()
It already asserts the very same condition before calling
reqlist_init_req().
2. cbw
ElkhartLake and TigerLake devices were tested in legacy mode with Linux
and Windows VMs. Both are working properly. It's likely that other Intel
GPUs of gen 11 and 12 like IceLake device are working too. However,
we're only adding known good devices for now.
Signed-off-by: Corvin Köhne
---
hw/vf
We're soon going to add support for legacy mode to ElkhartLake and
TigerLake devices. Those are gen 11 and 12 devices. At the moment, all
devices identified by our igd_gen function do support legacy mode. This
won't change when adding our new devices of gen 11 and 12. Therefore, it
makes more sense
We have to update the calculation of the stolen memory size because
we've seen devices using values of 0xf0 and above for the graphics mode
select field. The new calculation was taken from the linux kernel [1].
[1]
https://github.com/torvalds/linux/blob/7c626ce4bae1ac14f60076d00eafe71af30450ba/ar
Hi,
Qemu has experimental support for GPU passthrough of Intels integrated graphic
devices. Unfortunately, Intel has changed some bits for their gen 11 devices
and later. To support these devices, we have to account for those changes. This
patch series adds the missing bits on the Qemu side.
I've
Intel changed the location and size of the BDSM register for gen 11
devices and later. We have to adjust our emulation for these devices to
properly support them.
Signed-off-by: Corvin Köhne
---
hw/vfio/igd.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
The BDSM register is mirrored into MMIO space at least for gen 11 and
later devices. Unfortunately, the Windows driver reads the register
value from MMIO space instead of PCI config space for those devices [1].
Therefore, we either have to keep a 1:1 mapping for the host and guest
address or we hav
Intel changes it's specification quite often e.g. the location and size
of the BDSM register has change for gen 11 devices and later. This
causes our emulation to fail on those devices. So, it's impossible for
us to use a suitable default value for unknown devices. Instead of
returning a random gen
The stolen memory is required for the GOP (EFI) driver and the Windows
driver. While the GOP driver seems to work with any stolen memory size,
the Windows driver will crash if the size doesn't match the size
allocated by the host BIOS. For that reason, it doesn't make sense to
overwrite the stolen
On 2024/08/28 22:09, Peter Xu wrote:
On Wed, Aug 28, 2024 at 02:33:59PM +0900, Akihiko Odaki wrote:
On 2024/08/28 1:11, Peter Xu wrote:
On Tue, Aug 27, 2024 at 01:14:51PM +0900, Akihiko Odaki wrote:
On 2024/08/27 4:42, Peter Xu wrote:
On Mon, Aug 26, 2024 at 06:10:25PM +0100, Peter Maydell wr
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