Hello Stafford,
On 23.08.24 08:28, Stafford Horne wrote:
> Note the distribution list you use here: openr...@lists.librecores.org
> Is old and we should use linux-openr...@vger.kernel.org. I will get the qemu
> maintainer file updated.
So this list is appropriate for all openrisc-related develop
Hi,
On 21/8/24 10:27, Thomas Huth wrote:
From: Daniel P. Berrangé
Many tests need to access assets stored on remote sites. We don't want
to download these during test execution when run by meson, since this
risks hitting test timeouts when data transfers are slow.
Add support for pre-emptive
For virtio VGA deivce libvirt will select VIRTIO_VGA firstly rather than
VIRTIO_GPU, VIRTIO_VGA device supports frame buffer however it requires
legacy VGA compatible support. Frame buffer area 0xa -- 0xc
conflicts with low memory area 0 -- 0x1000.
Here remove default support for VIRTI
From: Paolo Bonzini
Include the correct path and arguments to rustc in the native
and cross files (native compilation is needed for procedural
macros).
Signed-off-by: Paolo Bonzini
---
configure | 50 --
meson.build | 8 +++-
2 files chang
Hello everyone,
This series adds:
- build system support for the Rust compiler
- a small Rust library, qemu-api, which includes bindings to QEMU's C
interface generated with bindgen, and qemu-api-macros, a procedural
macro library.
- a proof of concept ARM PL011 device implementation in Rust,
Add bindings_rs target for generating rust bindings to target-independent
qemu C APIs.
The bindings need be created before any rust crate that uses them is
compiled.
The bindings.rs file will end up in BUILDDIR/bindings.rs and have the
same name as a target:
ninja bindings.rs
Signed-off-by: P
Set rust source code to diff=rust (built-in with new git versions)
and merge=binary for Cargo.lock files (they should not be merged but
auto-generated by cargo)
Reviewed-by: Alex Bennée
Reviewed-by: Zhao Liu
Signed-off-by: Manos Pitsidianakis
---
.gitattributes | 3 +++
1 file changed, 3 inser
Add rust feature in meson.build, configure, to prepare for adding Rust
code in the followup commits.
Signed-off-by: Manos Pitsidianakis
---
MAINTAINERS | 5 +
meson.build | 25 -
Kconfig | 1 +
Kconfig.host
This commit adds a re-implementation of hw/char/pl011.c in Rust.
How to build:
1. Configure a QEMU build with:
--enable-system --target-list=aarch64-softmmu --enable-rust
2. Launching a VM with qemu-system-aarch64 should use the Rust version
of the pl011 device
Co-authored-by: Junjie Mao
From: Paolo Bonzini
This is needed for Rust support.
Signed-off-by: Paolo Bonzini
---
meson.build| 2 +-
python/scripts/vendor.py | 4 ++--
python/wheels/meson-1.2.3-py3-none-any.whl | Bin 964928 -> 0 bytes
python/wheels/meson-1.5.0-py3-no
Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and
provides some declaration macros for symbols visible to the rest of
QEMU.
Co-authored-by: Junjie Mao
Co-authored-by: Paolo Bonzini
Signed-off-by: Junjie Mao
Signed-off-by: Paolo Bonzini
Signed-off-by: Manos Pitsidianakis
This commit adds a helper crate library, qemu-api-macros for derive (and
other procedural) macros to be used along qemu-api.
It needs to be a separate library because in Rust, procedural macros, or
macros that can generate arbitrary code, need to be special separate
compilation units.
Only one ma
Straight forward conversion. Update the SHA1 hash to
SHA256 since SHA1 should not be used anymore nowadays.
Provide get_qemu_img() helper in qemu_test.
$ make check-functional-aarch64 V=1
...
▶ 1/4 test_aarch64_virt.Aarch64VirtMachine.test_aarch64_virt_gicv2
OK
▶ 1/4 test
On 22/8/24 14:41, Thomas Huth wrote:
On 22/08/2024 14.07, Philippe Mathieu-Daudé wrote:
Straight forward conversion. Update the SHA1 hash to
SHA256 since SHA1 should not be used anymore nowadays.
Use has_cmd() and run_cmd() methods from qemu_test.
$ make check-functional-aarch64 V=1
...
On Thu, Aug 22, 2024 at 6:21 PM Peter Maydell
wrote:
> This patchset fixes a collection of minor memory leaks in
> various xlnx devices, all detected by clang LeakSanitizer
> when running 'make check'. Since these are longstanding
> and not very important leaks, this is 9.2 material.
>
>
All of i
From: David Woodhouse
The vmclock device addresses the problem of live migration with
precision clocks. The tolerances of a hardware counter (e.g. TSC) are
typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that
counter against an external source of 'real' time, and track the pre
On Thu, Aug 22, 2024 at 05:21:22PM +0100, Peter Maydell wrote:
> Since the TYPE_XNLX_VERSAL_CFU_FDRO device creates a FIFO in its
> instance_init method, we must destroy the FIFO in instance_finalize
> to avoid a memory leak for the QOM introspection
> "instantiate-examine-finalize" cycle:
>
> Dir
On Thu, Aug 22, 2024 at 05:21:27PM +0100, Peter Maydell wrote:
> The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with
> register_init_block32() in its instance_init method; we must
> therefore destroy it in our instance_finalize method to avoid a leak
> in the QOM introspection "ini
Pierrick Bouvier writes:
> Hi Rowan, thanks for your contribution.
>
> To give some context on the answer, we are currently working to add a
> similar "read_memory" API, but associated to memory callbacks for
> plugins
> (https://lore.kernel.org/qemu-devel/20240724194708.1843704-1-pierrick.bouv..
Hi Sail,
On 8/22/24 8:58 PM, Salil Mehta wrote:
On 8/21/24 8:23 PM, Salil Mehta wrote:
>>
>> On 8/21/24 2:40 AM, Salil Mehta wrote:
>> >
>> > I don’t understand this clearly. Are you suggesting to reuse only
>> > single vCPU object to initialize all KVM vCPUs not yet plugged
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/93
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardwar
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test-allowed
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
accommodate the SPCR Table revision 4.
[1]:
https://learn.microsoft.com/en-u
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test-allowed
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/93
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]:
https://learn.microsoft.com/en-us/windows-hardwar
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
accommodate the SPCR Table revision 4.
[1]:
https://learn.microsoft.com/en-u
Akihiko Odaki writes:
> This fixes LeakSanitizer warnings.
>
> Signed-off-by: Akihiko Odaki
> Reviewed-by: Peter Xu
> Reviewed-by: Michael S. Tsirkin
> ---
> migration/savevm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/migration/savevm.c b/migration/savevm.c
> index deb57833f
On 8/20/24 12:16 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On 21/8/24 10:27, Thomas Huth wrote:
Provide a meson.build file for the upcoming python-based functional
tests, and add some wrapper glue targets to the tests/Makefile.include
file. We are going to use two "speed" modes for the functional tests:
The "quick" tests can be run at any time (i.e. also
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function. It introduces three layers of caches and modifies the cache
description registers accordingly. Additionally, a new function is added
to handle cache description when CCIDX is disabled. The CCIDX remains
disabled for cp
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
On Fri, Aug 23, 2024 at 04:31:40AM -0700, Sia Jee Heng wrote:
> Signed-off-by: Sia Jee Heng
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-diff.h
>
On 22/8/24 16:06, Marcin Juszkiewicz wrote:
On 22.08.2024 13:41, Philippe Mathieu-Daudé wrote:
# Timeouts for individual tests that can be slow e.g. with debugging
enabled
test_timeouts = {
+ 'aarch64_sbsaref' : 180,
What kind of machine is able to run those tests in 180s? I bumped them
On Fri, Aug 23, 2024 at 04:31:41AM -0700, Sia Jee Heng wrote:
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> [1]:
> https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port
Straight forward conversion. Since SBSA_FLASH files are not
tarballs, use lzma_uncompress() method.
Avocado used to set a timeout of 11 tests * 180s = 1980s.
Hopefully 600s should be sufficient.
Running on macOS Sonoma / Apple silicon M1:
$ QEMU_TEST_TIMEOUT_EXPECTED=1 make check-functional-aa
On 23/8/24 15:16, Philippe Mathieu-Daudé wrote:
Straight forward conversion. Since SBSA_FLASH files are not
tarballs, use lzma_uncompress() method.
Avocado used to set a timeout of 11 tests * 180s = 1980s.
Hopefully 600s should be sufficient.
Running on macOS Sonoma / Apple silicon M1:
$ QE
Hi Gavin,
> From: Gavin Shan
> Sent: Friday, August 23, 2024 11:52 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> Hi Sail,
>
> On 8/22/24 8:58 PM, Salil Mehta wrote:
> >> On 8/21/24 8:23 PM, Salil Mehta wrote:
> >> >>
> >> >> On 8/21/
I've been studying the example given in `contrib/vhost-user-blk`, and trying to
match the code to what is in the standard
(https://docs.oasis-open.org/virtio/virtio/v1.3/csd01/virtio-v1.3-csd01.html#x1-3050002),
so I can use the code to create my own vhost-user-vsock server.
I think I almost u
On Fri, Aug 23, 2024 at 04:31:42AM -0700, Sia Jee Heng wrote:
> Update the virt SPCR golden reference file for RISC-V to accommodate the
> SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
> latest ACPICA repository. The SPCR table has been modified to
> adhere to the revision
Hi,
Thank you once again!
> It's still not entirely clear to me what the situation is here. When the
> migration reaches pre-switchover state the VM is stopped, so there would
> be no more IO happening. Is this a matter of a race condition (of sorts)
> because pre-switchover happens while the blo
Hello,
Here is more data if my earlier mail did not provide enough details. I
apologize for not providing the critical data points in my previous mail.
- Created a file (dd if=/dev/urandom of=/orig.img bs=1M count=1000) before
starting live migration
- Started migration with block-job-cancel co
From: Haoran Zhang
fix vhost_user_gpu_chr_read() where `size` was incorrectly passed to
`msg->flags`.
Fixes: 267f664658 ("hw/display: add vhost-user-vga & gpu-pci")
Signed-off-by: Haoran Zhang
Reviewed-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael Tokarev
Si
The following changes since commit 407f9a4b121eb65166375c410e14d7b704bc1106:
Update version for v9.1.0-rc3 release (2024-08-22 15:07:32 +1000)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
for you to fetch changes up to d6192f3f7593536a4
From: Ani Sinha
Cosmetic: add comments in x86_load_linux() pointing to the kernel documentation
so that users can better understand the code.
CC: qemu-triv...@nongnu.org
Signed-off-by: Ani Sinha
Reviewed-by: Zhao Liu
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
---
hw/i386/x8
From: Peter Maydell
In commit 412d294ffdc we tried to improve the error message printed when
the machine type is unknown, but we used the wrong variable, resulting in:
$ ./build/x86/qemu-system-aarch64 -M bang
qemu-system-aarch64: unsupported machine type: "(null)"
Use -machine help to list supp
Hi Jee Heng,
On Fri, Aug 23, 2024 at 04:31:39AM -0700, Sia Jee Heng wrote:
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> Meanwhile, the virt SPCR golden reference file for RISC-V have been update
"Arisetty, Chakri" writes:
> Hello,
>
> Here is more data if my earlier mail did not provide enough details. I
> apologize for not providing the critical data points in my previous mail.
>
> - Created a file (dd if=/dev/urandom of=/orig.img bs=1M count=1000) before
> starting live migration
> -
On 23.08.2024 15:16, Philippe Mathieu-Daudé wrote:
Straight forward conversion. Since SBSA_FLASH files are not
tarballs, use lzma_uncompress() method.
Avocado used to set a timeout of 11 tests * 180s = 1980s.
Hopefully 600s should be sufficient.
Running on macOS Sonoma / Apple silicon M1:
$
On Thu, Aug 22, 2024 at 05:21:24PM +0100, Peter Maydell wrote:
> The TYPE_XLNX_BBRAM device creates a register block with
> register_init_block32() in its instance_init method; we must
> therefore destroy it in our instance_finalize method to avoid a leak
> in the QOM introspection "init-inspect-fi
On Thu, Aug 22, 2024 at 05:21:25PM +0100, Peter Maydell wrote:
> The TYPE_XLNX_ZYNQMP_EFUSE device creates a register block with
> register_init_block32() in its instance_init method; we must
> therefore destroy it in our instance_finalize method to avoid a leak
> in the QOM introspection "init-ins
On Thu, Aug 22, 2024 at 05:21:26PM +0100, Peter Maydell wrote:
> The TYPE_XLNX_VERSAL_TRNG device creates a register block with
> register_init_block32() in its instance_init method; we must
> therefore destroy it in our instance_finalize method to avoid a leak
> in the QOM introspection "init-insp
On Thu, Aug 22, 2024 at 05:21:27PM +0100, Peter Maydell wrote:
> The TYPE_XLNX_VERSAL_EFUSE_CTRL device creates a register block with
> register_init_block32() in its instance_init method; we must
> therefore destroy it in our instance_finalize method to avoid a leak
> in the QOM introspection "ini
On Fri, Aug 16, 2024 at 09:35:03AM -0700, Doug Brown wrote:
> Previously the emulated CAN ID register was being set to the exact same
> value stored in qemu_can_frame.can_id. This doesn't work correctly
> because the Xilinx IP core uses a different bit arrangement than
> qemu_can_frame for all of i
Hi folks,
Sorry for the ping, but any thoughts on this? I mainly implemented
what was discussed in the upstream bug[0].
Let me know what you think or any suggestions for this.
Thank you,
Tiago
[0] https://gitlab.com/qemu-project/qemu/-/issues/2398
On Tue, Aug 13, 2024 at 10:19 AM Tiago Pasqual
On 8/20/24 12:27 PM, Jason Chien wrote:
Hi Daniel,
On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are m
On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote:
> Convert the virtio-ccw code to three-phase reset. This allows us to
> remove a call to device_class_set_parent_reset(), replacing it with
> the three-phase equivalent resettable_class_set_parent_phases().
> Removing all the device_class_set
The MultiFD*Params structures are for per-channel data. Constant
values should not be there because that needlessly wastes cycles and
storage. The page_size and page_count fall into this category so move
them inline in multifd.h.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/
Skip saving and loading any ram data in the packet in the case of a
SYNC. This fixes a shortcoming of the current code which requires a
reset of the MultiFDPages_t fields right after the previous
pending_job finishes, otherwise the very next job might be a SYNC and
multifd_send_fill_packet() will p
Multifd currently has a simple scheduling mechanism that distributes
work to the various channels by keeping storage space within each
channel and an extra space that is given to the client. Each time the
client fills the space with data and calls into multifd, that space is
given to the next idle
All references to pages are being removed from the multifd worker
threads in order to allow multifd to deal with different payload
types.
multifd_send_zero_page_detect() is called by all multifd migration
paths that deal with pages and is the last spot where zero pages and
normal page amounts are
The total_normal_pages and total_zero_pages elements are used only for
the end tracepoints of the multifd threads. These are not super useful
since they record per-channel numbers and are just the sum of all the
pages that are transmitted per-packet, for which we already have
tracepoints. Remove th
We want multifd to be able to handle more types of data than just ram
pages. To start decoupling multifd from pages, replace p->pages
(MultiFDPages_t) with the new type MultiFDSendData that hides the
client payload inside an union.
The general idea here is to isolate functions that *need* to handl
I'm about to replace the p->pages pointer with an opaque pointer, so
do a cleanup now to reduce direct accesses to p->page, which makes the
next diffs cleaner.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/multifd-qpl.c | 8 +---
migration/multifd-uadk.c | 9 +
We want to stop dereferencing 'pages' so it can be replaced by an
opaque pointer in the next patches.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/file.c| 3 ++-
migration/file.h| 2 +-
migration/multifd.c | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
dif
In preparation for adding new payload types to multifd, move most of
the no-compression code into multifd-nocomp.c. Let's try to keep a
semblance of layering by not mixing general multifd control flow with
the details of transmitting pages of ram.
There are still some pieces leftover, namely the p
This value never changes and is always the same as page_count. We
don't need a copy of it per-channel plus one in the extra slot. Remove
it.
Reviewed-by: Peter Xu
Signed-off-by: Fabiano Rosas
---
migration/multifd.c | 6 ++
migration/multifd.h | 2 --
2 files changed, 2 insertions(+), 6 del
Separate the multifd sync from flushing the client data to the
channels. These two operations are closely related but not strictly
necessary to be executed together.
The multifd sync is intrinsic to how multifd works. The multiple
channels operate independently and may finish IO out of order in
re
Add a new data structure to replace p->pages in the multifd
channel. This new structure will hide the multifd payload type behind
an union, so we don't need to add a new field to the channel each time
we want to handle a different data type.
This also allow us to keep multifd_send_pages() as is, w
While we cannot yet disentangle the multifd packet from page data, we
can make the code a bit cleaner by setting the page-related fields in
a separate function.
Signed-off-by: Fabiano Rosas
---
migration/multifd.c| 99 +-
migration/trace-events | 5 ++
We're about to use MultiFDPages_t from inside the MultiFDSendData
payload union, which means we cannot have pointers to allocated data
inside the pages structure, otherwise we'd lose the reference to that
memory once another payload type touches the union. Move the offset
array into the end of the
Prior to moving the ram code into multifd-nocomp.c, change the code to
register the nocomp ops dynamically so we don't need to have the ops
structure defined in multifd.c.
While here, move the ops struct initialization to the end of the file
to make the next diff cleaner.
Signed-off-by: Fabiano R
Hi,
Not much changed sinced v3, the most notable is that I kept the nocomp
names and created multifd-nocomp.c. I think "plain" is even more
misterious, so let's keep what we are already used to.
CI run: https://gitlab.com/farosas/qemu/-/pipelines/1425141484
v3:
https://lore.kernel.org/r/20240801
Add the multifd_ prefix to all functions and remove the useless
docstrings.
Signed-off-by: Fabiano Rosas
---
migration/multifd-qpl.c | 57
migration/multifd-uadk.c | 55 ---
migration/multifd-zlib.c | 81 ++
On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote:
> Convert the s390 CPU to the Resettable interface. This is slightly
> more involved than the other CPU types were (see commits
> 9130cade5fc22..d66e64dd006df) because S390 has its own set of
> different kinds of reset with different behaviou
On Fri, Aug 16, 2024 at 09:35:04AM -0700, Doug Brown wrote:
> The endianness of the CAN data was backwards in each group of 4 bytes.
> For example, the following data:
>
> 00 11 22 33 44 55 66 77
>
> was showing up like this:
>
> 33 22 11 00 77 66 55 44
>
> Fix both the TX and RX code to put th
On Fri, Aug 16, 2024 at 09:35:05AM -0700, Doug Brown wrote:
> There was no case for handling received CAN FD frames with a DLC of 0-8.
> This was already handled properly with TX. Add similar code for RX.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-v
elp state is recorded in *status on trap entry (less privilege to higher
privilege) and restored in elp from *status on trap exit (higher to less
privilege).
Additionally this patch introduces a forward cfi helper function to
determine if current privilege has forward cfi is enabled or not based o
zicfiss [1] riscv cpu extension enables backward control flow integrity.
This patch sets up space for zicfiss extension in cpuconfig. And imple-
ments dependency on A, zicsr, zimop and zcmop extensions.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Sh
zicfilp [1] riscv cpu extension enables forward control flow integrity.
If enabled, all indirect calls must land on a landing pad instruction.
This patch sets up space for zicfilp extension in cpuconfig. zicfilp
is dependend on zicsr.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepa
Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used during
unwind to get extra information about instruction like how to massage
exceptions. Updated all callsites as well.
Signed-off-by: Deepak Gupta
---
target/r
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak
zicfiss has following instructions
- sspopchk: pops a value from shadow stack and compares with x1/x5.
If they dont match, reports a sw check exception with tval = 3.
- sspush: pushes value in x1/x5 on shadow stack
- ssrdp: reads current shadow stack
- ssamoswap: swaps contents of shadow sta
Shadow stack instructions can be decoded as zimop / zcmop or shadow stack
instructions depending on whether shadow stack are enabled at current
privilege. This requires a TB flag so that correct TB generation and correct
TB lookup happens. `DisasContext` gets a field indicating whether bcfi is
enab
Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap.
Disasembly is only enabled if zimop and zicfiss ext is set to true.
Signed-off-by: Deepak Gupta
---
disas/riscv.c | 40 +++-
disas/riscv.h | 1 +
2 files changed, 40 insertions(+), 1 deletion(-)
dif
sw check exception support was recently added. This patch further augments
sw check exception by providing support for additional code which is
provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
sw check exception is raised *tval gets the value deposited in
`sw_check_code`.
Si
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Shu
Co-developed-by: Andy Chiu
Reviewed-by: Richard Henderson
---
disas/riscv.c | 18 +-
disas/riscv.h | 2 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index c8364c2b07..c7c92a
zicfiss introduces a new state ssp ("shadow stack register") in cpu.
ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds
virtual address for shadow stack as programmed by software.
Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs.
Shadow stack can be enabled for a m
zicfiss protects shadow stack using new page table encodings PTE.W=0,
PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
implemented or if shadow stack are not enabled.
Loads on shadow stack memory are allowed while stores to shadow stack
memory leads to access faults. Shadow stack ac
zicfilp protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpad`. If
target of an indirect call or jmp is not `lpad` then cpu/hart must raise
a sw check exception with tval = 2.
This patch implements the mechanism using TCG. Ta
Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, . This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in
sspush and sspopchk have equivalent compressed encoding taken from zcmop.
cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
for both rs1 and rs2 from space bitfield, this required a new codec.
Signed-off-by: Deepak Gupta
---
disas/riscv.c | 19 ++-
disas/ri
zicfilp introduces a new state elp ("expected landing pad") in cpu.
During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
LP_EXPECTED, only a subsquent landing pad instruction can set state back
to NO_LP_EXPECTED
This patch adds one more word for tcg compile which can be obtained during
unwind time to determine fault type for original operation (example AMO).
Depending on that, fault can be promoted to store/AMO fault.
Signed-off-by: Deepak Gupta
Suggested-by: Richard Henderson
---
target/riscv/cpu.h
v8 for riscv zicfilp and zicfiss extensions support in qemu.
Links for previous versions
[1] - v1 https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html
[2] - v2
https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa958803...@linaro.org/T/
[3] - v3 https://lists.nongnu.org/archiv
On Fri, 23 Aug 2024 at 18:45, Nina Schoetterl-Glausch
wrote:
>
> On Tue, 2024-08-13 at 17:52 +0100, Peter Maydell wrote:
> > Convert the s390 CPU to the Resettable interface. This is slightly
> > more involved than the other CPU types were (see commits
> > 9130cade5fc22..d66e64dd006df) because S
On 8/22/24 9:32 PM, Alistair Francis wrote:
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9
On 8/23/24 3:34 AM, Vladimir Isaev wrote:
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x because privilege spec
version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not en
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