On Thu, Aug 15, 2024 at 5:18 PM Peter Maydell
wrote:
> On Mon, 29 Jul 2024 at 10:35, Peter Maydell
> wrote:
> >
> > On Mon, 29 Jul 2024 at 08:40, Konstantin Kostiuk
> wrote:
> > >
> > > Hi Peter,
> > >
> > > How to see the full coverity report? In
> https://gitlab.com/qemu-project/qemu/-/artifa
The two limit_max variables represent size - 1, just like the
encoding in the GDT, thus the 'old' access was off by one.
Access the minimal size of the new tss: the complete tss contains
the iopb, which may be a larger block than the access api expects,
and irrelevant because the iopb is not access
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240819-1
for you to fetch changes up to 6df664f87c738788891f3bda701e63e23a0dbbc2:
Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" (2024-08-19 14:34:49
+1000)
---
On Mon, Aug 19, 2024 at 11:19:18AM GMT, Alistair Francis wrote:
> On Sat, Aug 17, 2024 at 2:08 AM Andrew Jones wrote:
> >
> > Older firmwares and OS kernels which use deprecated device tree
> > properties or are missing support for new properties may not be
> > tolerant of fully compliant device t
From: lxx <1733205...@qq.com>
This patch adds support for the Zilsd and Zclsd extension,
which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0
Co-developed-by: SUN Dongya
Co-developed-by: LIU Xu
Co-developed-by: ZHAO Fujin
---
target/riscv/cpu.c
Fix for the last reply:
https://lists.gnu.org/archive/html/qemu-devel/2024-08/msg02469.html
lxx (1):
target/riscv: Add Zilsd and Zclsd extension support
target/riscv/cpu.c| 4 +
target/riscv/cpu_cfg.h| 2 +
target/riscv/insn16.decode
On 8/19/24 17:50, Andrew Jones wrote:
I agree we should deprecate the invalid DT usage, with the goal of only
generating DTs that make the validator happy. I'm not sure how long that
deprecation period should be, though. It may need to be a while since
we'll need to decide when we've waited long
On 2024/8/15 13:48, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Subject: Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-
selective PASID-based iotlb invalidation
On 2024/8/5 14:27, Zhenzhong Duan wrote:
Per spec 6.5.2.4, PADID-selective PASID-based iotl
On 18.08.24 13:42, Dorjoy Chowdhury wrote:
Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves for
stripped down TPM functionality like cryptographic attestation. The
requests to and responses from NSM device are CBOR[2] encoded.
This commit adds support for NSM device in QEMU. Al
On 2024/8/15 11:46, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Subject: Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control
FS1GP cap bit setting
On 2024/8/5 14:27, Zhenzhong Duan wrote:
When host IOMMU doesn't support FS1GP but vIOMMU does, host
IOMMU
On 2024/8/5 14:27, Zhenzhong Duan wrote:
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
Perhaps I have asked it in the before. :) To me, such emulated devices
should implement an ATS-capa
W dniu 16.08.2024 o 18:13, Peter Maydell pisze:
Now that our SMMU model supports enabling both stages of translation
at once, we can enable this in the sbsa-ref board. Existing guest
code that only programs stage 1 and doesn't care about stage 2 should
continue to run with the same behaviour, bu
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control
>FS1GP cap bit setting
>
>On 2024/8/15 11:46, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Liu, Yi L
>>> Subject: Re: [PATCH v2 16/17] intel_iommu: I
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH v2 13/17] intel_iommu: piotlb invalidation should
>notify unmap
>
>On 2024/8/5 14:27, Zhenzhong Duan wrote:
>> This is used by some emulated devices which caches address
>> translation result. When piotlb invalidation issued in gu
Hi Peter,
On 8/16/24 18:13, Peter Maydell wrote:
> This patchset enables support for nested (two stage) translations
> in the SMMU in the virt and sbsa-ref boards.
>
> Patch 1 is Cornelia's compat-machine machinery patch, which we
> need to make this change only happen for virt-9.2 and later;
> pa
Hey Dorjoy,
On 18.08.24 13:42, Dorjoy Chowdhury wrote:
AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
is used for stripped down TPM functionality like attestation. This commit
adds the built-in NSM device in the nitro-enclave machine type.
In Nitro Enclaves, all the PCR
On Sun, Aug 18, 2024 at 05:42:56PM +0600, Dorjoy Chowdhury wrote:
> QEMU requires minimum glib version 2.66.0 as per the root meson.build
> file and per glib documentation[1] G_CHECKSUM_SHA384 is available since
> 2.51.
>
> [1] https://docs.gtk.org/glib/enum.ChecksumType.html
>
> Signed-off-by: D
On 19/8/24 07:30, Thomas Huth wrote:
On 16/08/2024 19.18, Philippe Mathieu-Daudé wrote:
On 16/8/24 18:40, Thomas Huth wrote:
On 16/08/2024 18.34, Philippe Mathieu-Daudé wrote:
On 16/8/24 17:37, Thomas Huth wrote:
The qtests are broken since a while in the MSYS2 job in the gitlab-CI,
likely du
On Sun, Aug 18, 2024 at 05:42:55PM +0600, Dorjoy Chowdhury wrote:
> AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
> is used for stripped down TPM functionality like attestation. This commit
> adds the built-in NSM device in the nitro-enclave machine type.
>
> In Nitro Enc
On 19/08/2024 12.21, Philippe Mathieu-Daudé wrote:
On 19/8/24 07:30, Thomas Huth wrote:
On 16/08/2024 19.18, Philippe Mathieu-Daudé wrote:
On 16/8/24 18:40, Thomas Huth wrote:
On 16/08/2024 18.34, Philippe Mathieu-Daudé wrote:
On 16/8/24 17:37, Thomas Huth wrote:
The qtests are broken since
On Sun, Aug 18, 2024 at 05:42:54PM +0600, Dorjoy Chowdhury wrote:
> Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves for
> stripped down TPM functionality like cryptographic attestation. The
> requests to and responses from NSM device are CBOR[2] encoded.
>
> This commit adds supp
On Fri, 16 Aug 2024 09:37:33 +0200
Mauro Carvalho Chehab wrote:
> Adds a generic error device to handle generic hardware error
> events as specified at ACPI 6.5 specification at 18.3.2.7.2:
> https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-so
Signed-off-by: Philippe Mathieu-Daudé
---
I don't know how to use Powershell do use nproc+1 jobs
to optimize jobs waiting on I/O.
---
.gitlab-ci.d/windows.yml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index a83f23a786
This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
This converts the RISC-V charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.
v2:
- Use Fifo8 for the Sifive UART instead of a
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1].
Let's update the SiFive UART to use a async sifive_uart_xmit() function
to transmit the charecters and apply back preassure to the guest with
the SIFIVE_UART_TXFIFO_FULL status.
Thi
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1]. Ideally we want to
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have a way to do that.
Instead let's just use qemu_chr_fe_write_all() so at lea
On Fri, 16 Aug 2024 09:37:35 +0200
Mauro Carvalho Chehab wrote:
> From: Jonathan Cameron
>
> As a GED error device is now defined, add another type
> of notification.
>
> Add error notification to GHES v2 using
>a GED error device GED triggered via interrupt.
On Thu, 15 Aug 2024 at 15:53, Alex Bennée wrote:
>
> From: Nicholas Piggin
>
> chardev events to a muxed device don't get recorded because e.g.,
> qemu_chr_be_write() checks whether the base device has the record flag
> set.
>
> This can be seen when replaying a trace that has characters typed in
'/var/log/qemu-ga' is more reasonable and forward-looking to facilitate
future log management. All qga-related logs would be better placed in a
dedicated and unified log directory.
On Wed, Aug 14, 2024 at 7:54 PM Konstantin Kostiuk
wrote:
> This bug looks specific to the RedHat SELinux configura
On Fri, 16 Aug 2024 09:37:36 +0200
Mauro Carvalho Chehab wrote:
> Creates a QMP command to be used for generic ACPI APEI hardware error
> injection (HEST) via GHESv2.
>
> The actual GHES code will be added at the followup patch.
modulo inconsistency in comments (see below), LGTM
>
> Signed-of
HI Gavin,
Sorry, I was away for almost entire last week. Joined back today.
Thanks for taking out time to review.
> From: Gavin Shan
> Sent: Monday, August 12, 2024 5:36 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> On 6/14/24 9:36 AM, Salil Meh
From: Prasad Pandit
QEMU threads use vhost_user_write/read calls to send
and receive request/reply messages from a vhost-user
device. When multiple threads communicate with the
same vhost-user device, they can receive each other's
messages, resulting in an erroneous state.
When fault_thread exit
> From: Igor Mammedov
> Sent: Monday, August 12, 2024 9:16 AM
> To: Gavin Shan
>
> On Mon, 12 Aug 2024 14:35:56 +1000
> Gavin Shan wrote:
>
> > On 6/14/24 9:36 AM, Salil Mehta wrote:
> > > This shall be used to store user specified
> > > topology{socket,cluster,core,thread}
> > > an
On Fri, 16 Aug 2024 09:37:37 +0200
Mauro Carvalho Chehab wrote:
> The current logic is based on a lot of duct tape, with
> offsets calculated based on one define with the number of
> source IDs and an enum.
>
> Rewrite the logic in a way that it would be more resilient
> of code changes, by movi
> From: Gavin Shan
> Sent: Tuesday, August 13, 2024 2:05 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> On 6/14/24 9:36 AM, Salil Mehta wrote:
> > ACPI CPU hotplug state (is_present=_STA.PRESENT,
> > is_enabled=_STA.ENABLED) for all the possible v
On 2024/8/19 17:41, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Subject: Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control
FS1GP cap bit setting
On 2024/8/15 11:46, Duan, Zhenzhong wrote:
-Original Message-
From: Liu, Yi L
Subject: Re: [PATC
Hi Gavin,
> From: Gavin Shan
> Sent: Tuesday, August 13, 2024 2:17 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> On 6/14/24 9:36 AM, Salil Mehta wrote:
> > During `machvirt_init()`, QOM ARMCPU objects are pre-created along
> > with the correspon
Hi Gavin,
> From: Gavin Shan
> Sent: Tuesday, August 13, 2024 2:21 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> On 6/14/24 9:36 AM, Salil Mehta wrote:
> > Add CPU hot-unplug hooks and update hotplug hooks with additional
> > sanity checks for u
Hi Alex,
> From: Alex Bennée
> Sent: Friday, August 16, 2024 4:37 PM
> To: Salil Mehta
>
> Salil Mehta writes:
>
> > vCPU Hot-unplug will result in QOM CPU object unrealization which will
> > do away with all the vCPU thread creations, allocations, registrations
> > that happened as
On Fri, 16 Aug 2024 09:37:38 +0200
Mauro Carvalho Chehab wrote:
> Provide a generic interface for error injection via GHESv2.
>
> This patch is co-authored:
> - original ghes logic to inject a simple ARM record by Shiju Jose;
> - generic logic to handle block addresses by Jonathan Camero
On Fri, 16 Aug 2024 09:37:44 +0200
Mauro Carvalho Chehab wrote:
> Remove comments that are obvious.
>
> No functional changes.
>
> Signed-off-by: Mauro Carvalho Chehab
these comments help if you don't have spec side by side with code
to compare. I'd even say such comments are preferable than n
Hi Peter,
> From: Peter Maydell
> Sent: Friday, August 16, 2024 4:51 PM
> To: Alex Bennée
>
> On Fri, 16 Aug 2024 at 16:37, Alex Bennée wrote:
> >
> > Salil Mehta writes:
> >
> > > vCPU Hot-unplug will result in QOM CPU object unrealization which
> > > will do away with all the vCPU
> From: Peter Maydell
> Sent: Friday, August 16, 2024 6:00 PM
> To: Alex Bennée
>
> On Fri, 16 Aug 2024 at 16:50, Peter Maydell
> wrote:
> > We shouldn't need to explicitly call cpu_address_space_destroy() from
> > a target-specific unrealize anyway: we can do it all from the base
> >
'hyperv_synic' test from KVM unittests was observed to be flaky on certain
hardware (hangs sometimes). Debugging shows that the problem happens in
hyperv_sint_route_new() when the test tries to set up a new SynIC
route. The function bails out on:
if (!synic->sctl_enabled) {
goto cleanup;
Hi Gavin,
> From: Gavin Shan
> Sent: Monday, August 19, 2024 6:32 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> On 6/14/24 9:36 AM, Salil Mehta wrote:
> > In the ARMv8 architecture, the GIC must know all the CPUs it is
> > connected to during it
According to
https://docs.gitlab.com/ee/ci/runners/hosted_runners/windows.html the
Windows shared runner should have 2 vCPUs nowadays, indeed! Maybe worth to
mention it in the patch description?
Also, how much faster does the job now run for you?
On 19/08/2024 13.21, Philippe Mathieu-Daudé
On Mon, 19 Aug 2024 at 13:59, Salil Mehta wrote:
>
> > From: Peter Maydell
> > Sent: Friday, August 16, 2024 6:00 PM
> > To: Alex Bennée
> >
> > On Fri, 16 Aug 2024 at 16:50, Peter Maydell
> > wrote:
> > > We shouldn't need to explicitly call cpu_address_space_destroy() from
> > > a targ
On Mon, 19 Aug 2024 at 13:58, Salil Mehta wrote:
>
> Hi Peter,
>
> > From: Peter Maydell
> >
> > We shouldn't need to explicitly call cpu_address_space_destroy() from a
> > target-specific unrealize anyway: we can do it all from the base class
> > (and I
> > think this would fix some leaks i
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for device models to request mapping of several DMA
regions at the same time. Examples include:
* net
Hi Cedric,
On 15/08/24 23:22, Cédric Le Goater wrote:
I don't think this is a bug fix. is it ? AFAIUI, it is a debug
feature for skiboot. It's QEMU 9.2 material.
Thanks for answering Nick's question, I did not check my mails.
Yes, it can be considered a debug feature.
One little nit is Ma
Brings in assorted bug fixes. The following are of particular interest
with respect to message-based DMA support:
* bb308a2 "Fix address calculation for message-based DMA"
Corrects a bug in DMA address calculation.
* 1569a37 "Pass server->client command over a separate socket pair"
Adds suppo
Wire up support for DMA for the case where the vfio-user client does not
provide mmap()-able file descriptors, but DMA requests must be performed
via the VFIO-user protocol. This installs an indirect memory region,
which already works for pci_dma_{read,write}, and pci_dma_map works
thanks to the ex
This series adds basic support for message-based DMA in qemu's vfio-user
server. This is useful for cases where the client does not provide file
descriptors for accessing system memory via memory mappings. My motivating use
case is to hook up device models as PCIe endpoints to a hardware design. Th
Hello Nick,
On 16/08/24 07:50, Nicholas Piggin wrote:
<...snip...>
One little nit is MachineState.fdt vs PnvMachineState.fdt
which is now confusing. I would call the new PnvMachineState member
something like fdt_from_dtb, or fdt_override?
I agree. this is confusing. machine->fdt could be used
On Fri, 16 Aug 2024 09:37:45 +0200
Mauro Carvalho Chehab wrote:
> The OS kernels navigate between HEST, error source struct
> and CPER by the usage of some pointers. Double-check if such
> pointers were properly initializing, ensuring that they match
> the right address for CPER.
as QEMU, we don
On Fri, 16 Aug 2024 09:37:32 +0200
Mauro Carvalho Chehab wrote:
> This series add support for injecting generic CPER records. Such records
> are generated outside QEMU via a provided script.
>
> On this version, I added two optional patches at the end:
> - acpi/ghes: cleanup generic error data
At some point the way we allocate socket-id and core-id to CPUs
by default changed; update the example of how to do CPU hotplug
and unplug so the example commands work again. The differences
in the sample input and output are:
* the second CPU is now socket-id=0 core-id=1,
not socket-id=1 core-
When the creds->username property is set we allocate memory
for it in qcrypto_tls_creds_psk_prop_set_username(), but
we never free this when the QCryptoTLSCredsPSK is destroyed.
Free the memory in finalize.
This fixes a LeakSanitizer complaint in migration-test:
$ (cd build/asan; ASAN_OPTIONS="fa
Finally taking this off my to-do list. It’s been a privilege to be part
of this project, but I am no longer actively involved in reviewing
Python code here, so I believe it's best to update the list to reflect
the current maintainers.
Please, feel free to reach out if any questions arise.
Signed-
On Tue, 23 Jul 2024 at 11:59, Michael S. Tsirkin wrote:
>
> From: Salil Mehta
>
> Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also
> involves destruction of the CPU AddressSpace. Add common function to help
> destroy the CPU AddressSpace.
Based on some testing I've been d
Hey Alex,
On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
>
> Hey Dorjoy,
>
> On 18.08.24 13:42, Dorjoy Chowdhury wrote:
> > AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
> > is used for stripped down TPM functionality like attestation. This commit
> > adds the bui
On Mon, Aug 19, 2024 at 03:50:21PM +0100, Peter Maydell wrote:
> When the creds->username property is set we allocate memory
> for it in qcrypto_tls_creds_psk_prop_set_username(), but
> we never free this when the QCryptoTLSCredsPSK is destroyed.
> Free the memory in finalize.
>
> This fixes a Lea
On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
>
> Hey Dorjoy,
>
> On 18.08.24 13:42, Dorjoy Chowdhury wrote:
> > AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
> > is used for stripped down TPM functionality like attestation. This commit
> > adds the built-in NSM d
On Wed, 14 Aug 2024 00:39:57 +0800
Xiaoyao Li wrote:
> On 8/13/2024 10:51 PM, Xiaoyao Li wrote:
> > On 8/13/2024 5:27 PM, Igor Mammedov wrote:
> >> On Mon, 12 Aug 2024 23:31:45 -0400
> >> Xiaoyao Li wrote:
> >>
> >>> Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
> >>
On Sun, 18 Aug 2024 21:12:34 -0500
John Groves wrote:
> On 24/08/15 05:22PM, Jonathan Cameron wrote:
> > Introduction
> >
> >
> > If we think application specific memory (including inter-host shared
> > memory) is
> > a thing, it will also be a thing people want to use with virtual
On Mon, Aug 19, 2024 at 05:32:48PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> QEMU threads use vhost_user_write/read calls to send
> and receive request/reply messages from a vhost-user
> device. When multiple threads communicate with the
> same vhost-user device, they can receive each
On Mon, Aug 19, 2024 at 11:42:02AM -0400, Michael S. Tsirkin wrote:
> On Mon, Aug 19, 2024 at 05:32:48PM +0530, Prasad Pandit wrote:
> > From: Prasad Pandit
> >
> > QEMU threads use vhost_user_write/read calls to send
> > and receive request/reply messages from a vhost-user
> > device. When multi
On Mon, Aug 19, 2024 at 09:32:55PM +0600, Dorjoy Chowdhury wrote:
> On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
> >
> > Hey Dorjoy,
> >
> > On 18.08.24 13:42, Dorjoy Chowdhury wrote:
> > > AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
> > > is used for stripped
On 19.08.24 17:28, Dorjoy Chowdhury wrote:
Hey Alex,
On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
Hey Dorjoy,
On 18.08.24 13:42, Dorjoy Chowdhury wrote:
AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
is used for stripped down TPM functionality like attestat
On Mon, Aug 19, 2024 at 9:53 PM Daniel P. Berrangé wrote:
>
> On Mon, Aug 19, 2024 at 09:32:55PM +0600, Dorjoy Chowdhury wrote:
> > On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
> > >
> > > Hey Dorjoy,
> > >
> > > On 18.08.24 13:42, Dorjoy Chowdhury wrote:
> > > > AWS Nitro Enclaves have
[Resubmission now the merge is correct]
This patch set gives an implementation of "RISC-V Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
you can find the pdf format or the source code.
This is based on the implementation from 2021 by Liu Zhiwei [3], wh
From: Ian Brockbank
CSR mintstatus holds the active interrupt level for each supported
privilege mode. sintstatus, and user, uintstatus, provide restricted
views of mintstatus.
Signed-off-by: Ian Brockbank
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu_bits.h
On Mon, Aug 19, 2024 at 10:07:02PM +0600, Dorjoy Chowdhury wrote:
> On Mon, Aug 19, 2024 at 9:53 PM Daniel P. Berrangé
> wrote:
> >
> > On Mon, Aug 19, 2024 at 09:32:55PM +0600, Dorjoy Chowdhury wrote:
> > > On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
> > > >
> > > > Hey Dorjoy,
> > >
From: Ian Brockbank
The interrupt-level threshold (xintthresh) CSR holds an 8-bit field
for the threshold level of the associated privilege mode.
For horizontal interrupts, only the ones with higher interrupt levels
than the threshold level are allowed to preempt.
Signed-off-by: Ian Brockbank
Signed-off-by: Ian Brockbank
---
hw/riscv/virt.c | 235 +++-
include/hw/riscv/virt.h | 35 ++
2 files changed, 267 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cef41c150a..68d614ad5c 100644
--- a/hw/riscv/virt.
This adds riscv32-clic-test.c, containing qtest test cases for configuring
CLIC (via virt machine) and for triggering interrupts.
In order to detect the interrupts, qtest.c has been updated to send interrupt
information back to the test about the IRQ being delivered. Since we need to
both trigger
On Tue, Aug 13, 2024 at 04:01:03PM +0100, Roy Hopkins wrote:
> The IGVM library allows Independent Guest Virtual Machine files to be
> parsed and processed. IGVM files are used to configure guest memory
> layout, initial processor state and other configuration pertaining to
> secure virtual machine
On Mon, Aug 19, 2024 at 9:58 PM Alexander Graf wrote:
>
>
> On 19.08.24 17:28, Dorjoy Chowdhury wrote:
> > Hey Alex,
> >
> > On Mon, Aug 19, 2024 at 4:13 PM Alexander Graf wrote:
> >> Hey Dorjoy,
> >>
> >> On 18.08.24 13:42, Dorjoy Chowdhury wrote:
> >>> AWS Nitro Enclaves have built-in Nitro Sec
From: Ian Brockbank
The Core-Local Interrupt Controller (CLIC) provides low-latency,
vectored, pre-emptive interrupts for RISC-V systems.
The CLIC also supports a new Selective Hardware Vectoring feature
that allow users to optimize each interrupt for either faster
response or smaller code size.
From: Ian Brockbank
The CSR can be used by software to service the next horizontal interrupt
when it has greater level than the saved interrupt context
(held in xcause`.pil`) and greater level than the interrupt threshold of
the corresponding privilege mode,
Signed-off-by: LIU Zhiwei
Signed-off
From: Ian Brockbank
Decode CLIC interrupt information from exccode, includes interrupt
privilege mode, interrupt level, and irq number.
Then update CSRs xcause, xstatus, xepc, xintstatus and jump to
correct PC according to the CLIC specification.
Signed-off-by: LIU Zhiwei
Signed-off-by: Ian Br
From: Ian Brockbank
The new CLIC interrupt-handling mode is encoded as a new state in the
existing WARL xtvec register, where the low two bits of are 11.
Signed-off-by: LIU Zhiwei
Signed-off-by: Ian Brockbank
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 2 ++
target/riscv/c
From: Ian Brockbank
When a vectored interrupt is selected and serviced, the hardware will
automatically clear the corresponding pending bit in edge-triggered mode.
This may lead to a lower privilege interrupt pending forever.
Therefore when interrupts return, pull a pending interrupt to service.
From: Ian Brockbank
The xip CSR appears hardwired to zero in CLIC mode, replaced by separate
memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be
ignored and will not trap (i.e., no access faults).
Signed-off-by: LIU Zhiwei
Signed-off-by: Ian Brockbank
---
target/riscv/csr.c
On Mon, Aug 19, 2024 at 10:10 PM Daniel P. Berrangé wrote:
>
> On Mon, Aug 19, 2024 at 10:07:02PM +0600, Dorjoy Chowdhury wrote:
> > On Mon, Aug 19, 2024 at 9:53 PM Daniel P. Berrangé
> > wrote:
> > >
> > > On Mon, Aug 19, 2024 at 09:32:55PM +0600, Dorjoy Chowdhury wrote:
> > > > On Mon, Aug 19,
From: Ian Brockbank
The xie CSR appears hardwired to zero in CLIC mode, replaced by separate
memory-mapped interrupt enables (clicintie[i]). Writes to xie will be
ignored and will not trap (i.e., no access faults).
Signed-off-by: LIU Zhiwei
Signed-off-by: Ian Brockbank
---
target/riscv/csr.c
Hi; I'm looking at a memory leak apparently in the host memory backend
code that you can see from the qmp-cmd-test. Repro instructions:
(1) build QEMU with '--cc=clang' '--cxx=clang++' '--enable-debug'
'--target-list=x86_64-softmmu' '--enable-sanitizers'
(2) run 'make check'. More specifically, to
On 19/08/2024 17.00, Beraldo Leal wrote:
Finally taking this off my to-do list. It’s been a privilege to be part
of this project, but I am no longer actively involved in reviewing
Python code here, so I believe it's best to update the list to reflect
the current maintainers.
Please, feel free to
Add a LeakSanitizer suppressions file that documents and suppresses
known false-positive leaks in either QEMU or its dependencies.
To use it you'll need to set
LSAN_OPTIONS="suppressions=/path/to/scripts/lsan-suppressions.txt"
when running a QEMU built with the leak-sanitizer.
The first and curr
On Mon, 19 Aug 2024 at 18:07, Peter Maydell wrote:
>
> Add a LeakSanitizer suppressions file that documents and suppresses
> known false-positive leaks in either QEMU or its dependencies.
> To use it you'll need to set
> LSAN_OPTIONS="suppressions=/path/to/scripts/lsan-suppressions.txt"
> when r
On 19.08.24 18:24, Peter Maydell wrote:
Hi; I'm looking at a memory leak apparently in the host memory backend
code that you can see from the qmp-cmd-test. Repro instructions:
Hi Peter,
(1) build QEMU with '--cc=clang' '--cxx=clang++' '--enable-debug'
'--target-list=x86_64-softmmu' '--enable
Peter Maydell writes:
> Add a LeakSanitizer suppressions file that documents and suppresses
> known false-positive leaks in either QEMU or its dependencies.
> To use it you'll need to set
> LSAN_OPTIONS="suppressions=/path/to/scripts/lsan-suppressions.txt"
> when running a QEMU built with the l
On 19/8/24 17:00, Beraldo Leal wrote:
Finally taking this off my to-do list. It’s been a privilege to be part
of this project, but I am no longer actively involved in reviewing
Python code here, so I believe it's best to update the list to reflect
the current maintainers.
Please, feel free to re
On 16/8/24 09:22, Thomas Huth wrote:
From: Cleber Rosa
Commit 9b45cc993 added many cases of skipUnless for the sake of
organizing flaky tests. But, Python decorators *must* follow what
they decorate, so the newlines added should *not* exist there.
Signed-off-by: Cleber Rosa
Reviewed-by: Phil
The following changes since commit ecdfa31beb1f7616091bedba79dfdf9ee525ed9d:
Merge tag 'pull-request-2024-08-16' of https://gitlab.com/thuth/qemu into
staging (2024-08-16 18:18:27 +1000)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/hw-misc-20240820
for yo
From: Jiaxun Yang
Link:
https://lore.kernel.org/qemu-devel/972034d6-23b3-415a-b401-b8bc1cc51...@linaro.org/
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240621-loongson3-ipi-follow-v2-1-848eafcbb...@flygoat.com>
Signed-off-
From: Heinrich Schuchardt
processor-family and processor-id can be assigned independently.
Add missing brackets.
Fixes: b5831d79671c ("smbios: add processor-family option")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <2024072920
From: Jiaxun Yang
>>> CID 1547264: Null pointer dereferences (REVERSE_INULL)
>>> Null-checking "ipi" suggests that it may be null, but it has already
>>> been dereferenced on all paths leading to the check.
Resolves: Coverity CID 1547264
Link:
https://lore.kernel.org/qemu-devel/75241
From: Peter Maydell
In axidma_class_init() we accidentally used a comma at the end of
a statement rather than a semicolon. This has no ill effects, but
it's obviously not intended and it means that Coccinelle scripts
for instance will fail to match on the two statements. Use a
semicolon instead.
From: Peter Maydell
Directly invoking the DeviceClass::reset method is a bad idea,
because if the device is using three-phase reset then it relies on
transitional reset machinery which is likely to disappear at some
point.
Reset the device in the standard way, by calling device_cold_reset().
Si
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