Re: [PATCH] intel_iommu: Fix invalidation descriptor type field

2024-08-13 Thread Yi Liu
On 2024/8/13 13:53, Zhenzhong Duan wrote: According to spec, invalidation descriptor type is 7bits which is concatenation of bits[11:9] and bits[3:0] of invalidation descriptor. Currently we only pick bits[3:0] as the invalidation type and treat bits[11:9] as reserved zero. This is not a problem

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

2024-08-13 Thread CLEMENT MATHIEU--DRIF
On 13/08/2024 04:12, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Subject: Re: [PATCH v2 04/17] intel_

[PATCH] target/riscv32: Fix masking of physical address

2024-08-13 Thread Andrew Jones
C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will be cleared. rv32 physical addresses may b

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

2024-08-13 Thread CLEMENT MATHIEU--DRIF
On 13/08/2024 09:13, CLEMENT MATHIEU--DRIF wrote: > > On 13/08/2024 04:12, Duan, Zhenzhong wrote: >> Caution: External email. Do not open attachments or click links, unless this >> email comes from a known sender and you know the content is safe. >> >> >>> -Original Message- >>> From: CL

Re: [PATCH] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

2024-08-13 Thread Zhao Liu
On Tue, Aug 13, 2024 at 10:52:27AM +0800, Xiaoyao Li wrote: [snip] > > Any levels that 0xb doesn't cover. > > The name of extended_topo is so misleading. At least, it misleads me. > > Both Intel and AMD support leaf 0xb and the name of leaf 0xb is "Extended > topology enumeration". And here, x8

Re: [PATCH v2] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

2024-08-13 Thread Zhao Liu
On Mon, Aug 12, 2024 at 11:31:45PM -0400, Xiaoyao Li wrote: > Date: Mon, 12 Aug 2024 23:31:45 -0400 > From: Xiaoyao Li > Subject: [PATCH v2] i386/cpu: Introduce enable_cpuid_0x1f to force exposing > CPUID 0x1f > X-Mailer: git-send-email 2.34.1 > > Currently, QEMU exposes CPUID 0x1f to guest only

RE: [PATCH] intel_iommu: Fix invalidation descriptor type field

2024-08-13 Thread Duan, Zhenzhong
>-Original Message- >From: Liu, Yi L >Subject: Re: [PATCH] intel_iommu: Fix invalidation descriptor type field > >On 2024/8/13 13:53, Zhenzhong Duan wrote: >> According to spec, invalidation descriptor type is 7bits which is >> concatenation of bits[11:9] and bits[3:0] of invalidation de

Re: [PATCH] intel_iommu: Fix invalidation descriptor type field

2024-08-13 Thread CLEMENT MATHIEU--DRIF
On 13/08/2024 09:06, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/8/13 13:53, Zhenzhong Duan wrote: >> According to spec, invalidation descriptor type is 7bits whi

Re: [PATCH] target/riscv32: Fix masking of physical address

2024-08-13 Thread Richard Henderson
On 8/13/24 17:13, Andrew Jones wrote: C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32 bits of the u64 being zero. If that result is then used as a mask on another u64 the upper 32 bits will b

[PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

2024-08-13 Thread Zhenzhong Duan
In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are bypassed without scalable mode check. These two types are not valid in legacy mode and we should report error. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 22 +++--- 1 file

[PATCH v2 1/2] intel_iommu: Fix invalidation descriptor type field

2024-08-13 Thread Zhenzhong Duan
According to spec, invalidation descriptor type is 7bits which is concatenation of bits[11:9] and bits[3:0] of invalidation descriptor. Currently we only pick bits[3:0] as the invalidation type and treat bits[11:9] as reserved zero. This is not a problem for now as bits[11:9] is zero for all curre

[PATCH v2 0/2] intel_iommu minor fixes

2024-08-13 Thread Zhenzhong Duan
Hi Fixes two minor issues in intel iommu. See patch for details. Tested scalable mode and legacy mode with vfio device passthrough: PASS Tested intel-iommu.flat in kvm-unit-test: PASS Thanks Zhenzhong Zhenzhong Duan (2): intel_iommu: Fix invalidation descriptor type field intel_iommu: Make

Re: [PATCH] target/riscv32: Fix masking of physical address

2024-08-13 Thread Andrew Jones
On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote: > On 8/13/24 17:13, Andrew Jones wrote: > > C doesn't extend the sign bit for unsigned types since there isn't a > > sign bit to extend. This means a promotion of a u32 to a u64 results > > in the upper 32 bits of the u64 being zero.

Re: [PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

2024-08-13 Thread CLEMENT MATHIEU--DRIF
Reviewed-by: Clément Mathieu--Drif Super reactive! Maybe we can continue along this path after the handlers are implemented. It would be great to make sure we don't process PASID related descriptors when not in scalable mode. What are your thoughts? Thanks >cmd On 13/08/2024 09:44, Zhenzhong

Re: [PATCH v2 0/2] qdev-monitor: avoid QemuOpts in QMP device_add

2024-08-13 Thread Paul Durrant
On 12/08/2024 19:15, Stefan Hajnoczi wrote: On Fri, Aug 02, 2024 at 10:10:43AM +0200, Markus Armbruster wrote: Can we additionally cut out the QemuOpts middleman in usbback_portid_add()? qdict = qdict_new(); qdict_put_str(qdict, "driver", "usb-host"); tmp = g_strdup_printf("%s.0"

Re: [PATCH] target/riscv32: Fix masking of physical address

2024-08-13 Thread Philippe Mathieu-Daudé
On 13/8/24 10:00, Andrew Jones wrote: On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote: On 8/13/24 17:13, Andrew Jones wrote: C doesn't extend the sign bit for unsigned types since there isn't a sign bit to extend. This means a promotion of a u32 to a u64 results in the upper 32

Re: [RFC PATCH 05/23] hw: add register access utility functions

2024-08-13 Thread Philippe Mathieu-Daudé
On 12/8/24 23:14, Octavian Purdila wrote: On Mon, Aug 12, 2024 at 8:33 AM Peter Maydell wrote: On Mon, 5 Aug 2024 at 21:17, Octavian Purdila wrote: Add register access utility functions for device models, like checking aligned access and reading and writing to a register backstore. Sign

Re: [PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

2024-08-13 Thread Yi Liu
On 2024/8/13 15:44, Zhenzhong Duan wrote: In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are bypassed without scalable mode check. These two types are not valid in legacy mode and we should report error. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel

Re: [RFC PATCH 03/23] scripts: add script to generate C header files from SVD XML files

2024-08-13 Thread Philippe Mathieu-Daudé
On 9/8/24 11:59, Daniel P. Berrangé wrote: On Fri, Aug 09, 2024 at 11:42:38AM +0200, Paolo Bonzini wrote: On Fri, Aug 9, 2024 at 11:30 AM Philippe Mathieu-Daudé wrote: On 9/8/24 00:30, Octavian Purdila wrote: On Thu, Aug 8, 2024 at 2:56 PM John Snow wrote: diff --git a/configure b/confi

Re: [PATCH for-9.1] target/m68k: Always return a temporary from gen_lea_mode

2024-08-13 Thread Philippe Mathieu-Daudé
On 13/8/24 02:07, Richard Henderson wrote: Returning a raw areg does not preserve the value if the areg is subsequently modified. Fixes, e.g. "jsr (sp)", where the return address is pushed before the branch. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483 Signed-off-by: Richard Hen

Re: [PATCH v5 0/5] vvfat: Fix write bugs for large files and add iotests

2024-08-13 Thread Kevin Wolf
Am 11.08.2024 um 09:51 hat Michael Tokarev geschrieben: > 12.06.2024 15:43, Amjad Alsharafi wrote: > > These patches fix some bugs found when modifying files in vvfat. > > First, there was a bug when writing to the cluster 2 or above of a file, it > > will copy the cluster before it instead, so, wh

Re: [PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

2024-08-13 Thread Yi Liu
On 2024/8/13 16:00, CLEMENT MATHIEU--DRIF wrote: Reviewed-by: Clément Mathieu--Drif Super reactive! Maybe we can continue along this path after the handlers are implemented. It would be great to make sure we don't process PASID related descriptors when not in scalable mode. What are your thoug

Re: [PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

2024-08-13 Thread Jason Wang
On Tue, Aug 13, 2024 at 4:31 PM Yi Liu wrote: > > On 2024/8/13 15:44, Zhenzhong Duan wrote: > > In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are > > bypassed without scalable mode check. These two types are not valid > > in legacy mode and we should report error. > > > > Sugg

Re: [PATCH v2] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

2024-08-13 Thread Igor Mammedov
On Mon, 12 Aug 2024 23:31:45 -0400 Xiaoyao Li wrote: > Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., > when topology level that cannot be enumerated by leaf 0xB, e.g., die or > module level, are configured for the guest, e.g., -smp xx,dies=2. > > However, 1) TDX architec

Re: [PATCH] hvf: arm: Allow creating VMs with > 63GB of RAM on macOS 15+

2024-08-13 Thread Peter Maydell
On Mon, 12 Aug 2024 at 23:18, Danny Canter wrote: > On Aug 12, 2024, at 10:52 AM, Peter Maydell wrote: > > This is unfortunately probably going to imply a bit of extra > > plumbing to be implemented for hvf -- that MachineClass::kvm_type > > method is (as the name suggests) KVM specific. (Multi-p

Re: [PATCH v3 03/24] tests/functional: Set up logging

2024-08-13 Thread Thomas Huth
On 01/08/2024 12.10, Alex Bennée wrote: Daniel P. Berrangé writes: From: Thomas Huth Create log files for each test separately, one file that contains the basic logging and one that contains the console output. Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- tests/functio

Re: [PATCH for-9.1 0/3] target/i386: Do not apply REX to MMX operands

2024-08-13 Thread Paolo Bonzini
Queued, thanks. Paolo

[PATCH for-9.1] linux-user: Preserve NULL hit in target_mmap subroutines

2024-08-13 Thread Richard Henderson
Do not pass guest_base to the host mmap instead of zero hint. Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353 Signed-off-by: Richard Henderson --- linux-user/mmap.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/lin

[PATCH for-9.2? 0/2] meson: Rationalize sanitizer configuration

2024-08-13 Thread Richard Henderson
In the CI that we actually run (x86) we don't want to use ASan, only UBSan, we jump through --extra-cflags hoops to make that happen, and we fail to disable function sanitizer during normal configuration. In the CI that we don't run, we enable ASan and fail to disable function sanitizer. So its a

[PATCH 2/2] meson: Move -fsanitize=undefined into normal configuraton

2024-08-13 Thread Richard Henderson
With 8e466dd09246 and 23ef50ae2d0c, we disable function pointer sanitization in CI because the qemu code base does not support it. We must disable this for normal usage of --enable-ubsan as well, so move it there. Append options rather than prepend, since all of this requires proper ordering of op

[PATCH 1/2] meson: Split --enable-sanitizers to --enable-{asan, ubsan}

2024-08-13 Thread Richard Henderson
We do not always want both address and undefined behavior sanitizers running at the same time. For the gitlab custom-runners, drop to only --enable-ubsan. These jobs are not run by default, but as will be obvious in the next patch, we don't run ASan on x86 either, and it seems wrong to hold aarch6

Re: [PATCH v4 00/17] Introduce support for IGVM files

2024-08-13 Thread Roy Hopkins
On Sat, 2024-07-20 at 14:26 -0400, Michael S. Tsirkin wrote: > On Wed, Jul 03, 2024 at 12:05:38PM +0100, Roy Hopkins wrote: > > Here is v4 of the set of patches to add support for IGVM files to QEMU. This > > is > > based on commit 1a2d52c7fc of qemu. > > > > This version addresses all of the revi

Re: [PATCH for-9.1 0/3] target/i386: Do not apply REX to MMX operands

2024-08-13 Thread Richard Henderson
On 8/13/24 19:35, Paolo Bonzini wrote: Queued, thanks. Paolo Beware there's a missing \ in patch 3. Not sure how that happened between last test and posting... r~

[PATCH-for-9.1 v2 0/2] target/mips: Use correct MMU index in get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
Propage ptw_mmu_idx to get_pte() and use it via the cpu_ld/st_code_mmu() API. Philippe Mathieu-Daudé (2): target/mips: Pass page table entry size in bytes to get_pte() target/mips: Use correct MMU index in get_pte() target/mips/tcg/sysemu/tlb_helper.c | 35 - 1 fi

Re: [PATCH-for-9.1] target/mips: Fix execution mode in page_table_walk_refill()

2024-08-13 Thread Philippe Mathieu-Daudé
On 12/8/24 09:02, Richard Henderson wrote: On 8/12/24 15:35, Philippe Mathieu-Daudé wrote: On 12/8/24 02:48, Richard Henderson wrote: On 8/12/24 02:54, Philippe Mathieu-Daudé wrote: When refactoring page_table_walk_refill() in commit 4e999bf419 we replaced the execution mode and forced it to k

[PATCH-for-9.1 v2 1/2] target/mips: Pass page table entry size in bytes to get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
In order to simplify a bit, pass the PTE size in bytes rather than bits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/tlb_helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysem

[PATCH-for-9.1 v2 2/2] target/mips: Use correct MMU index in get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM

Re: [PATCH v4 00/17] Introduce support for IGVM files

2024-08-13 Thread Michael S. Tsirkin
On Tue, Aug 13, 2024 at 10:53:58AM +0100, Roy Hopkins wrote: > On Sat, 2024-07-20 at 14:26 -0400, Michael S. Tsirkin wrote: > > On Wed, Jul 03, 2024 at 12:05:38PM +0100, Roy Hopkins wrote: > > > Here is v4 of the set of patches to add support for IGVM files to QEMU. > > > This > > > is > > > based

Re: [PATCH] target/riscv32: Fix masking of physical address

2024-08-13 Thread Andrew Jones
On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote: > On 13/8/24 10:00, Andrew Jones wrote: > > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote: > > > On 8/13/24 17:13, Andrew Jones wrote: > > > > C doesn't extend the sign bit for unsigned types since there isn't a

Re: [PATCH for-9.1] linux-user: Preserve NULL hit in target_mmap subroutines

2024-08-13 Thread Philippe Mathieu-Daudé
On 13/8/24 11:46, Richard Henderson wrote: Do not pass guest_base to the host mmap instead of zero hint. Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353 Signed-off-by: Richard Henderson --- linux-user/mmap.c | 18 +++--- 1 file changed, 15

Re: [PATCH] hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

2024-08-13 Thread Peter Maydell
On Fri, 21 Jun 2024 at 13:59, Peter Maydell wrote: > > On Tue, 18 Jun 2024 at 14:56, Zheyu Ma wrote: > > > > This commit adds validation checks for the MCOPRE and MCOSEL values in > > the rcc_update_cfgr_register function. If the MCOPRE value exceeds > > 0b100 or the MCOSEL value exceeds 0b111, a

Re: [PATCH v4 05/17] i386/pc_sysfw: Ensure sysfw flash configuration does not conflict with IGVM

2024-08-13 Thread Roy Hopkins
On Wed, 2024-07-24 at 18:13 +0100, Daniel P. Berrangé wrote: > On Wed, Jul 03, 2024 at 12:05:43PM +0100, Roy Hopkins wrote: > > When using an IGVM file the configuration of the system firmware is > > defined by IGVM directives contained in the file. In this case the user > > should not configure an

Re: [PATCH v2 01/17] intel_iommu: Use the latest fault reasons defined by spec

2024-08-13 Thread Yi Liu
On 2024/8/5 14:27, Zhenzhong Duan wrote: From: Yu Zhang Spec revision 3.0 or above defines more detailed fault reasons for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Note spec revision has no relation with VERSION register, Guest kernel should not

Re: [PATCH-for-9.1 v2 1/2] target/mips: Pass page table entry size in bytes to get_pte()

2024-08-13 Thread Richard Henderson
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote: -if (ptei > entry_size) { +if (ptei > entry_bytes >> 3) { Shifting the wrong way here. r~

Re: [PATCH-for-9.1 v2 1/2] target/mips: Pass page table entry size in bytes to get_pte()

2024-08-13 Thread Richard Henderson
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote: In order to simplify a bit, pass the PTE size in bytes rather than bits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/tlb_helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m

Re: [PATCH-for-9.1 v2 2/2] target/mips: Use correct MMU index in get_pte()

2024-08-13 Thread Richard Henderson
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote: When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anym

[PATCH-for-9.1] buildsys: Fix building without plugins on Darwin

2024-08-13 Thread Philippe Mathieu-Daudé
Since commit 0082475e26 the plugin symbol list is unconditionally added to the linker flags, leading to a build failure: Undefined symbols for architecture arm64: "_qemu_plugin_entry_code", referenced from: ... ld: symbol(s) not found for architecture arm64 clang: error: linke

[PATCH v1 00/15] tcg/riscv: Add support for vector

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. Key features of this patch series include: 1. Improved register allocation constraints for vector registers. 2. Implementation of vset{i}vli instructions for vector confi

[PATCH v1 02/15] tcg/op-gvec: Fix iteration step in 32-bit operation

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng The loop in the 32-bit case of the vector compare operation was incorrectly incrementing by 8 bytes per iteration instead of 4 bytes. This caused the function to process only half of the intended elements. Signed-off-by: TANG Tiancheng Fixes: 9622c697d1 (tcg: Add gvec compa

[PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. S

[PATCH v1 03/15] tcg: Fix register allocation constraints

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng When allocating registers for input and output, ensure they match the available registers to avoid allocating illeagal registers. We should respect RISC-V vector extension's variable-length registers and LMUL-based register grouping. Coordinate with tcg_target_available_regs

Drop support for Python 3.7?

2024-08-13 Thread Stefan Weil via
Hi, I just saw that the documentation still mentions that QEMU supports Python 3.7. Python 3.7 is an unsupported Python version since about one year. Therefore I suggest to update the documentation for QEMU 9.1.0 and replace 3.7 by 3.8 as lowest supported version. In addition the code whic

[PATCH v1 04/15] tcg/riscv: Add basic support for vector

2024-08-13 Thread LIU Zhiwei
From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. The unused register

[PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multi

[PATCH v1 06/15] tcg/riscv: Implement vector load/store

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 2 + tcg/riscv/tcg-target.c.inc | 92 -- 2 files changed, 91 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/ris

[PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i}

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 43 ++ 1 file changed, 43 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f17d679d71..f60913e805 100644 ---

[PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 33 + 2 files changed, 34 insertions(+) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con

[PATCH v1 09/15] tcg/riscv: Implement vector cmp ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng 1.Address immediate value constraints in RISC-V Vector Extension 1.0 for comparison instructions. 2.Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_ve

[PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 13 + tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-targe

[PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 32 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-targ

[PATCH v1 12/15] tcg/riscv: Implement vector min/max ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 25 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc i

[PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 38 ++ tcg/riscv/tcg-target.h | 4 ++-- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git

[PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 107 - tcg/riscv/tcg-target.h | 8 +-- tcg/riscv/tcg-target.opc.h | 3 ++ 3 files changed, 113 insertions(+), 5 deletions(-) diff --git a/tcg

[PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native

2024-08-13 Thread LIU Zhiwei
From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.h | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..fe6c50e49e 100644 --- a/tcg/riscv/tcg-target.h

Re: [PATCH-for-9.1] buildsys: Fix building without plugins on Darwin

2024-08-13 Thread Richard Henderson
On 8/13/24 21:24, Philippe Mathieu-Daudé wrote: Since commit 0082475e26 the plugin symbol list is unconditionally added to the linker flags, leading to a build failure: Undefined symbols for architecture arm64: "_qemu_plugin_entry_code", referenced from: ... ld: symbol(s)

Re: [PATCH v1 03/15] tcg: Fix register allocation constraints

2024-08-13 Thread Richard Henderson
On 8/13/24 21:34, LIU Zhiwei wrote: From: TANG Tiancheng When allocating registers for input and output, ensure they match the available registers to avoid allocating illeagal registers. We should respect RISC-V vector extension's variable-length registers and LMUL-based register grouping. Coor

Re: Drop support for Python 3.7?

2024-08-13 Thread Philippe Mathieu-Daudé
Hi Stefan, On 13/8/24 13:36, Stefan Weil via wrote: Hi, I just saw that the documentation still mentions that QEMU supports Python 3.7. Oops. Python 3.7 is an unsupported Python version since about one year. Therefore I suggest to update the documentation for QEMU 9.1.0 and replace 3.7 by

Re: Drop support for Python 3.7?

2024-08-13 Thread John Snow
On Tue, Aug 13, 2024, 7:54 AM Philippe Mathieu-Daudé wrote: > Hi Stefan, > > On 13/8/24 13:36, Stefan Weil via wrote: > > Hi, > > > > I just saw that the documentation still mentions that QEMU supports > > Python 3.7. > > Oops. > Oops indeed, we just missed a spot. My apologies. > > Python 3.7

Re: [PATCH v3 05/24] tests/functional: Prepare the meson build system for the functional tests

2024-08-13 Thread Thomas Huth
On 01/08/2024 18.12, Philippe Mathieu-Daudé wrote: Hi, On 30/7/24 19:03, Daniel P. Berrangé wrote: From: Thomas Huth Provide a meson.build file for the upcoming python-based functional tests, and add some wrapper glue targets to the tests/Makefile.include file. We are going to use two "speed"

Re: [PATCH v3 13/24] tests/functional: Convert the s390x avocado tests into standalone tests

2024-08-13 Thread Thomas Huth
On 02/08/2024 15.25, Philippe Mathieu-Daudé wrote: On 1/8/24 19:38, Daniel P. Berrangé wrote: On Thu, Aug 01, 2024 at 07:11:01PM +0200, Philippe Mathieu-Daudé wrote: On 30/7/24 19:03, Daniel P. Berrangé wrote: From: Thomas Huth These tests use archive.lzma_uncompress() from the Avocado utils

Re: [PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate

2024-08-13 Thread Yi Liu
On 2024/8/5 14:27, Zhenzhong Duan wrote: When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation"

Re: [PATCH v3 13/24] tests/functional: Convert the s390x avocado tests into standalone tests

2024-08-13 Thread Thomas Huth
On 13/08/2024 14.04, Thomas Huth wrote: On 02/08/2024 15.25, Philippe Mathieu-Daudé wrote: On 1/8/24 19:38, Daniel P. Berrangé wrote: On Thu, Aug 01, 2024 at 07:11:01PM +0200, Philippe Mathieu-Daudé wrote: On 30/7/24 19:03, Daniel P. Berrangé wrote: From: Thomas Huth These tests use archive

Re: [PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0

2024-08-13 Thread Peter Maydell
On Fri, 21 Jun 2024 at 15:07, Florian Lugou wrote: > > On Thu, Jun 20, 2024 at 08:01:01PM +0100, Peter Maydell wrote: > > On Thu, 20 Jun 2024 at 14:56, Florian Lugou > > wrote: > > > > > > On Thu, Jun 20, 2024 at 11:43:17AM +0100, Peter Maydell wrote: > > > > For this timer check, we're doing I

Re: [PATCH-for-9.1 v2 1/2] target/mips: Pass page table entry size in bytes to get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
On 13/8/24 13:02, Richard Henderson wrote: On 8/13/24 20:18, Philippe Mathieu-Daudé wrote: In order to simplify a bit, pass the PTE size in bytes rather than bits. Signed-off-by: Philippe Mathieu-Daudé ---   target/mips/tcg/sysemu/tlb_helper.c | 16   1 file changed, 8 insertio

Re: [PATCH v1 04/15] tcg/riscv: Add basic support for vector

2024-08-13 Thread Richard Henderson
On 8/13/24 21:34, LIU Zhiwei wrote: +if (cpuinfo & CPUINFO_ZVE64X) { +/* We need to get vlenb for vector's extension */ +riscv_get_vlenb(); +tcg_debug_assert(riscv_vlen >= 64 && is_power_of_2(riscv_vlen)); + +if (riscv_vlen >= 256) { +tcg_target_ava

Re: [PATCH v3 3/5] device/virtio-nsm: Support for Nitro Secure Module device

2024-08-13 Thread Alexander Graf
On 10.08.24 18:45, Dorjoy Chowdhury wrote: Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves for stripped down TPM functionality like cryptographic attestation. The requests to and responses from NSM device are CBOR[2] encoded. This commit adds support for NSM device in QEMU. Al

Re: [PATCH v3 4/5] machine/nitro-enclave: Add built-in Nitro Secure Module device

2024-08-13 Thread Alexander Graf
On 10.08.24 18:45, Dorjoy Chowdhury wrote: AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which is used for stripped down TPM functionality like attestation. This commit adds the built-in NSM device in the nitro-enclave machine type. In Nitro Enclaves, all the PCRs start in a

[PATCH-for-9.1] docs: Fix some typos (found by typos) and grammar issues

2024-08-13 Thread Stefan Weil via
Fix the misspellings of "overriden" also in code comments. Signed-off-by: Stefan Weil --- docs/devel/migration/uadk-compression.rst | 4 ++-- docs/interop/qemu-ga.rst | 2 +- docs/tools/qemu-vmsr-helper.rst | 4 ++-- hw/arm/smmu-common.c | 2 +- in

Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode

2024-08-13 Thread Alex Bennée
Peter Maydell writes: > On Mon, 12 Aug 2024 at 12:10, Alex Bennée wrote: >> >> Peter Maydell writes: >> >> >> >> >> This fails testing: >> >> >> >> https://gitlab.com/qemu-project/qemu/-/jobs/7551982466 >> >> >> >> FAIL: duplicate register {'name': 'PMCCNTR', 'regnum': 96} vs {'name': >> >> '

Re: [RFC PATCH] target/i386: allow access_ptr to force slow path on failed probe

2024-08-13 Thread Alex Bennée
Richard Henderson writes: > On 8/8/24 02:02, Alex Bennée wrote: >> When we are using TCG plugin memory callbacks probe_access_internal >> will return TLB_MMIO to force the slow path for memory access. This >> results in probe_access returning NULL but the x86 access_ptr function >> happily accept

[PATCH] crypto: run qcrypto_pbkdf2_count_iters in a new thread

2024-08-13 Thread Tiago Pasqualini
CPU time accounting in the kernel has been demonstrated to have a sawtooth pattern[1][2]. This can cause the getrusage system call to not be as accurate as we are expecting, which can cause this calculation to stall. The kernel discussions shows that this inaccuracy happens when CPU time gets big

[PATCH v4 1/3] tests/acpi: pc: allow DSDT acpi table changes

2024-08-13 Thread Ricardo Ribalda
Signed-off-by: Ricardo Ribalda --- tests/qtest/bios-tables-test-allowed-diff.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..f81f4e2469 100644 --- a/tests/qtest/bios

[PATCH v4 2/3] hw/i386/acpi-build: Return a pre-computed _PRT table

2024-08-13 Thread Ricardo Ribalda
When qemu runs without kvm acceleration the ACPI executions take a great amount of time. If they take more than the default time (30sec), the ACPI calls fail and the system might not behave correctly. Now the _PRT table is computed on the fly. We can drastically reduce the execution of the _PRT me

[PATCH v4 0/3] hw/i386/acpi: Pre-compute the _PRT table

2024-08-13 Thread Ricardo Ribalda
Today for x86 the _PRT() table is computed in runtime. Under some configurations, computing the _PRT table can take more than 30 seconds and the ACPI timeout is violated. This patchset modifies _PRT() to return a pre-computed table. Changelog v3->v4 Thanks Igor: - Add missing files to tests/qtest

[PATCH v4 3/3] tests/acpi: pc: update golden masters for DSDT

2024-08-13 Thread Ricardo Ribalda
Signed-off-by: Ricardo Ribalda --- tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes tests/data/acpi/x86/pc/DSDT.bridge | Bin 13

[PATCH v3] hw/ppc: Implement -dtb support for PowerNV

2024-08-13 Thread Aditya Gupta
Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The existing behaviour when -dtb is 'not' passed, is preserved as-is. But when a '-dtb' is passed, it complete

[PATCH-for-9.1 v3 2/2] target/mips: Use correct MMU index in get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM

[PATCH-for-9.1 v3 0/2] target/mips: Use correct MMU index in get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
Since v2: - Use MemOp (rth) Propage ptw_mmu_idx to get_pte() and use it via the cpu_ld/st_code_mmu() API. Philippe Mathieu-Daudé (2): target/mips: Pass page table entry size as MemOp to get_pte() target/mips: Use correct MMU index in get_pte() target/mips/tcg/sysemu/tlb_helper.c | 70 +

[PATCH-for-9.1 v3 1/2] target/mips: Pass page table entry size as MemOp to get_pte()

2024-08-13 Thread Philippe Mathieu-Daudé
In order to simplify the next commit, pass the PTE size as MemOp. Rename: native_shift -> native_op directory_shift -> directory_mop leaf_shift -> leaf_mop Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/tlb_helper.c | 59 +---

Re: [PATCH-for-9.1] docs: Fix some typos (found by typos) and grammar issues

2024-08-13 Thread Peter Maydell
On Tue, 13 Aug 2024 at 13:57, Stefan Weil wrote: > > Fix the misspellings of "overriden" also in code comments. > > Signed-off-by: Stefan Weil > --- > docs/devel/migration/uadk-compression.rst | 4 ++-- > docs/interop/qemu-ga.rst | 2 +- > docs/tools/qemu-vmsr-helper.rst

Re: [PATCH-for-9.1] buildsys: Fix building without plugins on Darwin

2024-08-13 Thread Alex Bennée
Philippe Mathieu-Daudé writes: > Since commit 0082475e26 the plugin symbol list is unconditionally > added to the linker flags, leading to a build failure: > > Undefined symbols for architecture arm64: > "_qemu_plugin_entry_code", referenced from: > > ... > ld: symbol(s) not fo

Re: [PATCH] docs: Tweak location of qemu nbd extensions

2024-08-13 Thread Eric Blake
On Sat, Aug 03, 2024 at 03:18:35PM GMT, Wouter Verhelst wrote: > On Fri, Aug 02, 2024 at 08:36:43AM -0500, Eric Blake wrote: > > Upstream QEMU is moving the location of its NBD docs, as of its commit > > [1]. Instead of pointing to the raw git source file, point to the > > rendered html versio

Re: [PATCH v6 00/10] replay: fixes and new test cases

2024-08-13 Thread Alex Bennée
Nicholas Piggin writes: > Since v5, I cut down the series significantly to just the better > reviewed parts, without adding new CI testing, since there are > still be a few hiccups. aarch64 had some hangs Alex noticed, and > x86_64 doesn't seem to be working anymore for me (with the big > replay_

Re: [PATCH-for-9.1] docs: Fix some typos (found by typos) and grammar issues

2024-08-13 Thread Alex Bennée
Stefan Weil via writes: > Fix the misspellings of "overriden" also in code comments. > > Signed-off-by: Stefan Weil Queued to maintainer/for-9.1, thanks. -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH-for-9.1] docs: Fix some typos (found by typos) and grammar issues

2024-08-13 Thread Peter Xu
On Tue, Aug 13, 2024 at 02:56:38PM +0200, Stefan Weil via wrote: > Fix the misspellings of "overriden" also in code comments. > > Signed-off-by: Stefan Weil Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH 0/1] module: Prevent crash by resetting local_err in module_load_qom_all()

2024-08-13 Thread Paolo Bonzini
Queued, thanks. Paolo

Re: [PATCH v3] docs/devel: update tcg-plugins page

2024-08-13 Thread Alex Bennée
Pierrick Bouvier writes: > Reflect recent changes on API (inline ops) and new plugins. > > Signed-off-by: Pierrick Bouvier Queued to maintainer/for-9.1, thanks. -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [RFC PATCH] target/i386: allow access_ptr to force slow path on failed probe

2024-08-13 Thread Richard Henderson
On 8/13/24 23:12, Alex Bennée wrote: Richard Henderson writes: On 8/8/24 02:02, Alex Bennée wrote: When we are using TCG plugin memory callbacks probe_access_internal will return TLB_MMIO to force the slow path for memory access. This results in probe_access returning NULL but the x86 access_

Re: [PATCH v2] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

2024-08-13 Thread Xiaoyao Li
On 8/13/2024 5:27 PM, Igor Mammedov wrote: On Mon, 12 Aug 2024 23:31:45 -0400 Xiaoyao Li wrote: Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., when topology level that cannot be enumerated by leaf 0xB, e.g., die or module level, are configured for the guest, e.g., -smp

Re: [RFC V1 02/12] iommufd: no DMA to BARs

2024-08-13 Thread Steven Sistare
On 8/12/2024 9:39 PM, Yi Liu wrote: On 2024/7/21 03:15, Steve Sistare wrote: Do not map VFIO PCI BARs for DMA.  This stops a raft of warnings of the following form at QEMU start time when using -object iommufd: qemu-kvm: warning: IOMMU_IOAS_MAP failed: Bad address, PCI BAR? qemu-kvm: vfio_conta

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