On 2024/8/13 13:53, Zhenzhong Duan wrote:
According to spec, invalidation descriptor type is 7bits which is
concatenation of bits[11:9] and bits[3:0] of invalidation descriptor.
Currently we only pick bits[3:0] as the invalidation type and treat
bits[11:9] as reserved zero. This is not a problem
On 13/08/2024 04:12, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>> Subject: Re: [PATCH v2 04/17] intel_
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
physical addresses may b
On 13/08/2024 09:13, CLEMENT MATHIEU--DRIF wrote:
>
> On 13/08/2024 04:12, Duan, Zhenzhong wrote:
>> Caution: External email. Do not open attachments or click links, unless this
>> email comes from a known sender and you know the content is safe.
>>
>>
>>> -Original Message-
>>> From: CL
On Tue, Aug 13, 2024 at 10:52:27AM +0800, Xiaoyao Li wrote:
[snip]
> > Any levels that 0xb doesn't cover.
>
> The name of extended_topo is so misleading. At least, it misleads me.
>
> Both Intel and AMD support leaf 0xb and the name of leaf 0xb is "Extended
> topology enumeration". And here, x8
On Mon, Aug 12, 2024 at 11:31:45PM -0400, Xiaoyao Li wrote:
> Date: Mon, 12 Aug 2024 23:31:45 -0400
> From: Xiaoyao Li
> Subject: [PATCH v2] i386/cpu: Introduce enable_cpuid_0x1f to force exposing
> CPUID 0x1f
> X-Mailer: git-send-email 2.34.1
>
> Currently, QEMU exposes CPUID 0x1f to guest only
>-Original Message-
>From: Liu, Yi L
>Subject: Re: [PATCH] intel_iommu: Fix invalidation descriptor type field
>
>On 2024/8/13 13:53, Zhenzhong Duan wrote:
>> According to spec, invalidation descriptor type is 7bits which is
>> concatenation of bits[11:9] and bits[3:0] of invalidation de
On 13/08/2024 09:06, Yi Liu wrote:
> Caution: External email. Do not open attachments or click links,
> unless this email comes from a known sender and you know the content
> is safe.
>
>
> On 2024/8/13 13:53, Zhenzhong Duan wrote:
>> According to spec, invalidation descriptor type is 7bits whi
On 8/13/24 17:13, Andrew Jones wrote:
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will b
In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are
bypassed without scalable mode check. These two types are not valid
in legacy mode and we should report error.
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 22 +++---
1 file
According to spec, invalidation descriptor type is 7bits which is
concatenation of bits[11:9] and bits[3:0] of invalidation descriptor.
Currently we only pick bits[3:0] as the invalidation type and treat
bits[11:9] as reserved zero. This is not a problem for now as bits[11:9]
is zero for all curre
Hi
Fixes two minor issues in intel iommu.
See patch for details.
Tested scalable mode and legacy mode with vfio device passthrough: PASS
Tested intel-iommu.flat in kvm-unit-test: PASS
Thanks
Zhenzhong
Zhenzhong Duan (2):
intel_iommu: Fix invalidation descriptor type field
intel_iommu: Make
On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> On 8/13/24 17:13, Andrew Jones wrote:
> > C doesn't extend the sign bit for unsigned types since there isn't a
> > sign bit to extend. This means a promotion of a u32 to a u64 results
> > in the upper 32 bits of the u64 being zero.
Reviewed-by: Clément Mathieu--Drif
Super reactive!
Maybe we can continue along this path after the handlers are implemented.
It would be great to make sure we don't process PASID related descriptors when
not in scalable mode.
What are your thoughts?
Thanks
>cmd
On 13/08/2024 09:44, Zhenzhong
On 12/08/2024 19:15, Stefan Hajnoczi wrote:
On Fri, Aug 02, 2024 at 10:10:43AM +0200, Markus Armbruster wrote:
Can we additionally cut out the QemuOpts middleman in
usbback_portid_add()?
qdict = qdict_new();
qdict_put_str(qdict, "driver", "usb-host");
tmp = g_strdup_printf("%s.0"
On 13/8/24 10:00, Andrew Jones wrote:
On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
On 8/13/24 17:13, Andrew Jones wrote:
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32
On 12/8/24 23:14, Octavian Purdila wrote:
On Mon, Aug 12, 2024 at 8:33 AM Peter Maydell wrote:
On Mon, 5 Aug 2024 at 21:17, Octavian Purdila wrote:
Add register access utility functions for device models, like checking
aligned access and reading and writing to a register backstore.
Sign
On 2024/8/13 15:44, Zhenzhong Duan wrote:
In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are
bypassed without scalable mode check. These two types are not valid
in legacy mode and we should report error.
Suggested-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel
On 9/8/24 11:59, Daniel P. Berrangé wrote:
On Fri, Aug 09, 2024 at 11:42:38AM +0200, Paolo Bonzini wrote:
On Fri, Aug 9, 2024 at 11:30 AM Philippe Mathieu-Daudé
wrote:
On 9/8/24 00:30, Octavian Purdila wrote:
On Thu, Aug 8, 2024 at 2:56 PM John Snow wrote:
diff --git a/configure b/confi
On 13/8/24 02:07, Richard Henderson wrote:
Returning a raw areg does not preserve the value if the areg
is subsequently modified. Fixes, e.g. "jsr (sp)", where the
return address is pushed before the branch.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2483
Signed-off-by: Richard Hen
Am 11.08.2024 um 09:51 hat Michael Tokarev geschrieben:
> 12.06.2024 15:43, Amjad Alsharafi wrote:
> > These patches fix some bugs found when modifying files in vvfat.
> > First, there was a bug when writing to the cluster 2 or above of a file, it
> > will copy the cluster before it instead, so, wh
On 2024/8/13 16:00, CLEMENT MATHIEU--DRIF wrote:
Reviewed-by: Clément Mathieu--Drif
Super reactive!
Maybe we can continue along this path after the handlers are implemented.
It would be great to make sure we don't process PASID related descriptors when
not in scalable mode.
What are your thoug
On Tue, Aug 13, 2024 at 4:31 PM Yi Liu wrote:
>
> On 2024/8/13 15:44, Zhenzhong Duan wrote:
> > In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are
> > bypassed without scalable mode check. These two types are not valid
> > in legacy mode and we should report error.
> >
> > Sugg
On Mon, 12 Aug 2024 23:31:45 -0400
Xiaoyao Li wrote:
> Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
> when topology level that cannot be enumerated by leaf 0xB, e.g., die or
> module level, are configured for the guest, e.g., -smp xx,dies=2.
>
> However, 1) TDX architec
On Mon, 12 Aug 2024 at 23:18, Danny Canter wrote:
> On Aug 12, 2024, at 10:52 AM, Peter Maydell wrote:
> > This is unfortunately probably going to imply a bit of extra
> > plumbing to be implemented for hvf -- that MachineClass::kvm_type
> > method is (as the name suggests) KVM specific. (Multi-p
On 01/08/2024 12.10, Alex Bennée wrote:
Daniel P. Berrangé writes:
From: Thomas Huth
Create log files for each test separately, one file that contains
the basic logging and one that contains the console output.
Reviewed-by: Daniel P. Berrangé
Signed-off-by: Thomas Huth
---
tests/functio
Queued, thanks.
Paolo
Do not pass guest_base to the host mmap instead of zero hint.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/lin
In the CI that we actually run (x86) we don't want to use ASan,
only UBSan, we jump through --extra-cflags hoops to make that
happen, and we fail to disable function sanitizer during normal
configuration.
In the CI that we don't run, we enable ASan and fail to disable
function sanitizer. So its a
With 8e466dd09246 and 23ef50ae2d0c, we disable function pointer
sanitization in CI because the qemu code base does not support it.
We must disable this for normal usage of --enable-ubsan as well,
so move it there.
Append options rather than prepend, since all of this requires
proper ordering of op
We do not always want both address and undefined behavior
sanitizers running at the same time.
For the gitlab custom-runners, drop to only --enable-ubsan.
These jobs are not run by default, but as will be obvious in the
next patch, we don't run ASan on x86 either, and it seems wrong
to hold aarch6
On Sat, 2024-07-20 at 14:26 -0400, Michael S. Tsirkin wrote:
> On Wed, Jul 03, 2024 at 12:05:38PM +0100, Roy Hopkins wrote:
> > Here is v4 of the set of patches to add support for IGVM files to QEMU. This
> > is
> > based on commit 1a2d52c7fc of qemu.
> >
> > This version addresses all of the revi
On 8/13/24 19:35, Paolo Bonzini wrote:
Queued, thanks.
Paolo
Beware there's a missing \ in patch 3.
Not sure how that happened between last test and posting...
r~
Propage ptw_mmu_idx to get_pte() and use it via
the cpu_ld/st_code_mmu() API.
Philippe Mathieu-Daudé (2):
target/mips: Pass page table entry size in bytes to get_pte()
target/mips: Use correct MMU index in get_pte()
target/mips/tcg/sysemu/tlb_helper.c | 35 -
1 fi
On 12/8/24 09:02, Richard Henderson wrote:
On 8/12/24 15:35, Philippe Mathieu-Daudé wrote:
On 12/8/24 02:48, Richard Henderson wrote:
On 8/12/24 02:54, Philippe Mathieu-Daudé wrote:
When refactoring page_table_walk_refill() in commit 4e999bf419
we replaced the execution mode and forced it to k
In order to simplify a bit, pass the PTE size in
bytes rather than bits.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/sysemu/tlb_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/tcg/sysemu/tlb_helper.c
b/target/mips/tcg/sysem
When refactoring page_table_walk_refill() in commit 4e999bf419
we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill()
-> get_pte()
-> cpu_ld[lq]_code()
-> cpu_mmu_index()
Since we don't mask anymore the modes in hflags, cpu_mmu_index()
can return UM
On Tue, Aug 13, 2024 at 10:53:58AM +0100, Roy Hopkins wrote:
> On Sat, 2024-07-20 at 14:26 -0400, Michael S. Tsirkin wrote:
> > On Wed, Jul 03, 2024 at 12:05:38PM +0100, Roy Hopkins wrote:
> > > Here is v4 of the set of patches to add support for IGVM files to QEMU.
> > > This
> > > is
> > > based
On Tue, Aug 13, 2024 at 10:21:13AM GMT, Philippe Mathieu-Daudé wrote:
> On 13/8/24 10:00, Andrew Jones wrote:
> > On Tue, Aug 13, 2024 at 05:43:07PM GMT, Richard Henderson wrote:
> > > On 8/13/24 17:13, Andrew Jones wrote:
> > > > C doesn't extend the sign bit for unsigned types since there isn't a
On 13/8/24 11:46, Richard Henderson wrote:
Do not pass guest_base to the host mmap instead of zero hint.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 18 +++---
1 file changed, 15
On Fri, 21 Jun 2024 at 13:59, Peter Maydell wrote:
>
> On Tue, 18 Jun 2024 at 14:56, Zheyu Ma wrote:
> >
> > This commit adds validation checks for the MCOPRE and MCOSEL values in
> > the rcc_update_cfgr_register function. If the MCOPRE value exceeds
> > 0b100 or the MCOSEL value exceeds 0b111, a
On Wed, 2024-07-24 at 18:13 +0100, Daniel P. Berrangé wrote:
> On Wed, Jul 03, 2024 at 12:05:43PM +0100, Roy Hopkins wrote:
> > When using an IGVM file the configuration of the system firmware is
> > defined by IGVM directives contained in the file. In this case the user
> > should not configure an
On 2024/8/5 14:27, Zhenzhong Duan wrote:
From: Yu Zhang
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote:
-if (ptei > entry_size) {
+if (ptei > entry_bytes >> 3) {
Shifting the wrong way here.
r~
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote:
In order to simplify a bit, pass the PTE size in
bytes rather than bits.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/sysemu/tlb_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/m
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote:
When refactoring page_table_walk_refill() in commit 4e999bf419
we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill()
-> get_pte()
-> cpu_ld[lq]_code()
-> cpu_mmu_index()
Since we don't mask anym
Since commit 0082475e26 the plugin symbol list is unconditionally
added to the linker flags, leading to a build failure:
Undefined symbols for architecture arm64:
"_qemu_plugin_entry_code", referenced from:
...
ld: symbol(s) not found for architecture arm64
clang: error: linke
From: TANG Tiancheng
This patch set introduces support for the RISC-V vector extension
in TCG backend for RISC-V targets.
Key features of this patch series include:
1. Improved register allocation constraints for vector registers.
2. Implementation of vset{i}vli instructions for vector confi
From: TANG Tiancheng
The loop in the 32-bit case of the vector compare operation
was incorrectly incrementing by 8 bytes per iteration instead
of 4 bytes. This caused the function to process only half of
the intended elements.
Signed-off-by: TANG Tiancheng
Fixes: 9622c697d1 (tcg: Add gvec compa
From: TANG Tiancheng
Add support for probing RISC-V vector extension availability in
the backend. This information will be used when deciding whether
to use vector instructions in code generation.
While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X,
we use RISCV_HWPROBE_IMA_V instead.
S
From: TANG Tiancheng
When allocating registers for input and output, ensure they match
the available registers to avoid allocating illeagal registers.
We should respect RISC-V vector extension's variable-length registers
and LMUL-based register grouping. Coordinate with tcg_target_available_regs
Hi,
I just saw that the documentation still mentions that QEMU supports
Python 3.7.
Python 3.7 is an unsupported Python version since about one year.
Therefore I suggest to update the documentation for QEMU 9.1.0 and
replace 3.7 by 3.8 as lowest supported version.
In addition the code whic
From: Swung0x48
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers.
This implementation uses only the first register number of each group
while reserving the other register numbers within the group.
The unused register
From: TANG Tiancheng
In RISC-V, vector operations require initial configuration using
the vset{i}vl{i} instruction.
This instruction:
1. Sets the vector length (vl) in bytes
2. Configures the vtype register, which includes:
SEW (Single Element Width)
LMUL (vector register group multi
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 2 +
tcg/riscv/tcg-target.c.inc | 92 --
2 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/ris
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 43 ++
1 file changed, 43 insertions(+)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f17d679d71..f60913e805 100644
---
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 33 +
2 files changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con
From: TANG Tiancheng
1.Address immediate value constraints in RISC-V Vector Extension 1.0 for
comparison instructions.
2.Extend comparison results from mask registers to SEW-width elements,
following recommendations in The RISC-V SPEC Volume I (Version 20240411).
This aligns with TCG's cmp_ve
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 13 +
tcg/riscv/tcg-target.h | 4 ++--
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-targe
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 32
tcg/riscv/tcg-target.h | 4 ++--
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-targ
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 25 +
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
i
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 38 ++
tcg/riscv/tcg-target.h | 4 ++--
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 107 -
tcg/riscv/tcg-target.h | 8 +--
tcg/riscv/tcg-target.opc.h | 3 ++
3 files changed, 113 insertions(+), 5 deletions(-)
diff --git a/tcg
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index eb5129a976..fe6c50e49e 100644
--- a/tcg/riscv/tcg-target.h
On 8/13/24 21:24, Philippe Mathieu-Daudé wrote:
Since commit 0082475e26 the plugin symbol list is unconditionally
added to the linker flags, leading to a build failure:
Undefined symbols for architecture arm64:
"_qemu_plugin_entry_code", referenced from:
...
ld: symbol(s)
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
When allocating registers for input and output, ensure they match
the available registers to avoid allocating illeagal registers.
We should respect RISC-V vector extension's variable-length registers
and LMUL-based register grouping. Coor
Hi Stefan,
On 13/8/24 13:36, Stefan Weil via wrote:
Hi,
I just saw that the documentation still mentions that QEMU supports
Python 3.7.
Oops.
Python 3.7 is an unsupported Python version since about one year.
Therefore I suggest to update the documentation for QEMU 9.1.0 and
replace 3.7 by
On Tue, Aug 13, 2024, 7:54 AM Philippe Mathieu-Daudé
wrote:
> Hi Stefan,
>
> On 13/8/24 13:36, Stefan Weil via wrote:
> > Hi,
> >
> > I just saw that the documentation still mentions that QEMU supports
> > Python 3.7.
>
> Oops.
>
Oops indeed, we just missed a spot. My apologies.
> > Python 3.7
On 01/08/2024 18.12, Philippe Mathieu-Daudé wrote:
Hi,
On 30/7/24 19:03, Daniel P. Berrangé wrote:
From: Thomas Huth
Provide a meson.build file for the upcoming python-based functional
tests, and add some wrapper glue targets to the tests/Makefile.include
file. We are going to use two "speed"
On 02/08/2024 15.25, Philippe Mathieu-Daudé wrote:
On 1/8/24 19:38, Daniel P. Berrangé wrote:
On Thu, Aug 01, 2024 at 07:11:01PM +0200, Philippe Mathieu-Daudé wrote:
On 30/7/24 19:03, Daniel P. Berrangé wrote:
From: Thomas Huth
These tests use archive.lzma_uncompress() from the Avocado utils
On 2024/8/5 14:27, Zhenzhong Duan wrote:
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation"
On 13/08/2024 14.04, Thomas Huth wrote:
On 02/08/2024 15.25, Philippe Mathieu-Daudé wrote:
On 1/8/24 19:38, Daniel P. Berrangé wrote:
On Thu, Aug 01, 2024 at 07:11:01PM +0200, Philippe Mathieu-Daudé wrote:
On 30/7/24 19:03, Daniel P. Berrangé wrote:
From: Thomas Huth
These tests use archive
On Fri, 21 Jun 2024 at 15:07, Florian Lugou wrote:
>
> On Thu, Jun 20, 2024 at 08:01:01PM +0100, Peter Maydell wrote:
> > On Thu, 20 Jun 2024 at 14:56, Florian Lugou
> > wrote:
> > >
> > > On Thu, Jun 20, 2024 at 11:43:17AM +0100, Peter Maydell wrote:
> > > > For this timer check, we're doing I
On 13/8/24 13:02, Richard Henderson wrote:
On 8/13/24 20:18, Philippe Mathieu-Daudé wrote:
In order to simplify a bit, pass the PTE size in
bytes rather than bits.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/sysemu/tlb_helper.c | 16
1 file changed, 8 insertio
On 8/13/24 21:34, LIU Zhiwei wrote:
+if (cpuinfo & CPUINFO_ZVE64X) {
+/* We need to get vlenb for vector's extension */
+riscv_get_vlenb();
+tcg_debug_assert(riscv_vlen >= 64 && is_power_of_2(riscv_vlen));
+
+if (riscv_vlen >= 256) {
+tcg_target_ava
On 10.08.24 18:45, Dorjoy Chowdhury wrote:
Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves for
stripped down TPM functionality like cryptographic attestation. The
requests to and responses from NSM device are CBOR[2] encoded.
This commit adds support for NSM device in QEMU. Al
On 10.08.24 18:45, Dorjoy Chowdhury wrote:
AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which
is used for stripped down TPM functionality like attestation. This commit
adds the built-in NSM device in the nitro-enclave machine type.
In Nitro Enclaves, all the PCRs start in a
Fix the misspellings of "overriden" also in code comments.
Signed-off-by: Stefan Weil
---
docs/devel/migration/uadk-compression.rst | 4 ++--
docs/interop/qemu-ga.rst | 2 +-
docs/tools/qemu-vmsr-helper.rst | 4 ++--
hw/arm/smmu-common.c | 2 +-
in
Peter Maydell writes:
> On Mon, 12 Aug 2024 at 12:10, Alex Bennée wrote:
>>
>> Peter Maydell writes:
>>
>> >>
>> >> This fails testing:
>> >>
>> >> https://gitlab.com/qemu-project/qemu/-/jobs/7551982466
>> >>
>> >> FAIL: duplicate register {'name': 'PMCCNTR', 'regnum': 96} vs {'name':
>> >> '
Richard Henderson writes:
> On 8/8/24 02:02, Alex Bennée wrote:
>> When we are using TCG plugin memory callbacks probe_access_internal
>> will return TLB_MMIO to force the slow path for memory access. This
>> results in probe_access returning NULL but the x86 access_ptr function
>> happily accept
CPU time accounting in the kernel has been demonstrated to have a
sawtooth pattern[1][2]. This can cause the getrusage system call to
not be as accurate as we are expecting, which can cause this calculation
to stall.
The kernel discussions shows that this inaccuracy happens when CPU time
gets big
Signed-off-by: Ricardo Ribalda
---
tests/qtest/bios-tables-test-allowed-diff.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..f81f4e2469 100644
--- a/tests/qtest/bios
When qemu runs without kvm acceleration the ACPI executions take a great
amount of time. If they take more than the default time (30sec), the
ACPI calls fail and the system might not behave correctly.
Now the _PRT table is computed on the fly. We can drastically reduce the
execution of the _PRT me
Today for x86 the _PRT() table is computed in runtime.
Under some configurations, computing the _PRT table can take more than
30 seconds and the ACPI timeout is violated.
This patchset modifies _PRT() to return a pre-computed table.
Changelog v3->v4 Thanks Igor:
- Add missing files to tests/qtest
Signed-off-by: Ricardo Ribalda
---
tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes
tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes
tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes
tests/data/acpi/x86/pc/DSDT.bridge | Bin 13
Currently any device tree passed with -dtb option in QEMU, was ignored
by the PowerNV code.
Read and pass the passed -dtb to the kernel, thus enabling easier
debugging with custom DTBs.
The existing behaviour when -dtb is 'not' passed, is preserved as-is.
But when a '-dtb' is passed, it complete
When refactoring page_table_walk_refill() in commit 4e999bf419
we missed the indirect call to cpu_mmu_index() in get_pte():
page_table_walk_refill()
-> get_pte()
-> cpu_ld[lq]_code()
-> cpu_mmu_index()
Since we don't mask anymore the modes in hflags, cpu_mmu_index()
can return UM
Since v2:
- Use MemOp (rth)
Propage ptw_mmu_idx to get_pte() and use it via
the cpu_ld/st_code_mmu() API.
Philippe Mathieu-Daudé (2):
target/mips: Pass page table entry size as MemOp to get_pte()
target/mips: Use correct MMU index in get_pte()
target/mips/tcg/sysemu/tlb_helper.c | 70 +
In order to simplify the next commit, pass the PTE size as MemOp.
Rename:
native_shift -> native_op
directory_shift -> directory_mop
leaf_shift -> leaf_mop
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/sysemu/tlb_helper.c | 59 +---
On Tue, 13 Aug 2024 at 13:57, Stefan Weil wrote:
>
> Fix the misspellings of "overriden" also in code comments.
>
> Signed-off-by: Stefan Weil
> ---
> docs/devel/migration/uadk-compression.rst | 4 ++--
> docs/interop/qemu-ga.rst | 2 +-
> docs/tools/qemu-vmsr-helper.rst
Philippe Mathieu-Daudé writes:
> Since commit 0082475e26 the plugin symbol list is unconditionally
> added to the linker flags, leading to a build failure:
>
> Undefined symbols for architecture arm64:
> "_qemu_plugin_entry_code", referenced from:
>
> ...
> ld: symbol(s) not fo
On Sat, Aug 03, 2024 at 03:18:35PM GMT, Wouter Verhelst wrote:
> On Fri, Aug 02, 2024 at 08:36:43AM -0500, Eric Blake wrote:
> > Upstream QEMU is moving the location of its NBD docs, as of its commit
> > [1]. Instead of pointing to the raw git source file, point to the
> > rendered html versio
Nicholas Piggin writes:
> Since v5, I cut down the series significantly to just the better
> reviewed parts, without adding new CI testing, since there are
> still be a few hiccups. aarch64 had some hangs Alex noticed, and
> x86_64 doesn't seem to be working anymore for me (with the big
> replay_
Stefan Weil via writes:
> Fix the misspellings of "overriden" also in code comments.
>
> Signed-off-by: Stefan Weil
Queued to maintainer/for-9.1, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On Tue, Aug 13, 2024 at 02:56:38PM +0200, Stefan Weil via wrote:
> Fix the misspellings of "overriden" also in code comments.
>
> Signed-off-by: Stefan Weil
Reviewed-by: Peter Xu
--
Peter Xu
Queued, thanks.
Paolo
Pierrick Bouvier writes:
> Reflect recent changes on API (inline ops) and new plugins.
>
> Signed-off-by: Pierrick Bouvier
Queued to maintainer/for-9.1, thanks.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
On 8/13/24 23:12, Alex Bennée wrote:
Richard Henderson writes:
On 8/8/24 02:02, Alex Bennée wrote:
When we are using TCG plugin memory callbacks probe_access_internal
will return TLB_MMIO to force the slow path for memory access. This
results in probe_access returning NULL but the x86 access_
On 8/13/2024 5:27 PM, Igor Mammedov wrote:
On Mon, 12 Aug 2024 23:31:45 -0400
Xiaoyao Li wrote:
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest, e.g., -smp
On 8/12/2024 9:39 PM, Yi Liu wrote:
On 2024/7/21 03:15, Steve Sistare wrote:
Do not map VFIO PCI BARs for DMA. This stops a raft of warnings of the
following form at QEMU start time when using -object iommufd:
qemu-kvm: warning: IOMMU_IOAS_MAP failed: Bad address, PCI BAR?
qemu-kvm: vfio_conta
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