[PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 24 2 files changed, 27 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/int

[PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

Add an new element scalable_mode in IntelIOMMUState to mark scalable modern mode, this element will be exposed as an intel_iommu property finally. For now, it's only a placehholder and used for address width compatibility check and block host device passthrough until nesting is supported. Signed-

[PATCH v2 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

From: Yi Liu Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. While this vIOMMU implementation wants to simplify it for user by providing typical combinations. User could config it by "x-scalabl

[PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device

Hi, Per Jason Wang's suggestion, iommufd nesting series[1] is split into "Enable stage-1 translation for emulated device" series and "Enable stage-1 translation for passthrough device" series. This series enables stage-1 translation support for emulated device in intel iommu which we called "mode

[PATCH v2 06/17] intel_iommu: Implement stage-1 translation

From: Yi Liu This adds stage-1 page table walking to support stage-1 only transltion in scalable modern mode. Signed-off-by: Yi Liu Co-developed-by: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_intern

[PATCH v2 07/17] intel_iommu: Check if the input address is canonical

From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 21 + 2 files changed

[PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting

When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMMU can't translate stage-1 page table from guest correctly. Add a property x-cap-fs1gp for user to turn FS1GP off so that nested page table on host side works. This property has no effect when vIOMMU isn't in scalable modern mode. Si

[PATCH v2 17/17] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif --- MAINTAINERS|

[PATCH v2 13/17] intel_iommu: piotlb invalidation should notify unmap

This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 35 ++

[PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mode introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. By this chance, rem

[PATCH v2 10/17] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif ---

[PATCH v2 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw/i386/intel_iommu_internal.

[PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. In other cases, it is still default to 39

[PATCH v2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=001b)

Re: [PATCH for-9.2 v12 00/11] hw/pci: SR-IOV related fixes and improvements

On Sun, Aug 04, 2024 at 06:01:36PM +0900, Akihiko Odaki wrote: > Supersedes: <20240714-rombar-v2-0-af1504ef5...@daynix.com> > ("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto") > > I submitted a RFC series[1] to add support for SR-IOV emulation to > virtio-net-pci. During the development of

Re: [RFC PATCH] tests/avocado: Re-enable gdbsim-r5f562n8 testing U-Boot

On Fri, 02 Aug 2024 02:23:32 +0900, Philippe Mathieu-Daudé wrote: > > We disabled all RX tests on commit 9b45cc9931 ("docs/devel: > rationalise unstable gitlab tests under FLAKY_TESTS") for > being flaky. However I don't recall the U-Boot test to fail > (the problematic line checking the 'version'

Re: [PATCH 01/17] bsd-user: Delete TaskState next member

On 8/3/24 09:56, Warner Losh wrote: The next struct member of TaskState is unused. Remove it. Signed-off-by: Warner Losh --- bsd-user/qemu.h | 1 - 1 file changed, 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 02/17] bsd-user: Make init_task_state global

On 8/3/24 09:56, Warner Losh wrote: Restore init_task_state to its global status. It's needed for threading support outside of main. Signed-off-by: Warner Losh --- bsd-user/main.c | 2 +- bsd-user/qemu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson

Re: [PATCH 03/17] bsd-user: Make cpu_model and cpu_type file scope

On 8/3/24 09:56, Warner Losh wrote: linux-user already does this since 2278b93941d4. That same commit just added them with main() scope to bsd-user. We need the cpu_type, like linux-user does, to create new CPUs outside of main to support threading. Move both cpu_model and cpu_type to mirror linu

Re: [PATCH 04/17] bsd-user: Implement cpu_copy()

On 8/3/24 09:56, Warner Losh wrote: From: Stacey Son Catch up with 30ba0ee52d15 and implement cpu_copy(). It's needed for threading. Stacey's original code, with bug fixes from Jessica, Justin and myself. Signed-off-by: Stacey Son Signed-off-by: Jessica Clarke Signed-off-by: Justin Hibbits Sign

Re: [PATCH 06/17] bsd-user: Remove load_flt_binary prototype

On 8/3/24 09:56, Warner Losh wrote: bsd-user doesn't have support for loading FLT binaries. Signed-off-by: Warner Losh --- bsd-user/qemu.h | 2 -- 1 file changed, 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 07/17] bsd-user: Remove deprecated -p argument

On 8/3/24 09:56, Warner Losh wrote: FreeBSD never really used the -p argument, so it's safe to remove entirely. Signed-off-by: Warner Losh --- bsd-user/main.c | 8 1 file changed, 8 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 05/17] bsd-user: Eliminate unused regs arg in load_elf_binary

On 8/3/24 09:56, Warner Losh wrote: Signed-off-by: Warner Losh --- bsd-user/bsdload.c | 2 +- bsd-user/elfload.c | 3 +-- bsd-user/qemu.h| 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 08/17] bsd-user: Eliminate unused qemu_uname_release

On 8/3/24 09:56, Warner Losh wrote: bsd-user has never supported this, and FreeBSD make it easy to set this on a per-jail basis, so that the normal reporting routines that we pass through just work. Since this was never used, and never even in the usage(), retire it to cut down on the clutter. It

Re: [PATCH 09/17] bsd-user: target_msync unused, remove it

On 8/3/24 09:56, Warner Losh wrote: Nothing calls target_msync in the upstream or blitz fork, so remove it. It will save us having to modernize it. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 17 - bsd-user/qemu.h | 1 - 2 files changed, 18 deletions(-) Reviewed-by:

Re: [PATCH 10/17] bsd-user: Pass image name down the stack

On 8/3/24 09:56, Warner Losh wrote: Pass the image name down the stack so that we can give better error messages. Inspired by similar work in linux-user, and more likely to come. Signed-off-by: Warner Losh --- bsd-user/elfload.c | 19 +++ 1 file changed, 11 insertions(+), 8 de

[PATCH for-9.2 v12 00/11] hw/pci: SR-IOV related fixes and improvements

Supersedes: <20240714-rombar-v2-0-af1504ef5...@daynix.com> ("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto") I submitted a RFC series[1] to add support for SR-IOV emulation to virtio-net-pci. During the development of the series, I fixed some trivial bugs and made improvements that I think

[PATCH for-9.2 v12 05/11] pcie_sriov: Ensure VF function number does not overflow

pci_new() aborts when creating a VF with a function number equals to or is greater than PCI_DEVFN_MAX. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 8 +--- include/hw/pci/pcie_sriov.h | 5 +++-- hw/net/igb.c| 13 ++--- hw/nvme/ctrl.c |

[PATCH for-9.2 v12 08/11] pcie_sriov: Remove num_vfs from PCIESriovPF

num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 1 - hw/pci/pcie_sriov.c | 38 +++--- hw/pci/trace-events | 2 +- 3 files changed, 28 insertions(+), 13

[PATCH for-9.2 v12 10/11] hw/pci: Use -1 as the default value for rombar

vfio_pci_size_rom() distinguishes whether rombar is explicitly set to 1 by checking dev->opts, bypassing the QOM property infrastructure. Use -1 as the default value for rombar to tell if the user explicitly set it to 1. The property is also converted from unsigned to signed. -1 is signed so it is

[PATCH for-9.2 v12 11/11] hw/qdev: Remove opts member

It is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- include/hw/qdev-core.h | 4 hw/core/qdev.c | 1 - system/qdev-monitor.c | 12 +++- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/i

[PATCH for-9.2 v12 06/11] pcie_sriov: Reuse SR-IOV VF device instances

Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 5 --- incl

[PATCH for-9.2 v12 09/11] pcie_sriov: Register VFs after migration

pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- in

[PATCH for-9.2 v12 04/11] pcie_sriov: Do not manually unrealize

A device gets automatically unrealized when being unparented. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 4 1 file changed, 4 deletions(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index e9b23221d713..499becd5273f 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_

[PATCH for-9.2 v12 03/11] hw/ppc/spapr_pci: Do not reject VFs created after a PF

A PF may automatically create VFs and the PF may be function 0. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index f63182a03c41..ed4454bbf79e 100644 --- a/hw/ppc/spapr_pci.c +++

[PATCH for-9.2 v12 02/11] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

Disabled means it is a disabled SR-IOV VF or it is powered off, and hidden from the guest. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7cf9904c3546..f63182a03c41 100644 --- a/hw/ppc/spap

[PATCH for-9.2 v12 01/11] hw/pci: Rename has_power to enabled

The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 7 ++- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c| 14 +++--- hw/pci/pci_host

[PATCH for-9.2 v12 07/11] pcie_sriov: Release VFs failed to realize

Release VFs failed to realize just as we do in unregister_vfs(). Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri

Re: [PATCH for-9.2 v11 08/11] pcie_sriov: Remove num_vfs from PCIESriovPF

On 2024/08/03 1:52, Michael S. Tsirkin wrote: On Sat, Aug 03, 2024 at 12:38:10AM +0900, Akihiko Odaki wrote: On 2024/08/02 21:58, Michael S. Tsirkin wrote: On Fri, Aug 02, 2024 at 02:17:58PM +0900, Akihiko Odaki wrote: num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF inst

Re: [PATCH 11/17] bsd-user: Replace set_brk and padzero with zerobss from linux-user

On 8/3/24 09:56, Warner Losh wrote: The zero_bss interface from linux-user is much better at doing this. Use it in preference to set_brk (badly named) and padzero. These both have issues with the new variable page size code, so it's best to just retire them and reuse the code from linux-user. Als

Re: [PATCH v2 4/4] virtio-net: Add support for USO features

On Sun, Aug 04, 2024 at 03:49:45PM +0900, Akihiko Odaki wrote: > On 2024/08/03 1:26, Peter Xu wrote: > > On Sat, Aug 03, 2024 at 12:54:51AM +0900, Akihiko Odaki wrote: > > > > > > I'm not sure if I read it right. Perhaps you meant something more > > > > > > generic > > > > > > than -platform but

Re: [PATCH v2 4/4] virtio-net: Add support for USO features

On Sun, Aug 04, 2024 at 09:08:05AM -0400, Peter Xu wrote: > On Sun, Aug 04, 2024 at 03:49:45PM +0900, Akihiko Odaki wrote: > > On 2024/08/03 1:26, Peter Xu wrote: > > > On Sat, Aug 03, 2024 at 12:54:51AM +0900, Akihiko Odaki wrote: > > > > > > > I'm not sure if I read it right. Perhaps you meant s

[PATCH] vhost-user: rewrite vu_dispatch with if-else

rewrite with if-else instead of goto and I have a question, in two incorrent cases - need reply but no reply_requested - no need reply but has reply_requested should we call vu_panic or print warning message? --- subprojects/libvhost-user/libvhost-user.c | 39 +-- subprojec

Re: [PATCH V2 00/11] Live update: cpr-exec

On Mon, Jul 22, 2024 at 10:59:47AM +0200, David Hildenbrand wrote: > > So I wonder whether there's comparison between exec() and transfer mode > > that you recently proposed. > > > > I'm asking because exec() (besides all the rest of things that I dislike on > > it in this approach..) should be si

[PATCH] vhost-user: add NEED_REPLY flag

Front-end message requests which need reply should set NEED_REPLY_MASK in flag, and response from slave need clear NEED_REPLY_MASK flag. --- hw/virtio/vhost-user.c| 2 +- subprojects/libvhost-user/libvhost-user.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --g

Re: [PATCH V2 00/11] Live update: cpr-exec

On Sat, Jul 20, 2024 at 05:26:07PM -0400, Steven Sistare wrote: > On 7/18/2024 11:56 AM, Peter Xu wrote: > > Steve, > > > > On Sun, Jun 30, 2024 at 12:40:23PM -0700, Steve Sistare wrote: > > > What? > > > > Thanks for trying out with the cpr-transfer series. I saw that that series > > missed mos

[PATCH 1/3] configure: Fix arch detection for GDB_HAS_MTE

GDB_HAS_MTE must only be set if GDB supports the aarch64 arch, so the test if "aarch64" string is present must be against GDB-related '$gdb_arches' variable and not against '$arch' variable. Signed-off-by: Gustavo Romero --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -

[PATCH 3/3] configure: Fix GDB version detection for GDB_HAS_MTE

The test gdbstub/test-mte.py requires a GDB version that supports the qIsAddressTagged packet. According to GDB NEWS [0], this packet was first made available in the GDB 15.1 release, not in 15.0, so this commit fixes it in configure. [0] https://www.sourceware.org/gdb/news/ Signed-off-by: Gustav

[PATCH 2/3] configure: Avoid use of param. expansion when using gdb_version

$gdb_version is now used in more than one conditional case and its usage in such cases may increase in the future. Therefore, avoid using shell parameter expansion when using it by setting gdb_version to its final form. Signed-off-by: Gustavo Romero --- configure | 8 +--- 1 file changed, 5

[PATCH 0/3] configure: Bump GDB detection version for GDB_HAS_MTE

The main goal of this tiny series is to bump from 15.0. to 15.1 the GDB version used for setting GDB_HAS_MTE=y to correctly detect GDB versions that support all the packets necessary to run the QEMU gdbstub MTE tests in user mode, resolving issue 2447 [0]. I took the chance to fix a bug in configu

Re: [PATCH V2 01/11] machine: alloc-anon option

On Sat, Jul 20, 2024 at 04:35:58PM -0400, Steven Sistare wrote: > On 7/17/2024 3:24 PM, Peter Xu wrote: > > On Tue, Jul 16, 2024 at 11:19:55AM +0200, Igor Mammedov wrote: > > > On Sun, 30 Jun 2024 12:40:24 -0700 > > > Steve Sistare wrote: > > > > > > > Allocate anonymous memory using mmap MAP_ANO

Re: [PATCH v2 1/1] Add support for generating OpenSBI domains in the device tree

On 7/26/24 3:43 PM, Gregor Haas wrote: OpenSBI has support for domains, which are partitions of CPUs and memory into isolated compartments. Domains can be specified in the device tree according to a standardized format [1], which OpenSBI parses at boot time to initialize all system domains. Th

[RFC PATCH v6 3/5] .gitattributes: add Rust diff and merge attributes

Set rust source code to diff=rust (built-in with new git versions) and merge=binary for Cargo.lock files (they should not be merged but auto-generated by cargo) Reviewed-by: Alex Bennée Reviewed-by: Zhao Liu Signed-off-by: Manos Pitsidianakis --- .gitattributes | 3 +++ 1 file changed, 3 inser

[RFC PATCH v6 0/5] rust-pl011-rfc-v6

Changes === - Setting MSRV to 1.77.0: * cstr crate MSRV is 1.64, which is more recent than Debian bookworm (1.63.0) * pl011's dependencies (mostly proc-macro2) don't support 1.63.0 - Dropped CI/lcitool patches. - Dropped vendo

[RFC PATCH v6 5/5] rust: add PL011 device model

This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=aarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Signed-off-by: Manos Pitsidi

[RFC PATCH v6 2/5] rust: add bindgen step as a meson dependency

Add bindings_rs target for generating rust bindings to target-independent qemu C APIs. The bindings need be created before any rust crate that uses them is compiled. The bindings.rs file will end up in BUILDDIR/bindings.rs and have the same name as a target: ninja bindings.rs Signed-off-by: M

[RFC PATCH v6 1/5] build-sys: Add rust feature option

Add rust feature in meson.build, configure, to prepare for adding Rust code in the followup commits. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 5 + configure | 2 ++ meson.build | 25 - Kconfig

[RFC PATCH v6 4/5] rust: add crate to expose bindings and interfaces

Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and provides some declaration macros for symbols visible to the rest of QEMU. Signed-off-by: Manos Pitsidianakis --- MAINTAINERS | 6 ++ rust/meson.build | 13 +++ rust/qemu-api/.gitign

Re: [PATCH 12/17] bsd-user: Use guest_range_valid_untagged to validate range

On 8/3/24 09:56, Warner Losh wrote: This is the generic validation function, so remove some hand-rolled ones. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 13/17] bsd-user: target_mprotect: rename prot to target_prot

On 8/3/24 09:56, Warner Losh wrote: Linux-user's target_mprotect uses this convention, so move to it. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 14/17] bsd-user: target_mmap*: change prot to target_prot

On 8/3/24 09:56, Warner Losh wrote: Adopt the linux-user convention of using target_prot for passed in protections. no functional change. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 47 --- 1 file changed, 24 insertions(+), 23 deletions(-) Re

Re: [PATCH 15/17] bsd-user: target_mprotect: use helper host_page_size local

On 8/3/24 09:56, Warner Losh wrote: Use helper variable for host_page_size. Linux-user uses a similar helper to make the code smaller after the multi-page-size migration. Signed-off-by: Warner Losh --- bsd-user/mmap.c | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) Rev

Re: [PATCH 16/17] bsd-user: Define validate_prot_to_pageflags and use in mprotect

On 8/3/24 09:56, Warner Losh wrote: Define validate_prot_to_pageflags. Use it in target_mprotect to validate the flags. Our taraget_mmap needs more work before it can be used there, do don't copy linux-user's use of it there. This should hvae no net functional change, but does make target_mprotec

Re: [PATCH 17/17] bsd-user: copy linux-user target_mprotect impl

On 8/3/24 09:56, Warner Losh wrote: Now that we're closer to the linux-user target_mprotect code, go ahead and grab the rest of the implementation. This moves from a stard, end impl to a start, last which will allow last page mapping, etc. This also moves to a more general algorithm. We're close

Re: [PATCH for-9.2 v6 02/12] hw/riscv: add riscv-iommu-bits.h

On Fri, Aug 2, 2024 at 1:45 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > This header will be used by the RISC-V IOMMU emulation to be added > in the next patch. Due to its size it's being sent in separate for > an easier review. > > One thing to notice is that this header can be

Re: [PATCH for-9.2 v6 03/12] hw/riscv: add RISC-V IOMMU base emulation

On Fri, Aug 2, 2024 at 1:47 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The RISC-V IOMMU specification is now ratified as-per the RISC-V > international process. The latest frozen specifcation can be found at: > > https://github.com/riscv-non-isa/riscv-iommu/releases/download/v

Re: [PATCH for-9.2 v6 10/12] hw/riscv/riscv-iommu: add DBG support

On Fri, Aug 2, 2024 at 1:47 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > DBG support adds three additional registers: tr_req_iova, tr_req_ctl and > tr_response. > > The DBG cap is always enabled. No on/off toggle is provided for it. > > Signed-off-by: Tomasz Jeznach > Signed-of

Re: [PATCH for-9.2 v6 12/12] docs/specs: add riscv-iommu

On Fri, Aug 2, 2024 at 1:46 AM Daniel Henrique Barboza wrote: > > Add a simple guideline to use the existing RISC-V IOMMU support we just > added. > > This doc will be updated once we add the riscv-iommu-sys device. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alist

Re: [PATCH] hw/char/riscv_htif: Fix 64-bit var write order in 32-bit system

On Wed, Jul 31, 2024 at 12:51 AM Nikita Novikov wrote: > > When we are trying to write 64-bit value in 32-bit system, the value in HTIF > device divides > on 2 separate 32-bit parts. So device expects write to xHOST_OFFSET1 first, > then to xHOST_OFFSET2. > But some compilers (ex. CLANG) can cha

Re: [PATCH v3 1/3] target/riscv: Remove redundant insn length check for zama16b

On Fri, Aug 2, 2024 at 5:26 PM LIU Zhiwei wrote: > > Compressed encodings also applies to zama16b. > https://github.com/riscv/riscv-isa-manual/pull/1557 > > Suggested-by: Alistair Francis > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/tran

Re: [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On Fri, Aug 2, 2024 at 5:27 PM LIU Zhiwei wrote: > > Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q > extensions. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvd.c.inc | 8 ++-- > 1 file change

Re: [PATCH v3 3/3] target/riscv: Relax fld alignment requirement

On Fri, Aug 2, 2024 at 5:27 PM LIU Zhiwei wrote: > > According to the risc-v specification: > "FLD and FSD are only guaranteed to execute atomically if the effective > address is naturally aligned and XLEN≥64." > > We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does > not viol

[PATCH for-9.1] target/i386: Fix VSIB decode

With normal SIB, index == 4 indicates no index. With VSIB, there is no exception for VR4/VR12. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2474 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 20 ++-- target/i386/tcg/decode-new.c.inc | 3 ++-

[PULL 1/6] linux-user/elfload: Fix pr_pid values in core files

From: Ilya Leoshkevich Analyzing qemu-produced core dumps of multi-threaded apps runs into: (gdb) info threads [...] 21 Thread 0x3ff83cc0740 (LWP 9295) warning: Couldn't find general-purpose registers in core file. in ?? () The reason is that all pr_pid values are the sa

[PULL 0/6] misc patch queue

The following changes since commit f9851d2ffef59b3a7f39513469263ab3b019480f: Merge tag 'migration-20240802-pull-request' of https://gitlab.com/farosas/qemu into staging (2024-08-03 07:26:26 +1000) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-misc-202

[PULL 6/6] net/tap: Use qemu_close_all_open_fd()

From: Clément Léger Instead of using a slow implementation to close all open fd after forking, use qemu_close_all_open_fd(). Signed-off-by: Clément Léger Reviewed-by: Richard Henderson Message-ID: <20240802145423.3232974-6-cle...@rivosinc.com> Signed-off-by: Richard Henderson --- net/tap.c |

[PULL 5/6] qemu/osdep: Add excluded fd parameter to qemu_close_all_open_fd()

From: Clément Léger In order for this function to be usable by tap.c code, add a list of file descriptors that should not be closed. Signed-off-by: Clément Léger Message-ID: <20240802145423.3232974-5-cle...@rivosinc.com> [rth: Use max_fd in qemu_close_all_open_fd_close_range] Signed-off-by: Ric

[PULL 4/6] net/tap: Factorize fd closing after forking

From: Clément Léger The same code is used twice to actually close all open file descriptors after forking. Factorize it in a single place. Signed-off-by: Clément Léger Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240802145423.3232974-4-cle...@rivosinc.com>

[PULL 3/6] qemu/osdep: Split qemu_close_all_open_fd() and add fallback

From: Clément Léger In order to make it cleaner, split qemu_close_all_open_fd() logic into multiple subfunctions (close with close_range(), with /proc/self/fd and fallback). Signed-off-by: Clément Léger Reviewed-by: Richard Henderson Message-ID: <20240802145423.3232974-3-cle...@rivosinc.com> S

[PULL 2/6] qemu/osdep: Move close_all_open_fds() to oslib-posix

From: Clément Léger Move close_all_open_fds() in oslib-posix, rename it qemu_close_all_open_fds() and export it. Signed-off-by: Clément Léger Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240802145423.3232974-2-cle...@rivosinc.com> Signed-off-by: Richard He

Re: [PATCH v8 4/5] qemu/osdep: Add excluded fd parameter to qemu_close_all_open_fd()

On 8/3/24 00:54, Clément Léger wrote: In order for this function to be usable by tap.c code, add a list of file descriptors that should not be closed. Signed-off-by: Clément Léger --- include/qemu/osdep.h| 8 ++- system/async-teardown.c | 2 +- util/oslib-posix.c | 106

Re: [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b

On Fri, Aug 2, 2024 at 5:25 PM LIU Zhiwei wrote: > > In this patch set, we remove the redundant insn length check for zama16b as > the > specification clarified that zama16b applies to compressed encodings[1]. > > Richard points out we should obey the MXLEN requirement for F/D/Q loads or > store

Re: [PATCH] target/riscv: Add asserts for out-of-bound access

On Wed, Jul 24, 2024 at 6:33 PM Atish Patra wrote: > > Coverity complained about the possible out-of-bounds access with > counter_virt/counter_virt_prev because these two arrays are > accessed with privilege mode. However, these two arrays are accessed > only when virt is enabled. Thus, the privil

Re: [PATCH] target/riscv: Add asserts for out-of-bound access

On Wed, Jul 24, 2024 at 6:33 PM Atish Patra wrote: > > Coverity complained about the possible out-of-bounds access with > counter_virt/counter_virt_prev because these two arrays are > accessed with privilege mode. However, these two arrays are accessed > only when virt is enabled. Thus, the privil

Re: [PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()

On Mon, Jul 29, 2024 at 5:52 PM LIU Zhiwei wrote: > > > On 2024/7/29 14:07, Alvin Che-Chia Chang(張哲嘉) wrote: > > Hi Zhiwei, > > > >> -Original Message- > >> From: LIU Zhiwei > >> Sent: Monday, July 29, 2024 1:47 PM > >> To: Alvin Che-Chia Chang(張哲嘉) ; > >> qemu-ri...@nongnu.org; qemu-deve

Re: [PULL 0/8] Net patches

Hi Richard: On Fri, Aug 2, 2024 at 5:48 PM Richard Henderson wrote: > > On 8/2/24 13:19, Jason Wang wrote: > > The following changes since commit 31669121a01a14732f57c49400bc239cf9fd505f: > > > >Merge tag 'pull-target-arm-20240801' > > ofhttps://git.linaro.org/people/pmaydell/qemu-arm into s

[PATCH 1/2] include: bitops: Add mask extract64/deposit64

Based on the RISC-V get_field() and set_field() macros add mask_extract64() and mask_deposit64() bitop functions. These can extrac and deposit values into fields using a bit field mask directly instead of a length and shift. Signed-off-by: Alistair Francis --- include/qemu/bitops.h | 35

[PATCH 2/2] target/riscv: Remove get_field and set_field

Instead of using the custom RISC-V get_field() and set_field() macros let's use the newly introduced mask_extract64() and mask_deposit64() functions. Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 10 ++--- target/riscv/cpu_bits.h | 6 --- target/riscv/pmp.h| 6 +--

[PATCH 0/2] target/riscv: Convert RISC-V custom bitops to standard ones

Based on discussions at [1] this is a simple conversion from using the RISC-V specific bit operations to using standard QEMU ones. This series adds two new bit op helpers mask_extract64() and mask_deposit64() which the RISC-V target can then use. 1: https://mail.gnu.org/archive/html/qemu-devel/20

Re: [PATCH] hw/openrisc: Fixed undercounting of TTCR in continuous mode

On Mon, Jun 10, 2024 at 07:29:15PM +, Joel Holdsworth wrote: > Hi Stafford, thanks for your response. > > > - You sent this 2 times, is the only change in v2 the sender address? > > Yes, I was just having some difficulty with Git and SMTP. Should be fixed now. OK. > >> In the existing desig

[PATCH v2 01/17] intel_iommu: Use the latest fault reasons defined by spec

From: Yu Zhang Spec revision 3.0 or above defines more detailed fault reasons for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Note spec revision has no relation with VERSION register, Guest kernel should not use that register to judge what features a

[PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate

When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu Signed-off-by: Zhen

[PATCH v2 05/17] intel_iommu: Rename slpte to pte

From: Yi Liu Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation, rename variable and functions from slpte to pte whenever possible. But some are SST only, they are renamed with sl_ prefix. Signed-off-by: Yi Liu Co-developed-by: Clément Mathieu--Drif Signed-off-by: Cl

[PATCH v2 11/17] intel_iommu: Add an internal API to find an address space with PASID

From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/h