Hi Daniel,
On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel
Reviewed-by: Konstantin Kostiuk
On Wed, Jul 17, 2024 at 5:00 PM Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7d9811458c..af4db698de 100644
> --- a/MAINTAINER
>-Original Message-
>From: Joao Martins
>Subject: Re: [PATCH v4 11/12] vfio/migration: Don't block migration device
>dirty tracking is unsupported
>
>On 17/07/2024 03:38, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Joao Martins
>>> Subject: [PATCH v4 11/12] vfi
If a file imported from Linux is touched, emit a warning and suggest
using scripts/update-linux-headers.sh.
Also check that updating imported files from Linux are not mixed with
other changes, in which case emit an error.
Signed-off-by: Stefano Garzarella
---
v2:
- added an error when mixing imp
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 6 --
include/hw/intc/loongarch_extioi.h | 1 -
2 files changed, 7 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e592b1b6b7..2103a1
>-Original Message-
>From: Joao Martins
>Subject: Re: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain
>creation
>
>On 17/07/2024 11:05, Duan, Zhenzhong wrote:
>>> -Original Message-
>>> From: Joao Martins
>>> Subject: Re: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain
On 18/07/2024 01:44, Minwoo Im wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
On 24-07-11 19:00:58, CLEMENT MATHIEU--DRIF wrote:
On 11/07/2024 10:04, Minwoo Im wrote:
Caution: External
On Thu, Jul 18, 2024 at 09:20:50AM +0200, Stefano Garzarella wrote:
> If a file imported from Linux is touched, emit a warning and suggest
> using scripts/update-linux-headers.sh.
>
> Also check that updating imported files from Linux are not mixed with
> other changes, in which case emit an error
>-Original Message-
>From: Joao Martins
>Subject: Re: [PATCH v4 00/12] hw/iommufd: IOMMUFD Dirty Tracking
>
>On 16/07/2024 09:20, Duan, Zhenzhong wrote:
>>
>>
>>> -Original Message-
>>> From: Joao Martins
>>> Subject: [PATCH v4 00/12] hw/iommufd: IOMMUFD Dirty Tracking
>>>
>>> T
On 7/18/24 08:49, Jamin Lin wrote:
AST2700 and AST2600 ADC controllers are identical.
Introduce ast2700 class and set 2 engines.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/adc/aspeed_adc.c | 16
include/hw/adc/aspeed_adc.h | 1
On 7/18/24 08:49, Jamin Lin wrote:
Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_ and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.
Signed-off-by: Jamin Lin
On 7/18/24 08:49, Jamin Lin wrote:
According to the datasheet of ASPEED SOCs,
an I2C controller owns 8KB of register space for AST2700,
owns 4KB of register space for AST2600, AST2500 and AST2400,
and owns 64KB of register space for AST1030.
It set the memory region size 4KB by default and it do
On 18/7/24 04:11, maobibo wrote:
On 2024/7/18 上午5:46, Philippe Mathieu-Daudé wrote:
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Signed-o
On 17/7/24 19:15, marcandre.lur...@redhat.com wrote:
Marc-André Lureau (4):
ui: add more tracing for dbus
ui/vdagent: improve vdagent_fe_open() trace
ui/vdagent: notify clipboard peers of serial reset
ui/vdagent: send caps on fe_open
Reviewed-by: Philippe Mathieu-Daudé
On 7/18/24 08:49, Jamin Lin wrote:
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
And firmware required to set the offset of pool buffer
by writing "Function Control Register(I2CD 00)"
To
Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will
flush stage-2 iotlb entries with matching domain id and pasid.
With scalable modern mode introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries.
Signed-off-by: Zhen
Hi,
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for emulated device" series and
"Enable stage-1 translation for passthrough device" series.
This series enables stage-1 translation support for emulated device
in intel iommu which we called "mode
From: Yu Zhang
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not use that register to judge what features a
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 3 +++
hw/i386/intel_iommu.c | 24
2 files changed, 27 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/int
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 35 ++-
1 file changed, 34 i
From: Clément Mathieu--Drif
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 39 ---
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/h
From: Clément Mathieu--Drif
This piece of code can be shared by both IOTLB invalidation and
PASID-based IOTLB invalidation
No functional changes intended.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 57 ++
Add an new element scalable_mode in IntelIOMMUState to mark scalable
modern mode, this element will be exposed as an intel_iommu property
finally.
For now, it's only a placehholder and used for cap/ecap initialization,
compatibility check and block host device passthrough until nesting
is supporte
From: Yi Liu
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Cl
On 2024/7/18 下午3:25, Song Gao wrote:
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 6 --
include/hw/intc/loongarch_extioi.h | 1 -
2 files changed, 7 deletions(-)
diff --git a/hw/loongarch/virt.c b
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 3
According to spec, Page-Selective-within-Domain Invalidation (11b):
1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
(PGTT=100b) mappings associated with the specified domain-id and the
input-address range are invalidated.
2. IOTLB entries caching first-stage (PGTT=001b)
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu
Signed-off-by: Zhen
From: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 11
hw/i386/intel_iommu.c | 50 ++
2 files changed, 61 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48.
So default aw_bits to 48 in scalable modern mode. In other cases,
it is still default to 39
From: Yi Liu
This adds stage-1 page table walking to support stage-1 only
transltion in scalable modern mode.
Signed-off-by: Yi Liu
Co-developed-by: Clément Mathieu--Drif
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_intern
From: Clément Mathieu--Drif
First stage translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu_internal.h | 2 ++
hw/i386/intel_iommu.c | 21 +
2 files changed
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness in scalable
modern mode. Also tested cap/ecap bits consistency before
and after system reset.
Signed-off-by: Zhenzhong Duan
---
MAINTAINERS| 1 +
include/hw/i386/intel_iommu.h
From: Yi Liu
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
While this vIOMMU implementation wants to simplify it for user by providing
typical combinations. User could config it by "x-scalabl
Vladimir Sementsov-Ogievskiy writes:
> Add command to sync config from vhost-user backend to the device. It
> may be helpful when VHOST_USER_SLAVE_CONFIG_CHANGE_MSG failed or not
> triggered interrupt to the guest or just not available (not supported
> by vhost-user server).
>
> Command result is
Only a small subset of all architectures supported by qemu make use of
firmware files. Introduce and use a new enum to represent this.
This also removes the dependency to machine.json from the global qapi
definitions.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Thomas Weißschuh
---
docs/in
Only a small subset of all blockdev drivers make sense for firmware
images. Introduce and use a new enum to represent this.
This also reduces the dependency on firmware.json from the global qapi
definitions.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Thomas Weißschuh
---
docs/interop/firm
docs/interop/firmware.json is currently not usable with qapi-gen.py due
to various non-functional issues.
Fix those issue to provide compatibility.
In v3 there was an open question about @file vs. @raw,
but given that the existing descriptors in pc-bios/descriptors/ are
already using @raw it seems
To make sure that the QAPI description stays valid add a testcase.
Suggested-by: Philippe Mathieu-Daudé
Link:
https://lore.kernel.org/qemu-devel/d9ce0234-4beb-4b90-b14c-76810d3b8...@linaro.org/
Signed-off-by: Thomas Weißschuh
---
docs/meson.build | 5 +
1 file changed, 5 insertions(+)
dif
On Thu, Jul 18, 2024 at 10:27:38AM +0200, Thomas Weißschuh wrote:
> Only a small subset of all blockdev drivers make sense for firmware
> images. Introduce and use a new enum to represent this.
>
> This also reduces the dependency on firmware.json from the global qapi
> definitions.
>
> Suggested
Vladimir Sementsov-Ogievskiy writes:
> Here we just prepare for the following patch, making possible to report
> GenericError as recommended.
>
> This patch doesn't aim to prevent further use of DeviceNotFound by
> future interfaces:
>
> - find_device_state() is used in blk_by_qdev_id() and qmp_
Vladimir Sementsov-Ogievskiy writes:
> ping. Markus, Eric, could someone give an ACC for QAPI part?
I apologize for the delay. It was pretty bad.
From: BillXiang
We have added VHOST_USER_SET_LOG_BASE to vhost_user_per_device_request
in https://lists.nongnu.org/archive/html/qemu-devel/2024-06/msg02559.html
and will send this message only for vq 0.
Signed-off-by: BillXiang
---
V1[1] -> V2:
- Refrain from appending flags to messages that c
On Thu, Jul 18, 2024 at 10:27:39AM +0200, Thomas Weißschuh wrote:
> Only a small subset of all architectures supported by qemu make use of
> firmware files. Introduce and use a new enum to represent this.
>
> This also removes the dependency to machine.json from the global qapi
> definitions.
>
>
On Thu, Jul 18, 2024 at 10:27:40AM +0200, Thomas Weißschuh wrote:
> To make sure that the QAPI description stays valid add a testcase.
>
> Suggested-by: Philippe Mathieu-Daudé
> Link:
> https://lore.kernel.org/qemu-devel/d9ce0234-4beb-4b90-b14c-76810d3b8...@linaro.org/
> Signed-off-by: Thomas We
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/loongson_ipi.c | 21 +
1 file changed, 9 insertions(+),
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_finalize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bib
From: Bibo Mao
We'll have to add LoongsonIPIClass in few commits,
so rename LoongsonIPI as LoongsonIPIState for clarity.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed
From: Bibo Mao
In preparation to extract common IPI code in few commits,
extract loongson_ipi_common_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo
From: Bibo Mao
Loongson IPI is only available in little-endian,
so use that to access the guest memory (in case
we run on a big-endian host).
Signed-off-by: Bibo Mao
Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support")
[PMD: Extracted from bigger commit, added commit descript
Since v3:
- Use DEFINE_TYPES() macro (unreviewed patch #1)
- Update MAINTAINERS
- Added Bibo's tags
Song, since Bibo reviewed/tested, if you provide your
Acked-by I can queue that to my next hw-misc PR (pending
Jiaxun testing).
Thanks,
Phil.
Bibo Mao (16):
hw/intc/loongson_ipi: Access memory
From: Bibo Mao
Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
From: Bibo Mao
Move the IPICore structure and corresponding common fields
of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h".
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-
From: Bibo Mao
It is easier to manage one array of MMIO MR rather
than one per vCPU.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
From: Bibo Mao
Allow Loongson IPI implementations to have their own get_iocsr_as()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bib
From: Bibo Mao
Allow Loongson IPI implementations to have their own cpu_by_arch_id()
handler.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: B
From: Bibo Mao
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
include/hw/intc/loongson_ipi.h| 18 --
inc
From: Bibo Mao
In order to access loongson_ipi_core_read/write helpers
from loongson_ipi_common.c in the next commit, make their
prototype declaration public.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-of
On 7/18/24 08:49, Jamin Lin wrote:
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bibo Mao
Tested-by: Bibo Mao
---
hw/intc/loongson_ipi.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c
index 051e910586..aa1b0a474c 100644
--- a/hw/intc/loongson_ipi.c
+++ b/hw/intc/l
From: Bibo Mao
Loongarch IPI inherits from class LoongsonIPICommonClass, and it
only contains Loongarch 3A5000 virt machine specific interfaces,
rather than mix different machine implementations together.
Signed-off-by: Bibo Mao
[PMD: Rebased]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off
From: Bibo Mao
In order to get LoongsonIPICommonClass in send_ipi_data()
in the next commit, propagate LoongsonIPICommonState.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Re
From: Bibo Mao
Now than LoongArch target can use the TYPE_LOONGARCH_IPI
model, restrict TYPE_LOONGSON_IPI to MIPS.
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: B
From: Bibo Mao
Move the common code from loongson_ipi.c to loongson_ipi_common.c,
call parent_realize() instead of loongson_ipi_common_realize() in
loongson_ipi_realize().
Signed-off-by: Bibo Mao
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Dau
From: Bibo Mao
Loongarch IPI is added here, it inherits from class
TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and
cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can
be used when ipi is emulated in userspace with KVM mode.
Signed-off-by: Bibo Mao
[PMD: Rebased and s
On 7/18/24 08:49, Jamin Lin wrote:
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 -
On 7/18/24 08:49, Jamin Lin wrote:
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: D
Remove extioi INT_encode encode mode, because we don't emulate it.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/hw/intc/loongarch_extioi.h
b/include/hw/intc/loongarch_extioi.h
index eccc2e0d18..626a37dfa1 100644
--- a/
On 7/18/24 08:49, Jamin Lin wrote:
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus reg
On 7/18/24 08:49, Jamin Lin wrote:
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/arm/aspeed.c
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed.c | 21 ++---
1 file changed, 14 inse
On 7/18/24 08:49, Jamin Lin wrote:
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
As a followup, you could modify test_aarch64_ast2700_evb_sdk_v09_02
to
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Add an new element scalable_mode in IntelIOMMUState to mark scalable
> modern mode, this element wil
On 18/07/2024 08:20, Duan, Zhenzhong wrote:
>
>
>> -Original Message-
>> From: Joao Martins
>> Subject: Re: [PATCH v4 11/12] vfio/migration: Don't block migration device
>> dirty tracking is unsupported
>>
>> On 17/07/2024 03:38, Duan, Zhenzhong wrote:
>>>
>>>
-Original Message-
Reviewed-by: Clément Mathieu--Drif
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> When guest configures Nested Translation(011b) or First-stage Tra
When injecting a new poisoned region through qmp_cxl_inject_poison(),
the newly injected region should not overlap with existing poisoned
regions.
The current validation method does not consider the following
overlapping region:
┌───┬───┬───┐
│a │ b(a) │a │
└───┴───┴───┘
(a is a newly a
Reviewed-by: Clément Mathieu--Drif
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> According to VTD spec, stage-1 page table could support 4-level
On 18/07/2024 08:44, Duan, Zhenzhong wrote:
> If existing hwpt doesn't support dirty tracking.
> Another device supporting dirty tracking attaches to that hwpt, what
>> will
happen?
>
Hmm, It succeeds as there's no incompatbility. At the very least I plan on
blocking
On Wed, 17 Jul 2024 at 21:11, Volker Rümelin wrote:
>
> Fix the search function in Sphinx generated html docs when built
> with Sphinx >= 6.0.0.
>
> Quote from the Sphinx blog at
> https://blog.readthedocs.com/sphinx6-upgrade
>
> Sphinx 6 is out and has important breaking changes
>
> Bundled jQuer
On Thu, 18 Jul 2024 at 07:15, Markus Armbruster wrote:
>
> Looks like this one fell through the cracks.
>
> Octavian Purdila writes:
>
> > Add path option to the pty char backend which will create a symbolic
> > link to the given path that points to the allocated PTY.
> >
> > This avoids having t
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> From: Yi Liu
>
> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
> rela
Hi Cedric,
> Subject: Re: [PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > ASPEED SDK add lm75 in i2c bus 0 for AST2700.
> > LM75 is compatible with TMP105 driver.
> >
> > Introduce a new i2c init function and
> > add tmp105 device model in i2
On Thu, Jul 18, 2024 at 08:15:01AM +0200, Markus Armbruster wrote:
> Looks like this one fell through the cracks.
>
> Octavian Purdila writes:
>
> > Add path option to the pty char backend which will create a symbolic
> > link to the given path that points to the allocated PTY.
> >
> > This avoi
Hi Cedric,
> Subject: Re: [PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > Introduce a new ast2700 class to support AST2700.
> > The I2C bus register memory regions and I2C bus pool buffer memory
> > regions are discontinuous and they do not back compa
The gtk-vnc package is used by the vnc-display-test qtest
program. Technically only gvnc is needed, but since we
already pull in the gtk3 dep, it is harmless to depend
on gtk-vnc.
Signed-off-by: Daniel P. Berrangé
---
tests/lcitool/projects/qemu.yml | 1 +
1 file changed, 1 insertion(+)
diff --
Refresh with the newly added gtk-vnc package
Signed-off-by: Daniel P. Berrangé
---
.gitlab-ci.d/cirrus/freebsd-13.vars | 2 +-
.gitlab-ci.d/cirrus/macos-13.vars | 2 +-
.gitlab-ci.d/cirrus/macos-14.vars | 2 +-
scripts/ci/setup/ubuntu/ubu
The vnc-display-test is skipped in CI due to missing gvnc RPMs,
fix that.
Daniel P. Berrangé (2):
ci: add gtk-vnc to the deps
ci: refresh package lists with lcitool
.gitlab-ci.d/cirrus/freebsd-13.vars | 2 +-
.gitlab-ci.d/cirrus/macos-13.vars | 2 +-
.gi
Hi Eric,
On 17/07/2024 18:43, Eric Auger wrote:
Hi Peter, Richard,
On 7/17/24 17:09, Jean-Philippe Brucker wrote:
On Mon, Jul 15, 2024 at 08:45:00AM +, Mostafa Saleh wrote:
Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
but not nested instances.
This patch series adds
Hi Cedric,
> Subject: Re: [PATCH v1 03/15] hw/i2c/aspeed: support to set the different
> memory size
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > According to the datasheet of ASPEED SOCs, an I2C controller owns 8KB
> > of register space for AST2700, owns 4KB of register space for AST2600,
> > AST25
Hi Cedric,
> Subject: Re: [PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register
> memory region of I2C bus
>
> On 7/18/24 08:49, Jamin Lin wrote:
> > It only support continuous register memory region for all I2C bus.
> > However, the register address of all I2c bus are discontinuous for
>
From: Thomas Huth
The test has been marked as broken more than 4 years ago, and
so far nobody ever cared to fix it. Thus let's simply remove it
now ... if somebody ever needs it again, they can restore the
file from an older version of QEMU.
Signed-off-by: Thomas Huth
Reviewed-by: Clément Chigo
Coverity reported a memory leak (CID 1549757) in this code and its
admittedly rather clumsy handling of extending the command table.
Instead of handing over a full array of the commands lets use the
lighter weight GPtrArray and simply test for the presence of each
entry as we go. This avoids compli
This brings in the latest python mappings for the BSD updates.
Signed-off-by: Alex Bennée
---
.gitlab-ci.d/cirrus/freebsd-13.vars | 2 +-
tests/lcitool/libvirt-ci| 2 +-
tests/vm/generated/freebsd.json | 14 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff
From: Philippe Mathieu-Daudé
Since the SEMIHOSTING feature is optional, we need
a stub to link when it is disabled.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240717105723.58965-4-phi...@linaro.org>
Signed-off-by: Alex Bennée
---
target/mips/tcg/sysemu/semihosting-stub.c | 15 ++
I'm just flushing my various maintainer queues for the up-coming 9.1
soft freeze. Mostly this is a collection of fixes and tweaks although
there is a new plugin in contrib. We've also bumped the libvirt-ci for
the BSD python updates.
The following still need review:
tests/plugins: use qemu_plug
From: Pierrick Bouvier
data was correctly copied, but size of array was not set
(g_array_sized_new only reserves memory, but does not set size).
As a result, callbacks were not called for code path relying on
plugin_register_vcpu_mem_cb().
Found when trying to trigger mem access callbacks for a
From: Philippe Mathieu-Daudé
The semihosting feature depends on TCG (due to the probe_access
API access). Although TCG is the single accelerator currently
available for the xtensa target, use the Kconfig "imply" directive
which is more correct (if we were to support a different accel).
Reported-
From: Frédéric Pétrot
Register values are dumped as 'sz' chunks of two nibbles in the execlog
plugin, sz was 1 too big.
Signed-off-by: Frédéric Pétrot
Reviewed-by: Pierrick Bouvier
Message-Id: <20240620083805.73603-1-frederic.pet...@univ-grenoble-alpes.fr>
Signed-off-by: Alex Bennée
---
cont
From: Philippe Mathieu-Daudé
Since the SEMIHOSTING feature is optional, we need
a stub to link when it is disabled.
Suggested-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20240717105723.58965-3-phi...@linaro.org>
Signed-off-by: Alex Bennée
---
target/m68k/semihosting-
From: Simon Hamelin
This new plugin allows to stop emulation using conditions on the
emulation state. By setting this plugin arguments, it is possible
to set an instruction count limit and/or trigger address(es) to stop at.
The code returned at emulation exit can be customized.
This plugin demon
From: Philippe Mathieu-Daudé
The semihosting feature depends on TCG (due to the probe_access
API access). Although TCG is the single accelerator currently
available for the m68k target, use the Kconfig "imply" directive
which is more correct (if we were to support a different accel).
Reported-by
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