On 7/8/24 4:34 PM, Joao Martins wrote:
By default VFIO migration is set to auto, which will support live
migration if the migration capability is set *and* also dirty page
tracking is supported.
For testing purposes one can force enable without dirty page tracking
via enable-migration=on, but th
On 7/8/24 4:34 PM, Joao Martins wrote:
ioctl(iommufd, IOMMU_HWPT_GET_DIRTY_BITMAP, arg) is the UAPI
that fetches the bitmap that tells what was dirty in an IOVA
range.
A single bitmap is allocated and used across all the hwpts
sharing an IOAS which is then used in log_sync() to set Qemu
global b
On 7/8/24 4:34 PM, Joao Martins wrote:
ioctl(iommufd, IOMMU_HWPT_SET_DIRTY_TRACKING, arg) is the UAPI that
enables or disables dirty page tracking. It is used if the hwpt
has been created with dirty tracking supported domain (stored in
hwpt::flags) and it is called on the whole list of iommu doma
Hi Jean,
On Thu, Jul 04, 2024 at 07:02:00PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:25AM +, Mostafa Saleh wrote:
> > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> > class of events faults as:
> >
> > CLASS: The class of the operation that cau
Hi Jean,
On Thu, Jul 04, 2024 at 07:08:43PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:30AM +, Mostafa Saleh wrote:
> > According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
> > In "5.2 Stream Table Entry":
> > [51:6] S1ContextPtr
> > If Config[1] == 1
Hi Jean,
On Thu, Jul 04, 2024 at 07:12:35PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:31AM +, Mostafa Saleh wrote:
> > In the next patch, combine_tlb() will be added which combines 2 TLB
> > entries into one for nested translations, which chooses the granule
> > and l
Hi Jean,
On Thu, Jul 04, 2024 at 07:31:10PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:33AM +, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 table address IPA into PA through stage-2.
> > - Translate stage
Hi Eric,
On Mon, Jul 08, 2024 at 05:19:59PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 7/1/24 13:02, Mostafa Saleh wrote:
> > When nested translation is requested, do the following:
> >
> > - Translate stage-1 table address IPA into PA through stage-2.
> > - Translate stage-1 table walk output
Hi Jean,
On Thu, Jul 04, 2024 at 07:32:36PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:34AM +, Mostafa Saleh wrote:
> > With nesting, we would need to invalidate IPAs without
> > over-invalidating stage-1 IOVAs. This can be done by
> > distinguishing IPAs in the TLBs b
Hi Jean,
On Thu, Jul 04, 2024 at 07:35:03PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:37AM +, Mostafa Saleh wrote:
> > IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
> > SMMU instances we consider the input address as the IOVA, but when
> > nesting is use
Hi Jean,
On Thu, Jul 04, 2024 at 07:36:58PM +0100, Jean-Philippe Brucker wrote:
> On Mon, Jul 01, 2024 at 11:02:40AM +, Mostafa Saleh wrote:
> > QEMU doesn's support memory attributes, so FWB is NOP, this
> > might change in the future if memory attributre would be supported.
> >
> > Signed-o
Hi Eric,
On Mon, Jul 08, 2024 at 07:09:02PM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 7/4/24 20:36, Jean-Philippe Brucker wrote:
> > On Mon, Jul 01, 2024 at 11:02:40AM +, Mostafa Saleh wrote:
> >> QEMU doesn's support memory attributes, so FWB is NOP, this
> >> might change in the future
On Mon, 8 Jul 2024 at 21:49, Paolo Bonzini wrote:
>
>
>
> Il lun 8 lug 2024, 20:39 Manos Pitsidianakis
> ha scritto:
>>
>>
>>
>> On Mon, 8 Jul 2024, 21:34 Paolo Bonzini, wrote:
>>>
>>>
>>>
>>> Il lun 8 lug 2024, 19:12 Daniel P. Berrangé ha
>>> scritto:
That's exactly why I suggest i
On Mon, Jul 08, 2024 at 05:49:32PM +1000, Nicholas Piggin wrote:
> On Sun Jul 7, 2024 at 9:46 AM AEST, David Gibson wrote:
> > On Sat, Jul 06, 2024 at 11:37:08AM +0100, Peter Maydell wrote:
> > > On Fri, 5 Jul 2024 at 06:13, David Gibson
> > > wrote:
> > > >
> > > > On Fri, Jul 05, 2024 at 02:40:
On Mon, Jul 08, 2024 at 04:59:30PM +0100, Peter Maydell wrote:
> On Mon, 8 Jul 2024 at 08:49, Nicholas Piggin wrote:
> >
> > On Sun Jul 7, 2024 at 9:46 AM AEST, David Gibson wrote:
> > > On Sat, Jul 06, 2024 at 11:37:08AM +0100, Peter Maydell wrote:
> > > > On Fri, 5 Jul 2024 at 06:13, David Gibso
On Tue, Jul 9, 2024 at 9:38 AM Manos Pitsidianakis
wrote:
> Ah, alright. That wasn't obvious because that e-mail was not directed
> to me nor did it mention my name :)
Oh, ok. Sorry about that. Generally when I say "we" I include as large
a part of the community as applicable.
> I do not want to
Hi Mostafa,
On 7/9/24 09:18, Mostafa Saleh wrote:
> Hi Eric,
>
> On Mon, Jul 08, 2024 at 05:19:59PM +0200, Eric Auger wrote:
>> Hi Mostafa,
>>
>> On 7/1/24 13:02, Mostafa Saleh wrote:
>>> When nested translation is requested, do the following:
>>>
>>> - Translate stage-1 table address IPA into PA
On Mon, 8 Jul 2024 23:30:01 +
Salil Mehta wrote:
> Hi Igor,
>
> On 08/07/2024 13:32, Igor Mammedov wrote:
> > On Sat, 6 Jul 2024 15:43:01 +
> > Salil Mehta wrote:
> >
> >> Hi Igor,
> >> Thanks for taking out time to review.
> >>
> >> On Sat, Jul 6, 2024 at 1:12 PM Igor Mammedov wrote
On Mon, May 6, 2024 at 2:26 PM Markus Armbruster wrote:
> Looks like this fell through the cracks. Is anyone familiar with LUKS
> willing to review it?
>
:) Ping?
>
> Hyman Huang writes:
>
> > Signed-off-by: Hyman Huang
> > ---
> > MAINTAINERS | 1 +
> > docs/devel
On 9/7/24 02:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 94 +-
target/arm/tcg/a64.decode | 3 ++
2 files changed, 15 insertions(+), 82 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
> -Original Message-
> From: Yichen Wang
> Sent: Saturday, July 6, 2024 2:29 AM
> To: Paolo Bonzini ; Daniel P. Berrangé
> ; Eduardo Habkost ; Marc-André
> Lureau ; Thomas Huth ;
> Philippe Mathieu-Daudé ; Peter Xu ;
> Fabiano Rosas ; Eric Blake ; Markus
> Armbruster ; Laurent Vivier ; qem
Two new regs added: ztso and zacas.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 1047961fed..f6e3156b8d 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/targe
On 09/07/2024 04:43, Duan, Zhenzhong wrote:
> Hi Joao,
>
>> -Original Message-
>> From: Joao Martins
>> Subject: [PATCH v3 01/10] vfio/iommufd: Don't fail to realize on
>> IOMMU_GET_HW_INFO failure
>>
>> mdevs aren't "physical" devices and when asking for backing IOMMU info, it
>> fails t
On 09/07/2024 07:20, Cédric Le Goater wrote:
> On 7/8/24 5:32 PM, Joao Martins wrote:
>> On 08/07/2024 16:28, Cédric Le Goater wrote:
>>> Hello Joao,
>>>
>>> On 7/8/24 4:34 PM, Joao Martins wrote:
In preparation to implement auto domains have the attach function
return the errno it got du
On 09/07/2024 07:26, Duan, Zhenzhong wrote:
>
>
>> -Original Message-
>> From: Joao Martins
>> Subject: [PATCH v3 04/10] vfio/iommufd: Introduce auto domain creation
>>
>> There's generally two modes of operation for IOMMUFD:
>>
>> * The simple user API which intends to perform relativel
On 09/07/2024 07:28, Cédric Le Goater wrote:
> On 7/8/24 4:34 PM, Joao Martins wrote:
>> diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
>> index 2ca9a32cc7b6..1b5b46d28ed6 100644
>> --- a/hw/vfio/iommufd.c
>> +++ b/hw/vfio/iommufd.c
>> @@ -212,6 +212,20 @@ static bool iommufd_cdev_detach_ioas_h
On 09/07/2024 07:50, Cédric Le Goater wrote:
> On 7/8/24 4:34 PM, Joao Martins wrote:
>> There's generally two modes of operation for IOMMUFD:
>>
>> * The simple user API which intends to perform relatively simple things
>> with IOMMUs e.g. DPDK. It generally creates an IOAS and attach to VFIO
>> a
On 09/07/2024 08:02, Cédric Le Goater wrote:
> On 7/8/24 4:34 PM, Joao Martins wrote:
>> By default VFIO migration is set to auto, which will support live
>> migration if the migration capability is set *and* also dirty page
>> tracking is supported.
>>
>> For testing purposes one can force enable
Hi Nicolin,
On 6/26/24 02:28, Nicolin Chen wrote:
> A nested SMMU must use iommufd ioctls to communicate with the host-level
> SMMU instance for 2-stage translation support. Add an iommufd link to the
> ARM virt-machine, allowing QEMU command to pass in an iommufd object.
If I am not wrong vfio de
On 09/07/2024 08:05, Cédric Le Goater wrote:
> On 7/8/24 4:34 PM, Joao Martins wrote:
>> ioctl(iommufd, IOMMU_HWPT_GET_DIRTY_BITMAP, arg) is the UAPI
>> that fetches the bitmap that tells what was dirty in an IOVA
>> range.
>>
>> A single bitmap is allocated and used across all the hwpts
>> sharing
On 09/07/2024 08:07, Cédric Le Goater wrote:
> On 7/8/24 4:34 PM, Joao Martins wrote:
>> ioctl(iommufd, IOMMU_HWPT_SET_DIRTY_TRACKING, arg) is the UAPI that
>> enables or disables dirty page tracking. It is used if the hwpt
>> has been created with dirty tracking supported domain (stored in
>> hwpt
Hi Nicolin,
On 6/26/24 02:28, Nicolin Chen wrote:
> Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
> instance(s). Add a helper to read the sysfs for the number of instances.
> Log them in a vms list using a new struct VirtNestedSmmu.
>
> This will be used by a following p
On Mon, 8 Jul 2024 at 19:18, Roman Kiryanov wrote:
>
> void* pointer arithmetic is a GCC extentension
> which could not be available in other build tools
> (e.g. C++). This changes removes this assumption.
>
> Signed-off-by: Roman Kiryanov
We had the question on a previous "make this C++
compati
On 7/4/24 10:29 AM, Jamin Lin wrote:
change from v1:
- ftgmac100
- fix coding style
- support 64 bits dma dram address for AST2700
change from v2:
- ftgmac100: update memory region size to 0x200.
- ftgmac100: introduce a new class(ftgmac100_high),
class attribute and memop handlers, for
> diff --git a/hw/core/smp-cache.c b/hw/core/smp-cache.c
> new file mode 100644
> index ..c0157ce51c8f
> --- /dev/null
> +++ b/hw/core/smp-cache.c
> @@ -0,0 +1,103 @@
> +/*
> + * Cache Object for SMP machine
> + *
> + * Copyright (C) 2024 Intel Corporation.
> + *
> + * Author: Zhao Liu
> From: Igor Mammedov
> Sent: Tuesday, July 9, 2024 9:06 AM
> To: Salil Mehta
>
> On Mon, 8 Jul 2024 23:30:01 +
> Salil Mehta wrote:
>
> > Hi Igor,
> >
> > On 08/07/2024 13:32, Igor Mammedov wrote:
> > > On Sat, 6 Jul 2024 15:43:01 +
> > > Salil Mehta wrote:
> > >
> > >
On 24-07-02 05:52:45, CLEMENT MATHIEU--DRIF wrote:
> From: Clément Mathieu--Drif
>
> Devices implementing ATS can send translation requests using
> pci_ats_request_translation_pasid.
>
> The invalidation events are sent back to the device using the iommu
> notifier managed with pci_register_iomm
John Snow writes:
> On Sat, Jul 6, 2024, 10:47 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Factor out the compatibility parser helper into a base class, so it can
>> > be shared by other directives.
>> >
>> > Signed-off-by: John Snow
>>
>> R-by stands.
>
> Assuming true even if
John Snow writes:
> This is a directive that creates a syntactic sugar for creating
> "Example" boxes very similar to the ones already used in the bitmaps.rst
> document, please see e.g.
> https://www.qemu.org/docs/master/interop/bitmaps.html#creation-block-dirty-bitmap-add
>
> In its simplest fo
John Snow writes:
> For any code literal blocks inside of a qmp-example directive, apply and
> enforce the QMP lexer/highlighter to those blocks.
>
> This way, you won't need to write:
>
> ```
> .. qmp-example::
>:annotated:
>
>Blah blah
>
>.. code-block:: QMP
>
> -> { "lorem":
John Snow writes:
> From: Harmonie Snow
>
> Add CSS styling for qmp-example directives to increase readability and
> consistently style all example blocks.
>
> Signed-off-by: Harmonie Snow
> Signed-off-by: John Snow
Same sadness as for the previous patch.
Acked-by: Markus Armbruster
On Mon, 8 Jul 2024 at 21:39, Manos Pitsidianakis
wrote:
>
>
>
> On Mon, 8 Jul 2024, 21:34 Paolo Bonzini, wrote:
>>
>>
>>
>> Il lun 8 lug 2024, 19:12 Daniel P. Berrangé ha scritto:
>>>
>>> That's exactly why I suggest its a pre-requisite for merging
>>> this. Unless we're able to demonstrate that
John Snow writes:
> Fully eliminate the "Example" sections in QAPI doc blocks now that they
> have all been converted to arbitrary rST syntax using the
> ".. qmp-example::" directive. Update tests to match.
>
> Migrating to the new syntax
> ---
>
> The old "Example:" or "E
Manos Pitsidianakis writes:
> Add mechanism to generate rust hw targets that depend on a custom
> bindgen target for rust bindings to C.
>
> This way bindings will be created before the rust crate is compiled.
>
> The bindings will end up in BUILDDIR/{target}-generated.rs and have the same
> nam
John Snow writes:
> On Sat, Jul 6, 2024, 10:42 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Use the no-option form of ".. qmp-example::" to convert any Examples
>> > that do not have any form of caption or explanation whatsoever. Note
>> > that in a few cases, example sections are
John Snow writes:
> When an Example section has a brief explanation, convert it to a
> qmp-example:: section using the :title: option.
>
> Rule of thumb: If the title can fit on a single line and requires no rST
> markup, it's a good candidate for using the :title: option of
> qmp-example.
>
> In
John Snow writes:
> These examples require longer explanations or have explanations that
> require markup to look reasonable when rendered and so use the longer
> form of the ".. qmp-example::" directive.
>
> By using the :annotated: option, the content in the example block is
> assumed *not* to
Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
additionally defines 8 MOP instructions named MOP.RR.n, where n
is an integer between 0 and 7.
These 40 MOPs i
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Deepak Gupta
---
disas/riscv.c | 98 +++
1 file changed, 98 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 90d6b26de9..0b82ab2322 100644
--- a/disas/riscv.c
+++ b/d
Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
the reserved encoding space corresponding to C.LUI xn, 0.
Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
are defined to not write any re
I once used a wrong major opcode for zimop. It should use 0x73 as major opcode.
This was detected after I got a toolchain with zimop support. Before that, I
tested
this implementation with hardwire code instruction instead of assemble code.
This patch set has been queued to alistair/riscv-to-appl
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei
Acked-by: Ali
Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to AMOs, loads
and stores defined in the base ISAs, and loads and stores of no more
than XLEN bits defined in the F, D, and Q exten
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 21 -
target/riscv/translate.c| 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.in
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131
target/riscv/translate.c| 4 +-
4 fil
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/translate.c| 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
b
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3bad6372
Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Signe
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate.c | 10 --
target/ppc/translat
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5219b44176..8cd52e6801 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -117,6 +117,7 @@ const RISCVIsaExt
Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future
use.
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
Updating a bunch of VMX and VSX storage access instructions to use
tcg_gen_qemu_ld/st_i128 instead of using tcg_gen_qemu_ld/st_i64 in
succession; as suggested by Richard, in my decodetree patches.
Plus some minor clean-ups to facilitate the above in case of VMX insns.
Change log:
v3 : Rectified E
On 09/07/2024 09:56, Joao Martins wrote:
> On 09/07/2024 04:43, Duan, Zhenzhong wrote:
>> Hi Joao,
>>
>>> -Original Message-
>>> From: Joao Martins
>>> Subject: [PATCH v3 01/10] vfio/iommufd: Don't fail to realize on
>>> IOMMU_GET_HW_INFO failure
>>>
>>> mdevs aren't "physical" devices and
Hi Philippe/Jiaxun,
Could you do me a favor giving a review about this patch?
Regards
Bibo Mao
On 2024/7/4 上午11:37, Bibo Mao wrote:
Now loongson ipi and loongarch ipi share the same code with different
macro, loongson ipi has its separate function such mmio region,
loongarch ipi has other requ
On Tue, 9 Jul 2024 at 11:53, Alex Bennée wrote:
>
> Manos Pitsidianakis writes:
> > +msrv = {
> > + 'rustc': '1.77.2',
> > + 'cargo': '1.77.2',
> > + 'bindgen': '0.69.4',
> > +}
>
> This is still pretty bleeding edge (it even tripped up on the
> .cargo/bin/cargo I have installed). This needs t
On 09/07/2024 12:45, Joao Martins wrote:
> On 09/07/2024 09:56, Joao Martins wrote:
>> On 09/07/2024 04:43, Duan, Zhenzhong wrote:
>>> Hi Joao,
>>>
-Original Message-
From: Joao Martins
Subject: [PATCH v3 01/10] vfio/iommufd: Don't fail to realize on
IOMMU_GET_HW_INFO f
Extend the 'mte' property for the virt machine to cover KVM as
well. For KVM, we don't allocate tag memory, but instead enable
the capability.
If MTE has been enabled, we need to disable migration, as we do not
yet have a way to migrate the tags as well. Therefore, MTE will stay
off with KVM unles
On Tue, Jul 09, 2024 at 09:54:43AM +0200, Paolo Bonzini wrote:
> On Tue, Jul 9, 2024 at 9:38 AM Manos Pitsidianakis
> wrote:
> > Ah, alright. That wasn't obvious because that e-mail was not directed
> > to me nor did it mention my name :)
>
> Oh, ok. Sorry about that. Generally when I say "we" I
From: Jamin Lin
Update TX and RX ring base address data type to uint64_t for
64 bits dram address DMA support.
Both "Normal Priority Transmit Ring Base Address Register(0x20)" and
"Receive Ring Base Address Register (0x24)" are used for saving the
low part physical address of descriptor manager.
From: Eric Auger
In 94df5b2180d6 ("virtio-iommu: Fix 64kB host page size VFIO device
assignment"), in case of bypass mode, we transiently enabled the
IOMMU MR to allow the set_page_size_mask() to be called and pass
information about the page size mask constraint of cold plugged
VFIO devices. Now
From: Eric Auger
This callback will be used to retrieve the page size mask supported
along a given Host IOMMU device.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
Reviewed-by: Michael S. Tsirkin
---
include/hw/vfio/vfio-container-base.h | 7 +++
i
From: Zhenzhong Duan
EDID related device region info is leaked in vfio_display_edid_init()
error path and VFIODisplay destroying path.
Fixes: 08479114b0de ("vfio/display: add edid support.")
Signed-off-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
Reviewed-by: Marc-André Lureau
---
hw/vfi
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index d29cb1ff7d..c8364c2b07 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6 +954
On Tue, Jul 9, 2024 at 2:09 PM Peter Maydell wrote:
> * what is the actual baseline requirement? We definitely want
>to support "using rustup on an older system" (should be no
>problem) and "current distro building QEMU using the distro's
>rust", I assume. It would certainly be nice t
From: Eric Auger
Introduce vfio_container_get_iova_ranges() to retrieve the usable
IOVA regions of the base container and use it in the Host IOMMU
device implementations of get_iova_ranges() callback.
We also fix a UAF bug as the list was shallow copied while
g_list_free_full() was used both on
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
Set dma64 property for ftgmac100 model to support
64bits dram address DMA.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/asp
From: David Woodhouse
While refactoring the NIC initialization code, I broke '-net nic,model=help'
which no longer outputs a list of available NIC models.
Fixes: 2cdeca04adab ("net: report list of available models according to
platform")
Signed-off-by: David Woodhouse
---
net/net.c | 25 +
On 09/07/2024 10:13, Joao Martins wrote:
> On 09/07/2024 08:05, Cédric Le Goater wrote:
>> On 7/8/24 4:34 PM, Joao Martins wrote:
>>> ioctl(iommufd, IOMMU_HWPT_GET_DIRTY_BITMAP, arg) is the UAPI
>>> that fetches the bitmap that tells what was dirty in an IOVA
>>> range.
>>>
>>> A single bitmap is a
From: Jamin Lin
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" command to get the QE bit
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Normal Priority Transmit Ring Base Address Register High(0x17C)",
"High Priority Transmit Ring Base Address Register High(0x184)" and
"Rece
From: Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "TXDES 2" and "RXDES 2" to save the high part
physical address of packet buffer.
Ex: TX packet buffer address [34:0]
The "TXDES 2" bits [18:
09.07.2024 15:34, David Woodhouse wrote:
From: David Woodhouse
While refactoring the NIC initialization code, I broke '-net nic,model=help'
which no longer outputs a list of available NIC models.
Fixes: 2cdeca04adab ("net: report list of available models according to
platform")
Signed-off-by:
From: Jamin Lin
Update test case to test ASPEED OpenBMC SDK v09.02 for AST2700.
ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c.
It is required to use ASPEED OpenBMC SDK since v09.02
for AST2700 QEMU network testing.
A test image is downloaded from the ASPEED Forked OpenBMC GitHub
rel
From: Jamin Lin
Update test case to test network connection via SSH.
Test command:
```
cd build
pyvenv/bin/avocado run
../qemu/tests/avocado/machine_aspeed.py:AST2x00MachineSDK.test_aarch64_ast2700_evb_sdk_v09_02
```
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/m
On 09/07/2024 10:04, Joao Martins wrote:
> On 09/07/2024 07:28, Cédric Le Goater wrote:
>> On 7/8/24 4:34 PM, Joao Martins wrote:
>>> diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
>>> index 2ca9a32cc7b6..1b5b46d28ed6 100644
>>> --- a/hw/vfio/iommufd.c
>>> +++ b/hw/vfio/iommufd.c
>>> @@ -212,6
The following changes since commit 44b7329de469c121555a1acf9b288f3ae71b8e61:
Merge tag 'pull-qapi-2024-07-06' of https://repo.or.cz/qemu/armbru into
staging (2024-07-07 13:23:28 -0700)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-vfio-202
From: Zhenzhong Duan
vfio_display_edid_init() can fail for many reasons and return silently.
It would be good to report the error.
Old mdev driver may not support vfio edid region and we allow to go
through in this case.
vfio_display_edid_update() isn't changed because it can be called at
runti
On 09/07/2024 12:15, Minwoo Im wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On 24-07-02 05:52:45, CLEMENT MATHIEU--DRIF wrote:
>> From: Clément Mathieu--Drif
>>
>> Devices implemen
The following changes since commit 44b7329de469c121555a1acf9b288f3ae71b8e61:
Merge tag 'pull-qapi-2024-07-06' of https://repo.or.cz/qemu/armbru into
staging (2024-07-07 13:23:28 -0700)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-202
From: Jamin Lin
According to the datasheet of ASPEED SOCs,
one MAC controller owns 128KB of register space for AST2500.
However, one MAC controller only owns 64KB of register space for AST2600
and AST2700. It set the memory region size 128KB and it occupied another
controllers Address Spaces.
Up
From: Eric Auger
The error handle argument is not used anywhere. let's remove it.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
Reviewed-by: Michael S. Tsirkin
---
include/sysemu/host_iommu_device.h | 3 +--
hw/vfio/container.c| 2 +-
hw
From: Eric Auger
Retrieve the Host IOMMU Device page size mask when this latter is set.
This allows to get the information much sooner than when relying on
IOMMU MR set_page_size_mask() call, whcih happens when the IOMMU MR
gets enabled. We introduce check_page_size_mask() helper whose code
is in
From: Eric Auger
In case no IOMMUPciBus/IOMMUDevice are found we need to properly
set the error handle and return.
Fixes : Coverity CID 1549006
Signed-off-by: Eric Auger
Fixes: cf2647a76e ("virtio-iommu: Compute host reserved regions")
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
Hi Mostafa,
On Tue, Jul 09, 2024 at 07:12:59AM +, Mostafa Saleh wrote:
> > In this case I think we're reporting InputAddr as the CD address, but it
> > should be the IOVA
>
> As Eric mentioned this would require some rework to propagate the iova,
> but what I am more worried about is the read
On Tue, Jul 09, 2024 at 02:28:38PM +0200, Paolo Bonzini wrote:
> On Tue, Jul 9, 2024 at 2:09 PM Peter Maydell wrote:
> > * what is the actual baseline requirement? We definitely want
> >to support "using rustup on an older system" (should be no
> >problem) and "current distro building QEM
From: Eric Auger
Everything is now in place to use the Host IOMMU Device callbacks
to retrieve the page size mask usable with a given assigned device.
This new method brings the advantage to pass the info much earlier
to the virtual IOMMU and before the IOMMU MR gets enabled. So let's
remove the
Hi Nicolin,
On 6/26/24 02:28, Nicolin Chen wrote:
> VIRT_SMMU can be used as an emulated SMMU, i.e. iommu=smmuv3. However, the
> MMIO space for VIRT_SMMU isn't large enough to accommodate multiple nested
> SMMUv3 instances. Add a new VIRT_NESTED_SMMU to separate MMIO space.
>
> Meanwhile, a nested
On 6/26/24 02:28, Nicolin Chen wrote:
> With iommu=nested-smmuv3, there could be multiple nested SMMU instances in
> the vms. A passthrough device must to look up for its iommu handler in its
> sysfs node, and then link to the nested SMMU instance created for the same
> iommu handler. This isn't
In commit c1a1f80518d360b when we added the FEAT_LSE2 relaxations to
the alignment requirements for atomic and ordered loads and stores,
we didn't quite get it right for LDAPR/LDAPRH/LDAPRB with no
immediate offset. These instructions were handled in the old decoder
as part of disas_ldst_atomic(),
Patch 1 here fixes https://gitlab.com/qemu-project/qemu/-/issues/2419
which is a bug in the LDAPR/STLR-immediate insns that I introduced
when I did the decodetree conversion: the immediate field should be
signed, not unsigned.
Patch 2 is an unrelated bug that I happened to notice when I was
lookin
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