Re: [PATCH v1 2/2] xen: mapcache: Fix unmapping of first entries in buckets

"Edgar E. Iglesias" writes: > On Thu, Jul 4, 2024 at 9:48 PM Edgar E. Iglesias > wrote: > > On Thu, Jul 04, 2024 at 05:44:52PM +0100, Alex Bennée wrote: > > Anthony PERARD writes: > > > > > On Tue, Jul 02, 2024 at 12:44:21AM +0200, Edgar E. Iglesias wrote: > > >> From: "Edgar E. Iglesias

[PATCH v3 0/3] Connect STM32L4x5 USART devices to the EXTI

STM32L4x5 EXTI was handling only configurable interrupts (such as those coming from STM32L4x5 SYSCFG which was the only device connected to the EXTI). This patch adds support for direct line interrupts and connects the existing STM32L4x5 USART devices to the EXTI. The patch also corrects the handli

[PATCH v3 1/3] hw/misc: In STM32L4x5 EXTI, consolidate 2 constants

Up until now, the EXTI implementation had 16 inbound GPIOs connected to the 16 outbound GPIOs of STM32L4x5 SYSCFG. The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART devices which are already implemented in QEMU). In order to connect USART devices to EXTI, this commit consolidates co

[PATCH v3 3/3] hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI

The USART devices were previously connecting their outbound IRQs directly to the CPU because the EXTI wasn't handling direct lines interrupts. Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects its IRQs to the CPU. The existing QTest for the USART (tests/qtest/stm32l4x5_usart-t

[PATCH v3 2/3] hw/misc: In STM32L4x5 EXTI, handle direct interrupts

The previous implementation for EXTI interrupts only handled "configurable" interrupts, like those originating from STM32L4x5 SYSCFG (the only device currently connected to the EXTI up until now). In order to connect STM32L4x5 USART to the EXTI, this commit adds handling for direct interrupts (int

[PATCH] char-mux: Don't overwrite the receive buffer

This commit fixes a bug that causes incorrect results when pasting more than 32 bytes, the size of the receive buffer b->buffer, into the virtio console. Example (note that the last 32 bytes are always correct, but something goes wrong just before the last 32 bytes): Pasting abcdefghijk

Re: [PATCH] char-mux: Don't overwrite the receive buffer

Hi On Sun, Jul 7, 2024 at 3:26 PM Ruihan Li wrote: > This commit fixes a bug that causes incorrect results when pasting more > than 32 bytes, the size of the receive buffer b->buffer, into the virtio > console. > > Example (note that the last 32 bytes are always correct, but something > goes wro

Re: [PATCH RFC v4] virtio: Implement Virtio Backend for SD/MMC in QEMU

> 6 июля 2024 г., в 18:48, Mikhail Krasheninnikov > написал(а): > > From: Mi > > Add a Virtio backend for SD/MMC devices. Confirmed interoperability with > Linux. > > Linux patch link: > https://lore.kernel.org/linux-mmc/20240701120642.30001-1-krashmi...@gmail.com/ > > Signed-off-by: Mikh

[PATCH v1 1/1] target/i386: Add VMX entry load FRED control name to VMX feature words

As VMX entry load FRED control is required to enable FRED in nested VMX, add it to VMX feature words. Signed-off-by: Xin Li (Intel) --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c05765eeaf..84a09c19cf 100644

Re: [PATCH v6 7/7] tests/tcg/x86_64: add test for plugin memory access

On 7/6/24 12:13, Pierrick Bouvier wrote: +++ b/tests/tcg/x86_64/test-plugin-mem-access.c @@ -0,0 +1,89 @@ +#include +#include All new files should have license boilerplate and description. You can use spdx to limit to just a couple of lines. r~

[PATCH v2 8/8] bsd-user:Add AArch64 improvements and signal handling functions

From: Stacey Son Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags indicating interrupts or exceptions are set. Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency. Chan

[PATCH v2 2/8] bsd-user:Add AArch64 register handling and related functions

From: Stacey Son Added header file for managing CPU register states in FreeBSD user mode. Introduced prototypes for setting and getting thread-local storage (TLS). Implemented AArch64 sysarch() system call emulation and a printing function. Added function for setting up thread upcall to add threa

[PATCH v2 3/8] bsd-user:Add ARM AArch64 support and capabilities

From: Warner Losh Added function to access rval2 by accessing the x1 register. Defined ARM AArch64 ELF parameters including mmap and dynamic load addresses. Introduced extensive hardware capability definitions and macros for retrieving hardware capability (hwcap) flags. Implemented function to r

[PATCH v2 0/8] ARM AArch64 Support for BSD

Patch 1: Previous patches 1 to 5, which were reviewed and acked, have been folded into this patch.Some changes that were suggested, such as replacing "pstate &= ~PSTATE_C" with faster constructs like "env->CF = 0", have been addressed in patch 8. Patch 2: In this patch, patches 6 to 11 h

[PATCH v2 5/8] bsd-user:Add get_mcontext function for ARM AArch64

From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans --- bsd-user/aarch64/signal.c | 30

[PATCH v2 6/8] bsd-user:Add setup_sigframe_arch function for ARM AArch64

From: Warner Losh The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/aarch64/signal.c | 14 ++ 1 file changed, 14 insertion

[PATCH v2 1/8] bsd-user:Add CPU initialization and management functions

From: Stacey Son Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to

[PATCH v2 7/8] bsd-user:Add set_mcontext function for ARM AArch64

From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers. Note:FP is unfinished upstream but will be a separate commit coming soon. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 22 ++

[PATCH v2 4/8] bsd-user:Add ARM AArch64 signal handling support

From: Stacey Son Added sigcode setup function for signal trampoline which initializes a sequence of instructions to handle signal returns and exits, copying this code to the target offset. Defined ARM AArch64 specific signal definitions including register indices and sizes, and introduced struc

Re: [PATCH] char-mux: Don't overwrite the receive buffer

Hi, Thanks for your quick review! On Sun, Jul 07, 2024 at 08:28:50PM GMT, Marc-André Lureau wrote: > Hi > > On Sun, Jul 7, 2024 at 3:26 PM Ruihan Li wrote: > > > This commit fixes a bug that causes incorrect results when pasting more > > than 32 bytes, the size of the receive buffer b->buffer,

Re: [PULL 00/16] SD/MMC patches for 2024-07-06

On 7/5/24 15:04, Philippe Mathieu-Daudé wrote: The following changes since commit f2cb4026fccfe073f84a4b440e41d3ed0c3134f6: Merge tag 'pull-maintainer-july24-050724-1' ofhttps://gitlab.com/stsquad/qemu into staging (2024-07-05 09:15:48 -0700) are available in the Git repository at: htt

Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote: > > Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. > Therefore, the encoding of the MODE should also be restricted to 0 and 1. > > Signed-off-by: Jiayi Li Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cs

RE: [PATCH v4] hw/core/loader: allow loading larger ROMs

Reviewed-by: Xingtao Yao > -Original Message- > From: Gregor Haas > Sent: Saturday, June 29, 2024 2:27 AM > To: qemu-devel@nongnu.org > Cc: berra...@redhat.com; Yao, Xingtao/姚 幸涛 ; > Gregor Haas > Subject: [PATCH v4] hw/core/loader: allow loading larger ROMs > > The read() syscall is n

Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On 2024/7/1 10:25, Jiayi Li wrote: Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li --- target/riscv/csr.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-)

Re: [PATCH] target/riscv: Validate the mode in write_vstvec

On Mon, Jul 1, 2024 at 3:42 PM Jiayi Li wrote: > > Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. > Therefore, the encoding of the MODE should also be restricted to 0 and 1. > > Signed-off-by: Jiayi Li Thanks! Applied to riscv-to-apply.next Alistair > --- > target

[PULL 0/1] ufs queue

From: Jeuk Kim The following changes since commit b9ee1387e0cf0fba5a73a610d31cb9cead457dc0: Merge tag 'sdmmc-20240706' of https://github.com/philmd/qemu into staging (2024-07-07 10:34:52 -0700) are available in the Git repository at: https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20

[PULL 1/1] hw/ufs: Fix mcq register range determination logic

From: Jeuk Kim The function ufs_is_mcq_reg() only evaluated the range of the mcq_op_reg offset, which is defined as a constant. Therefore, it was possible for ufs_is_mcq_reg() to return true despite ufs device is configured to not support the mcq. This could cause ufs_mmio_read()/ufs_mmio_write()

Re: [PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU

On Thu, Jul 4, 2024 at 12:53 AM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an > RV64 QEMU. > > Signed-off-by: TANG Tiancheng > Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") > Reviewed-by: Liu Zhiwei

Re: [PATCH] i386/cpu: Drop the check of phys_bits in host_cpu_realizefn()

Hi Xiaoyao, On Thu, Jul 04, 2024 at 07:12:31AM -0400, Xiaoyao Li wrote: > Date: Thu, 4 Jul 2024 07:12:31 -0400 > From: Xiaoyao Li > Subject: [PATCH] i386/cpu: Drop the check of phys_bits in > host_cpu_realizefn() > X-Mailer: git-send-email 2.34.1 > > The check of cpu->phys_bits to be in range

Re: [PATCH 0/3] target/i386/cpu: Misc Cleanup on host-cache-info

Hi Igor, Just a gentle poke and what do you think about this minor series? Thanks, Zhao On Wed, Jun 19, 2024 at 10:42:12PM +0800, Zhao Liu wrote: > Date: Wed, 19 Jun 2024 22:42:12 +0800 > From: Zhao Liu > Subject: [PATCH 0/3] target/i386/cpu: Misc Cleanup on host-cache-info > X-Mailer: git-send

Re: [PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation

On Thu, Jul 4, 2024 at 7:33 PM Peter Maydell wrote: > > On Wed, 3 Jul 2024 at 22:32, Zheyu Ma wrote: > > > > The sifive_plic_read function in hw/intc/sifive_plic.c had a potential > > heap-buffer-overflow issue when reading from the pending_base region. > > This occurred because the code did not

Re: [PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support

On Sat, Jul 6, 2024 at 7:26 AM Daniel Henrique Barboza wrote: > > Hi, > > Would it make it easier for review if we squash patch 3: > > [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation > > and patch 8: > > [PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support > > In the s

Re: [PATCH v2] disas/riscv: Add decode for Zawrs extension

On Sat, Jul 6, 2024 at 2:54 AM Rob Bradford wrote: > > From: Balaji Ravikumar > > Add disassembly support for these instructions from Zawrs: > > * wrs.sto > * wrs.nto > > Signed-off-by: Balaji Ravikumar > Signed-off-by: Rob Bradford Acked-by: Alistair Francis Alistair > --- > disas/riscv.c

Re: [PATCH v2] disas/riscv: Add decode for Zawrs extension

On Sat, Jul 6, 2024 at 2:54 AM Rob Bradford wrote: > > From: Balaji Ravikumar > > Add disassembly support for these instructions from Zawrs: > > * wrs.sto > * wrs.nto > > Signed-off-by: Balaji Ravikumar > Signed-off-by: Rob Bradford Thanks! Applied to riscv-to-apply.next Alistair > --- > d

Re: [PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64

On Thu, Jul 4, 2024 at 12:54 AM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Ensure correct bit width based on sxl when running RV32 on RV64 QEMU. > This is required as MMU address translations run in S-mode. > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei > --- > target/riscv/cp

Re: [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU

On Thu, Jul 4, 2024 at 12:55 AM LIU Zhiwei wrote: > > From: TANG Tiancheng > > Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs > in RV64 QEMU. > > Signed-off-by: TANG Tiancheng > Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Alistair > --- > configs/targe

Re: [PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64

On Thu, Jul 4, 2024 at 12:55 AM LIU Zhiwei wrote: > > From: TANG Tiancheng > > To regularly test booting Linux with rv32 on QEMU RV64, > we have added a test to boot_linux_console.py to retrieve > cpuinfo and verify if it shows 'rv32' when using RV64 to > boot rv32 CPUs. > > Signed-off-by: TANG T

Re: [PATCH v1 1/1] target/i386: Add VMX entry load FRED control name to VMX feature words

On Sun, Jul 07, 2024 at 11:10:57AM -0700, Xin Li (Intel) wrote: > Date: Sun, 7 Jul 2024 11:10:57 -0700 > From: "Xin Li (Intel)" > Subject: [PATCH v1 1/1] target/i386: Add VMX entry load FRED control name > to VMX feature words > X-Mailer: git-send-email 2.45.2 > > As VMX entry load FRED control

Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V

On Thu, Jul 4, 2024 at 12:57 AM Sunil V L wrote: > > On Wed, Jul 03, 2024 at 03:53:08PM +0530, Sunil V L wrote: > > On Tue, Jul 02, 2024 at 03:02:36PM +0100, Jonathan Cameron wrote: > > > On Mon, 1 Jul 2024 17:03:43 -0400 > > > "Michael S. Tsirkin" wrote: > > > > > > > On Thu, Jun 27, 2024 at 02:

[PATCH] MAINTAINERS: Add myself as a VT-d reviewer

Signed-off-by: Yi Liu --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6725913c8b..61724b91d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3656,6 +3656,7 @@ F: tests/uefi-test-tools/ VT-d Emulation M: Michael S. Tsirkin R: Jason Wang +R: Y

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Sat, Jul 6, 2024 at 4:30 AM Hyman Huang wrote: > > Unexpected work by certain Windows guests equipped with the e1000 > interface can cause the network to go down and never come back up > again unless the guest's interface is reset. > > To reproduce the failure: > 1. Set up two guests with a Win

Re: [PATCH] MAINTAINERS: Add myself as a VT-d reviewer

On Mon, Jul 8, 2024 at 11:21 AM Yi Liu wrote: > > Signed-off-by: Yi Liu > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 6725913c8b..61724b91d8 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -3656,6 +3656,7 @@ F: tests/uefi-test-

Re: [PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

On Wed, Jul 3, 2024 at 1:29 PM ~liuxu wrote: > > From: lxx <1733205...@qq.com> > > This patch adds support for the Zilsd and Zcmlsd extension, > which is documented at > https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 > > Co-developed-by: SUN Dongya > Co-developed-by: LIU Xu > Co-devel

Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH] target/riscv: Fix the check with vector register multiples of LMUL

On Fri, Jun 28, 2024 at 7:46 PM Zhiwei Jiang wrote: > > In the original extract32(val, 0, lmul) logic, when lmul is 2 and val is v10 > or v12, > there is an issue with this check condition. I think a simple mod operation > is sufficient. Overall looks ok. Do you mind updating the commit message

[PATCH 1/1] pci: don't skip function 0 occupancy verification for devfn auto assign

When the devfn is already assigned in the command line, the do_pci_register_device() may verify if the function 0 is already occupied. However, when devfn < 0, the verification is skipped because it is part of the last "else if". For instance, suppose there is already a device at addr=00.00 of a

Re: [PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V

On Mon, Jul 08, 2024 at 01:16:49PM +1000, Alistair Francis wrote: > On Thu, Jul 4, 2024 at 12:57 AM Sunil V L wrote: > > > > On Wed, Jul 03, 2024 at 03:53:08PM +0530, Sunil V L wrote: > > > On Tue, Jul 02, 2024 at 03:02:36PM +0100, Jonathan Cameron wrote: > > > > On Mon, 1 Jul 2024 17:03:43 -0400

Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

On Wed, Jun 26, 2024 at 3:53 PM Ethan Chen wrote: > > On Wed, Jun 26, 2024 at 11:22:46AM +1000, Alistair Francis wrote: > > > > On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote: > > > > > > Hi Alistair, > > > > > > IOPMP can applies all device. In this patch series, PCI devices on the > > > bri

[PATCH v9] virtio-net: Fix network stall at the host side waiting for kick

From: thomas Patch 06b12970174 ("virtio-net: fix network stall under load") added double-check to test whether the available buffer size can satisfy the request or not, in case the guest has added some buffers to the avail ring simultaneously after the first check. It will be lucky if the availab

[PATCH] vhsot-user: Do not wait for replay for not sent VHOST_USER_SET_LOG_BASE

From: BillXiang Hello, there are some code that must be added to my last commit 7c211eb078c42146ee9a441cc028fbc4c378ef5a of 'Skip unnecessary duplicated VHOST_USER_SET_LOG_BASE requests'. We can not wait for replies from those duplicated VHOST_USER_SET_LOG_BASE that not really sent. Signed-off-

Re: [PATCH v2 20/40] gitlab: don't bother with KVM for TCI builds

On 05/07/2024 23.44, Philippe Mathieu-Daudé wrote: On 5/7/24 18:49, Thomas Huth wrote: On 05/07/2024 18.34, Philippe Mathieu-Daudé wrote: On 5/7/24 10:40, Alex Bennée wrote: In fact any other accelerator would be pointless as the point is to exercise the TCI accelerator anyway. Signed-off-by:

Re: [PATCH V13 2/8] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file

Hi Igor, On 06/07/2024 13:20, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:43 +0100 Salil Mehta wrote: CPU ctrl-dev MMIO region length could be used in ACPI GED and various other architecture specific places. Move ACPI_CPU_HOTPLUG_REG_LEN macro to more appropriate common header file. Signed

Re: [PATCH V13 3/8] hw/acpi: Update ACPI GED framework to support vCPU Hotplug

On 06/07/2024 13:46, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:44 +0100 Salil Mehta wrote: ACPI GED (as described in the ACPI 6.4 spec) uses an interrupt listed in the _CRS object of GED to intimate OSPM about an event. Later then demultiplexes the notified event by evaluating ACPI _EVT

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Mon, Jul 8, 2024 at 11:21 AM Jason Wang wrote: > On Sat, Jul 6, 2024 at 4:30 AM Hyman Huang wrote: > > > > Unexpected work by certain Windows guests equipped with the e1000 > > interface can cause the network to go down and never come back up > > again unless the guest's interface is reset. >

Re: [PATCH V13 4/8] hw/acpi: Update GED _EVT method AML with CPU scan

Hi Igor, On 06/07/2024 14:28, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:45 +0100 Salil Mehta wrote: OSPM evaluates _EVT method to map the event. The CPU hotplug event eventually results in start of the CPU scan. Scan figures out the CPU and the kind of event(plug/unplug) and notifies it b

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Sat, Jul 6, 2024 at 4:30 AM Hyman Huang wrote: > Unexpected work by certain Windows guests equipped with the e1000 > interface can cause the network to go down and never come back up > again unless the guest's interface is reset. > > To reproduce the failure: > 1. Set up two guests with a Wind

Re: [PATCH V13 5/8] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change

On 06/07/2024 14:35, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:46 +0100 Salil Mehta wrote: CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port based and existing CPUs AML code assumes _CRS objects would evaluate to a system resource which describes IO Port addres

Re: [PATCH V13 6/8] physmem: Add helper function to destroy CPU AddressSpace

On 06/07/2024 14:37, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:47 +0100 Salil Mehta wrote: Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also involves destruction of the CPU AddressSpace. Add common function to help destroy the CPU AddressSpace. Signed-off-by: Salil

Re: [PATCH V13 7/8] gdbstub: Add helper function to unregister GDB register space

Hi Igor, On 06/07/2024 14:41, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:48 +0100 Salil Mehta wrote: Add common function to help unregister the GDB register space. This shall be done in context to the CPU unrealization. Note: These are common functions exported to arch specific code. For

Re: [PATCH V13 8/8] docs/specs/acpi_hw_reduced_hotplug: Add the CPU Hotplug Event Bit

On 06/07/2024 14:45, Igor Mammedov wrote: On Fri, 7 Jun 2024 12:56:49 +0100 Salil Mehta wrote: GED interface is used by many hotplug events like memory hotplug, NVDIMM hotplug and non-hotplug events like system power down event. Each of these can be selected using a bit in the 32 bit GED IO in

Re: [PATCH v2 2/2] target/loongarch: Fix cpu_reset set wrong CSR_CRMD

On 2024/7/5 上午10:18, Song Gao wrote: After cpu_reset, DATF in CSR_CRMD is 0, DATM is 0. See the manual[1] 6.4. [1]: https://github.com/loongson/LoongArch-Documentation/releases/download/2023.04.20/LoongArch-Vol1-v1.10-EN.pdf Signed-off-by: Song Gao --- target/loongarch/cpu.c | 6 +++--

Re: [PATCH v2 1/2] target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values

On 2024/7/5 上午10:18, Song Gao wrote: We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1 and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the default values of the physical machine. Signed-off-by: Song Gao --- v2: - Add a new patch fix set CSR_CRMD wrong value; - S

[PATCH v3 1/9] spapr: Free stdout path

This fixes LeakSanitizer warnings. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- hw/ppc/spapr_vof.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c index 09f29be0b9de..c02eaacfed0

[PATCH v3 0/9] Fix check-qtest-ppc64 sanitizer errors

Based-on: <3ad18bc590ef28e1526e8053568086b453e7ffde.1718211878.git.quic_mathb...@quicinc.com> ("[PATCH] cpu: fix memleak of 'halt_cond' and 'thread'") I saw various sanitizer errors when running check-qtest-ppc64. While I could just turn off sanitizers, I decided to tackle them this time. Unfort

[PATCH v3 6/9] memory: Clarify that owner may be missing

A memory region may not have an owner, and memory_region_ref() and memory_region_unref() do nothing for such. Signed-off-by: Akihiko Odaki --- include/exec/memory.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index e1bd2

[PATCH v3 3/9] migration: Free removed SaveStateEntry

This fixes LeakSanitizer warnings. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Xu Reviewed-by: Michael S. Tsirkin --- migration/savevm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/migration/savevm.c b/migration/savevm.c index deb57833f8a8..85958d7b09cd 100644 --- a/migration/sav

[PATCH v3 5/9] memory: Refer to docs/devel/memory.rst for "owner"

memory_region_ref() and memory_region_unref() used to have their own descriptions of "owner", but they are somewhat out-of-date and misleading. In particular, they say "whenever memory regions are accessed outside the BQL, they need to be preserved against hot-unplug", but protecting against hot-u

[PATCH v3 4/9] memory: Do not refer to "memory region's reference count"

Now MemoryRegions do have their own reference counts, but they will not be used when their owners are not themselves. However, the documentation of memory_region_ref() says it adds "1 to a memory region's reference count", which is confusing. Avoid referring to "memory region's reference count" and

[PATCH v3 9/9] tests/qtest: Delete previous boot file

A test run may create boot files several times. Delete the previous boot file before creating a new one. Signed-off-by: Akihiko Odaki Reviewed-by: Michael S. Tsirkin --- tests/qtest/migration-test.c | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/tests/qt

[PATCH v3 8/9] memory: Do not create circular reference with subregion

memory_region_update_container_subregions() calls memory_region_ref() on behalf of the owner of the container. memory_region_ref() must not be called if the owner of the container also owns the subregion. Signed-off-by: Akihiko Odaki Reviewed-by: Michael S. Tsirkin --- system/memory.c | 11

[PATCH v3 7/9] memory: Clarify owner must not call memory_region_ref()

Signed-off-by: Akihiko Odaki --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 847c84c86db0..32bb430acdc4 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1246,6 +1246,7 @@ void memory_region_init(Me

[PATCH v3 2/9] ppc/vof: Fix unaligned FDT property access

FDT properties are aligned by 4 bytes, not 8 bytes. Signed-off-by: Akihiko Odaki Reviewed-by: Peter Maydell Reviewed-by: Michael S. Tsirkin --- hw/ppc/vof.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c index e3b430a81f4f..b5b6514d79fc 100644 -