Re: [PATCH 27/43] target/ppc/mmu_common.c: Remove mmu_ctx_t

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Completely get rid of mmu_ctx_t after converting the remaining > functions to pass raddr and prot without the context struct. Reviewed-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 25 +++

Re: [PATCH 26/43] target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb()

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Pass raddr and prot in function parameters instead Reviewed-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 17 + > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --gi

Re: [PATCH 28/43] target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr()

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > This function is used only once and does not add more clarity than > doing it inline. > > Signed-off-by: BALATON Zoltan Ah, not really sure I agree. Yes I suppose in this case because it has that comment. But you could instead remove th

Re: [PATCH 29/43] target/ppc/mmu-hash32.c: Move get_pteg_offset32() to the header

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > This function is a simple shared function, move it to other similar > static inline functions in the header. Reviewed-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu-hash32.c | 7 --- > target/ppc/mmu

Re: [PATCH 30/43] target/ppc: Unexport some functions from mmu-book3s-v3.h

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > The ppc_hash64_hpt_base() and ppc_hash64_hpt_mask() functions are > mostly used by mmu-hash64.c only but there is one call to > ppc_hash64_hpt_mask() in hw/ppc/spapr_vhyp_mmu.c.in a helper function > that can be moved to mmu-hash64.c whic

Re: [PATCH 32/43] target/ppc: Remove includes from mmu-book3s-v3.h

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Drop includes from header that is not needed by the header itself and > only include them from C files that really need it. Acked-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu-book3s-v3.h | 3 --- > tar

Re: [PATCH 31/43] target/ppc/mmu-radix64: Remove externally unused parts from header

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Move the parts not needed outside of mmu-radix64.c from the header to > the C file to leave only parts in the header that need to be exported. > Also drop unneded include of this header. > > Signed-off-by: BALATON Zoltan Acked-by: Nicho

Re: [PATCH 33/43] target/ppc: Remove single use static inline function

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > The ger_pack_masks() function is only used once and the inverse of > this operation is already inlined so it can be inlined too in the only > caller and removed from the header. Is this needed for later patches? I might prefer to keep it

Re: [PATCH 35/43] target/ppc/mmu-hash32.c: Change parameter type of ppc_hash32_bat_lookup()

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > This function takes PowerPCCPU but only needs the env from it. Change > its parameter to CPUPPCState *env. > Reviewed-by: Nicholas Piggin > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu-hash32.c | 5 ++--- > 1 file changed, 2

Re: [PATCH 36/43] target/ppc/mmu-hash32: Remove some static inlines from header

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Two of these are not used anywhere and the other two are used only > once and can be inlined and removed from the header. I'd prefer to put these in the .c file. Probably calculating the base once would generate marginally better code si

Re: [PATCH 37/43] target/ppc/mmu-hash32.c: Return and use pte address instead of base + offset

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > Change ppc_hash32_pteg_search() to return pte address instead of an > offset to avoid needing to get the base and add offset to it when we > already have the address we need. I think this looks good, but would need small rebase if the pr

Re: [PATCH 39/43] target/ppc: Change parameter type of some inline functions

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > These functions take PowerPCCPU but only need the env from it. Change > their parameter to CPUPPCState *env. I suppose that's okay. Probably generates a little better code. Acked-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan

Re: [PATCH 40/43] target/ppc: Change parameter type of ppc64_v3_radix()

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > This function takes PowerPCCPU but only needs the env from it. Change > its parameter to CPUPPCState *env. Acked-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > hw/ppc/spapr_rtas.c| 2 +- > target/ppc/mmu-book3s

Re: [PATCH v3] virtio: Implement Virtio Backend for SD/MMC in QEMU

On Wed, 3 Jul 2024, Michael S. Tsirkin wrote: > On Wed, Jul 03, 2024 at 10:55:17PM +0300, Mikhail Krasheninnikov wrote: > > > > Hello, Alex! > > > > No, there's no patch to the VirtIO specification yet. This is > > proof-of-concept solution since I'm not sure that I did everything > > correc

[PATCH v3] memory tier: consolidate the initialization of memory tiers

The current memory tier initialization process is distributed across two different functions, memory_tier_init() and memory_tier_late_init(). This design is hard to maintain. Thus, this patch is proposed to reduce the possible code paths by consolidating different initialization patches into one.

Re: [PATCH 41/43] target/ppc: Change MMU xlate functions to take CPUState

On Mon May 27, 2024 at 9:13 AM AEST, BALATON Zoltan wrote: > The callers of xlate functions get CPUState which is then cast to > PowerPCCPU that is then cast back to CPUState by most xlate functions. > Avoid this back and forth casting by passing the existing CPUState to > xlate functions and let t

Re: [PATCH V13 1/8] accel/kvm: Extract common KVM vCPU {creation,parking} code

Looks like there is a bit of noise around this recently. Do we think the hotplug patches can get over the line this time? If not, perhaps we work with Salil to get this patch 1 upstream at least. Thanks, Nick On Tue Jun 25, 2024 at 3:08 PM AEST, Harsh Prateek Bora wrote: > +qemu-devel, qemu-ppc

Re: [PATCH v2 1/7] target/ppc: use locally stored msr and avoid indirect access

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > hreg_compute_hflags_value already stores msr locally to be used in most > of the logic in the routine however some instances are still using > env->msr which is unnecessary. Use locally stored value as available. > > Signed-off-by: Ha

Re: [PATCH v2 2/7] target/ppc: optimize hreg_compute_pmu_hflags_value

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple > conditions to avoid multiple indirect accesses. > > Signed-off-by: Harsh Prateek Bora Compiler might cache it in a reg, but anyway I like it. Reviewed-by: Ni

Re: [PATCH v2 3/7] target/ppc: optimize hreg_compute_pmu_hflags_value

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > The second if-condition can be true only if the first one above is true. > Enclose the latter into the former to avoid un-necessary check if first > condition fails. > > Signed-off-by: Harsh Prateek Bora > Reviewed-by: BALATON Zoltan

Re: [PATCH v3] virtio: Implement Virtio Backend for SD/MMC in QEMU

On Thu, Jul 04, 2024 at 10:25:53AM +0300, Mikhail Krasheninnikov wrote: > > On Wed, 3 Jul 2024, Michael S. Tsirkin wrote: > > > On Wed, Jul 03, 2024 at 10:55:17PM +0300, Mikhail Krasheninnikov wrote: > > > > > > Hello, Alex! > > > > > > No, there's no patch to the VirtIO specification yet. This

Re: [PATCH v2 4/7] target/ppc: optimize p9 exception handling routines

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > Currently, p9 exception handling has multiple if-condition checks where > it does an indirect access to pending_interrupts via env. Pass the > value during entry to avoid multiple indirect accesses. Does code change? I don't mind, wo

Re: [PATCH v2 1/7] target/ppc: use locally stored msr and avoid indirect access

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > hreg_compute_hflags_value already stores msr locally to be used in most > of the logic in the routine however some instances are still using > env->msr which is unnecessary. Use locally stored value as available. BTW hreg_store_msr u

Re: [PATCH v2 5/7] target/ppc: optimize p9 exception handling routines for lpcr

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > Like pending_interrupts, env->spr[SPR_LPCR] is being used at multiple > places across p9 exception handlers. Pass the value during entry and > avoid multiple indirect accesses. Ditto for this (does it help code, other CPU functions s

Re: [PATCH] net: update netdev stream/dgram man page

Hi Marc-André, thank you for your comments, you're right I should not mix TCP/UDP and unix socket. I'm going to fix that. Thanks, Laurent On 02/07/2024 09:39, Marc-André Lureau wrote: Hi On Wed, Jun 26, 2024 at 7:53 PM Laurent Vivier > wrote: Add the descri

Re: [PATCH v2 7/7] target/ppc: redue code duplication across Power9/10 init code

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: > Power9/10 initialization code consists of a lot of logical OR of > various flag bits as supported by respective Power platform during its > initialization, most of which is duplicated and only selected bits are > added or removed as n

Re: [PATCH v3] memory tier: consolidate the initialization of memory tiers

"Ho-Ren (Jack) Chuang" writes: > The current memory tier initialization process is distributed across > two different functions, memory_tier_init() and memory_tier_late_init(). > This design is hard to maintain. Thus, this patch is proposed to reduce > the possible code paths by consolidating dif

Re: [PULL v3 58/85] hw/i386/fw_cfg: Add etc/e820 to fw_cfg late

On Wed, 2024-07-03 at 18:48 -0400, Michael S. Tsirkin wrote: > From: David Woodhouse Oops, that was supposed to be From: David Woodhouse Not the end of the world if it's too late to change it. smime.p7s Description: S/MIME cryptographic signature

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

On 2024/7/4 12:36, CLEMENT MATHIEU--DRIF wrote: On 03/07/2024 14:32, Yi Liu wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Hi, thanks for your review! very efficient! Hi CMD, I've went th

[PATCH] MAINTAINERS: add Stefano Garzarella as vhost/vhost-user reviewer

I have recently been working on supporting vhost-user on any POSIX, so I want to help maintain it. Cc: Michael S. Tsirkin Signed-off-by: Stefano Garzarella --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6725913c8b..47493f19d9 100644 --- a/MAI

Re: [PATCH v3] virtio: Implement Virtio Backend for SD/MMC in QEMU

> 4 июля 2024 г., в 10:38, Michael S. Tsirkin написал(а): > > On Thu, Jul 04, 2024 at 10:25:53AM +0300, Mikhail Krasheninnikov wrote: >> >> On Wed, 3 Jul 2024, Michael S. Tsirkin wrote: >> >>> On Wed, Jul 03, 2024 at 10:55:17PM +0300, Mikhail Krasheninnikov wrote: Hello, Alex!

[PATCH v3 0/8] support AST2700 network

change from v1: - ftgmac100 - fix coding style - support 64 bits dma dram address for AST2700 change from v2: - ftgmac100: update memory region size to 0x200. - ftgmac100: introduce a new class(ftgmac100_high), class attribute and memop handlers, for FTGMAC100_*_HIGH regs read/write. - aspee

[PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq

According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2". Besides, users are able to utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get the QE bit status. To suppo

[PATCH v3 3/8] hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits

ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register High(0x184)" and "Receive Ring Base Addr

[PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB

According to the datasheet of ASPEED SOCs, one MAC controller owns 128KB of register space for AST2500. However, one MAC controller only owns 64KB of register space for AST2600 and AST2700. It set the memory region size 128KB and it occupied another controllers Address Spaces. Update one MAC contr

[PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits

Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address of descriptor manager. Therefore, chang

[PATCH v3 7/8] machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700

Update test case to test ASPEED OpenBMC SDK v09.02 for AST2700. ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c. It is required to use ASPEED OpenBMC SDK since v09.02 for AST2700 QEMU network testing. A test image is downloaded from the ASPEED Forked OpenBMC GitHub release repository :

[PATCH v3 8/8] machine_aspeed.py: update to test network for AST2700

Update test case to test network connection via SSH. Test command: ``` cd build pyvenv/bin/avocado run ../qemu/tests/avocado/machine_aspeed.py:AST2x00MachineSDK.test_aarch64_ast2700_evb_sdk_v09_02 ``` Signed-off-by: Jamin Lin --- tests/avocado/machine_aspeed.py | 6 -- 1 file changed, 4 in

[PATCH v3 4/8] hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits

ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "TXDES 2" and "RXDES 2" to save the high part physical address of packet buffer. Ex: TX packet buffer address [34:0] The "TXDES 2" bits [18:16] which correspo

[PATCH v3 5/8] aspeed/soc: set dma64 property for AST2700 ftgmac100

ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. Set dma64 property for ftgmac100 model to support 64bits dram address DMA. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 3 +++ 1 file changed, 3 insertio

[PATCH 1/4] accel/kvm/kvm-all: Fix superfluous trailing semicolon

Signed-off-by: Zhao Liu --- accel/kvm/kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 2b4ab896794b..64bf47a03300 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3878,7 +3878,7 @@ static StatsList *add_kvm

[PATCH 2/4] hw/i386/x86: Fix superfluous trailing semicolon

Signed-off-by: Zhao Liu --- hw/i386/x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index a4aa8e081098..01fc5e656272 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -242,7 +242,7 @@ static void x86_machine_get_pit(Object *obj, Visitor *v,

[PATCH 4/4] target/hexagon/imported/mmvec: Fix superfluous trailing semicolon

Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/ ext.idef. Cc: Brian Cain Signed-off-by: Zhao Liu --- target/hexagon/imported/mmvec/ext.idef | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/impor

[PATCH 3/4] util/oslib-posix: Fix superfluous trailing semicolon

Signed-off-by: Zhao Liu --- util/oslib-posix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/oslib-posix.c b/util/oslib-posix.c index e76441695bdc..b090fe0eed0d 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -263,7 +263,7 @@ int qemu_socketpair(int domain,

[PATCH 0/4] trivial: Fix superfluous trailing semicolon

Hi, I checked the files in QEMU to fix these few errors about "superfluous trailing semicolon" to honor the requirement in checkpatch.pl. Thanks and Best Regards, Zhao --- Zhao Liu (4): accel/kvm/kvm-all: Fix superfluous trailing semicolon hw/i386/x86: Fix superfluous trailing semicolon uti

Re: [PATCH] i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT

On Thu, Jul 04, 2024 at 08:51:05AM +0200, Paolo Bonzini wrote: > On Thu, Jul 4, 2024 at 2:01 AM Michael Roth wrote: > > Currently if the 'legacy-vm-type' property of the sev-guest object is > > left unset, QEMU will attempt to use the newer KVM_SEV_INIT2 kernel > > interface in conjunction with th

Re: [PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB

On 7/4/24 10:29 AM, Jamin Lin wrote: According to the datasheet of ASPEED SOCs, one MAC controller owns 128KB of register space for AST2500. However, one MAC controller only owns 64KB of register space for AST2600 and AST2700. It set the memory region size 128KB and it occupied another controller

Re: [PATCH v4 30/31] i386/kvm: Add KVM_EXIT_HYPERCALL handling for KVM_HC_MAP_GPA_RANGE

On 5/30/2024 7:16 PM, Pankaj Gupta wrote: [...] +/* + * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE + * to service guest-initiated memory attribute update requests so that + * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be + * backed by the priv

Re: [PATCH v3 3/8] hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits

On 7/4/24 10:29 AM, Jamin Lin wrote: ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register H

Re: [PATCH v3 5/8] aspeed/soc: set dma64 property for AST2700 ftgmac100

On 7/4/24 10:29 AM, Jamin Lin wrote: ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. Set dma64 property for ftgmac100 model to support 64bits dram address DMA. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le

Re: [PATCH v3 7/8] machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700

On 7/4/24 10:29 AM, Jamin Lin wrote: Update test case to test ASPEED OpenBMC SDK v09.02 for AST2700. ASPEED fixed TX mask issue from linux/drivers/ftgmac100.c. It is required to use ASPEED OpenBMC SDK since v09.02 for AST2700 QEMU network testing. A test image is downloaded from the ASPEED Fork

Re: [PATCH v3 8/8] machine_aspeed.py: update to test network for AST2700

On 7/4/24 10:29 AM, Jamin Lin wrote: Update test case to test network connection via SSH. Test command: ``` cd build pyvenv/bin/avocado run ../qemu/tests/avocado/machine_aspeed.py:AST2x00MachineSDK.test_aarch64_ast2700_evb_sdk_v09_02 ``` Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goat

Re: [PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits

On 7/4/24 10:29 AM, Jamin Lin wrote: Update TX and RX ring base address data type to uint64_t for 64 bits dram address DMA support. Both "Normal Priority Transmit Ring Base Address Register(0x20)" and "Receive Ring Base Address Register (0x24)" are used for saving the low part physical address o

[PATCH] hw/cxl/cxl-host: Fix guest crash when getting cxl-fmw property

From: Zhao Liu Guest crashes (Segmentation fault) when getting cxl-fmw property via qmp: (QEMU) qom-get path=machine property=cxl-fmw This issue is caused by accessing wrong callback (opaque) type in machine_get_cfmw(). cxl_machine_init() sets the callback as `CXLState *` type but machine_get_

Re: [PATCH v3 4/8] hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits

On 7/4/24 10:29 AM, Jamin Lin wrote: ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "TXDES 2" and "RXDES 2" to save the high part physical address of packet buffer. Ex: TX packet buffer address [34:0] Th

Re: [PATCH] i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT

On Thu, Jul 4, 2024 at 10:42 AM Daniel P. Berrangé wrote: > > On Thu, Jul 04, 2024 at 08:51:05AM +0200, Paolo Bonzini wrote: > > On Thu, Jul 4, 2024 at 2:01 AM Michael Roth wrote: > > > Currently if the 'legacy-vm-type' property of the sev-guest object is > > > left unset, QEMU will attempt to us

Re: [PATCH] hw/intc: sifive_plic: Fix heap-buffer-overflow in SiFive PLIC read operation

On Wed, 3 Jul 2024 at 22:32, Zheyu Ma wrote: > > The sifive_plic_read function in hw/intc/sifive_plic.c had a potential > heap-buffer-overflow issue when reading from the pending_base region. > This occurred because the code did not check if the calculated word index > was within valid bounds befo

Re: [PATCH 1/4] accel/kvm/kvm-all: Fix superfluous trailing semicolon

On Thu, 4 Jul 2024 at 09:32, Zhao Liu wrote: > > Signed-off-by: Zhao Liu > --- > accel/kvm/kvm-all.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c > index 2b4ab896794b..64bf47a03300 100644 > --- a/accel/kvm/kvm-all.c > +++ b/ac

Re: [PATCH 3/4] util/oslib-posix: Fix superfluous trailing semicolon

On Thu, 4 Jul 2024 at 09:33, Zhao Liu wrote: > > Signed-off-by: Zhao Liu > --- > util/oslib-posix.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/util/oslib-posix.c b/util/oslib-posix.c > index e76441695bdc..b090fe0eed0d 100644 > --- a/util/oslib-posix.c > +++ b/util/o

Re: [PATCH 4/4] target/hexagon/imported/mmvec: Fix superfluous trailing semicolon

On Thu, 4 Jul 2024 at 09:33, Zhao Liu wrote: > > Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/ > ext.idef. > > Cc: Brian Cain > Signed-off-by: Zhao Liu > --- > target/hexagon/imported/mmvec/ext.idef | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --gi

Re: [PATCH 2/4] hw/i386/x86: Fix superfluous trailing semicolon

On Thu, 4 Jul 2024 at 09:33, Zhao Liu wrote: > > Signed-off-by: Zhao Liu > --- > hw/i386/x86.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/i386/x86.c b/hw/i386/x86.c > index a4aa8e081098..01fc5e656272 100644 > --- a/hw/i386/x86.c > +++ b/hw/i386/x86.c > @@ -242,7

Re: [PATCH] i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT

On Thu, Jul 04, 2024 at 11:31:16AM +0200, Paolo Bonzini wrote: > On Thu, Jul 4, 2024 at 10:42 AM Daniel P. Berrangé > wrote: > > > > On Thu, Jul 04, 2024 at 08:51:05AM +0200, Paolo Bonzini wrote: > > > On Thu, Jul 4, 2024 at 2:01 AM Michael Roth wrote: > > > > Currently if the 'legacy-vm-type' p

Re: [PATCH 1/4] accel/kvm/kvm-all: Fix superfluous trailing semicolon

Zhao Liu writes: > Signed-off-by: Zhao Liu > --- > accel/kvm/kvm-all.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c > index 2b4ab896794b..64bf47a03300 100644 > --- a/accel/kvm/kvm-all.c > +++ b/accel/kvm/kvm-all.c > @@ -3878,

Re: [PATCH 4/4] target/hexagon/imported/mmvec: Fix superfluous trailing semicolon

Zhao Liu writes: > Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/ > ext.idef. > > Cc: Brian Cain > Signed-off-by: Zhao Liu Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 3/4] util/oslib-posix: Fix superfluous trailing semicolon

Zhao Liu writes: > Signed-off-by: Zhao Liu Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH] MAINTAINERS: add Stefano Garzarella as vhost/vhost-user reviewer

Stefano Garzarella writes: > I have recently been working on supporting vhost-user on any POSIX, > so I want to help maintain it. > > Cc: Michael S. Tsirkin > Signed-off-by: Stefano Garzarella Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH] i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT

On Thu, Jul 4, 2024 at 11:39 AM Daniel P. Berrangé wrote: > > The debug_swap parameter simply could not be enabled in the old API > > without breaking measurements. The new API *is the fix* to allow using > > it (though QEMU doesn't have the option plumbed in yet). There is no > > extensibility. >

Re: [PULL v3 58/85] hw/i386/fw_cfg: Add etc/e820 to fw_cfg late

David Woodhouse writes: > On Wed, 2024-07-03 at 18:48 -0400, Michael S. Tsirkin wrote: >> From: David Woodhouse > > Oops, that was supposed to be > > From: David Woodhouse > > Not the end of the world if it's too late to change it. If attribution matters we do have .mailmap and the gitdm metad

[PULL 01/16] meson: move shared_module() calls where modules are already walked

Signed-off-by: Paolo Bonzini --- meson.build | 34 +++--- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/meson.build b/meson.build index 54e6b09f4fb..8909f8c87d9 100644 --- a/meson.build +++ b/meson.build @@ -3602,6 +3602,7 @@ modinfo_files = [] blo

[PULL 06/16] meson: Drop the .fa library suffix

The non-standard .fa library suffix breaks the link source de-duplication done by Meson so drop it. The lack of link source de-duplication causes AddressSanitizer to complain ODR violations, and makes GNU ld abort when combined with clang's LTO. Fortunately, the non-standard suffix is not necessa

[PULL 03/16] meson: merge plugin_ldflags into emulator_link_args

These serve the same purpose, except plugin_ldflags ends up in the linker command line in a more roundabout way (through specific_ss). Simplify. Signed-off-by: Paolo Bonzini --- plugins/meson.build | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/plugins/meson.build b/

[PULL 11/16] i386/sev: Fix error message in sev_get_capabilities()

From: Michal Privoznik When a custom path is provided to sev-guest object and opening the path fails an error message is reported. But the error message still mentions DEFAULT_SEV_DEVICE ("/dev/sev") instead of the custom path. Fixes: 16dcf200dc951c1cde3e5b442457db5f690b8cf0 Signed-off-by: Micha

[PULL 12/16] i386/sev: Fallback to the default SEV device if none provided in sev_get_capabilities()

From: Michal Privoznik When management tools (e.g. libvirt) query QEMU capabilities, they start QEMU with a minimalistic configuration and issue various commands on monitor. One of the command issued is/might be "query-sev-capabilities" to learn values like cbitpos or reduced-phys-bits. But as of

[PULL 05/16] Revert "meson: Propagate gnutls dependency"

From: Akihiko Odaki This reverts commit 3eacf70bb5a83e4775ad8003cbca63a40f70c8c2. It was only needed because of duplicate objects caused by declare_dependency(link_whole: ...), and can be dropped now that meson.build specifies objects and dependencies separately for the internal dependencies. S

[PULL 02/16] meson: move block.syms dependency out of libblock

In order to define libqemuutil symbols that are requested by block modules, QEMU currently uses a combination of the "link_depends" argument of libraries (which is propagated into dependencies, but not available in dependencies) and the "link_args" argument of declare_dependency() (which _is_ avail

[PULL 04/16] meson: Pass objects and dependencies to declare_dependency()

From: Akihiko Odaki We used to request declare_dependency() to link_whole static libraries. If a static library is a thin archive, GNU ld keeps all object files referenced by the archive open, and sometimes exceeds the open file limit. Another problem with link_whole is that suboptimal handling

[PULL 16/16] target/i386/SEV: implement mask_cpuid_features

Drop features that are listed as "BitMask" in the PPR and currently not supported by AMD processors. The only ones that may become useful in the future are TSC deadline timer and x2APIC, everything else is not needed for SEV-SNP guests (e.g. VIRT_SSBD) or would require processor support (e.g. TSC_

[PULL 10/16] target/i386: do not include undefined bits in the AMD topoext leaf

Commit d7c72735f61 ("target/i386: Add new EPYC CPU versions with updated cache_info", 2023-05-08) ensured that AMD-defined CPU models did not have the 'complex_indexing' bit set, but left it set in "-cpu host" which uses the default ("legacy") cache information. Reimplement that commit using a CPU

[PULL 08/16] target/i386: drop AMD machine check bits from Intel CPUID

The recent addition of the SUCCOR bit to kvm_arch_get_supported_cpuid() causes the bit to be visible when "-cpu host" VMs are started on Intel processors. While this should in principle be harmless, it's not tidy and we don't even know for sure that it doesn't cause any guest OS to take unexpected

[PULL 14/16] char-stdio: Restore blocking mode of stdout on exit

From: Maxim Mikityanskiy qemu_chr_open_fd() sets stdout into non-blocking mode. Restore the old fd flags on exit to avoid breaking unsuspecting applications that run on the same terminal after qemu and don't expect to get EAGAIN. While at at, also ensure term_exit is called once (at the moment i

[PULL 13/16] target/i386: add avx-vnni-int16 feature

AVX-VNNI-INT16 (CPUID[EAX=7,ECX=1).EDX[10]) is supported by Clearwater Forest processor, add it to QEMU as it does not need any specific enablement. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i

[PULL 07/16] target/i386: pass X86CPU to x86_cpu_get_supported_feature_word

This allows modifying the bits in "-cpu max"/"-cpu host" depending on the guest CPU vendor (which, at least by default, is the host vendor in the case of KVM). For example, machine check architecture differs between Intel and AMD, and bits from AMD should be dropped when configuring the guest for

[PULL 09/16] target/i386: SEV: fix formatting of CPUID mismatch message

Fixes: 70943ad8e4d ("i386/sev: Add support for SNP CPUID validation", 2024-06-05) Signed-off-by: Paolo Bonzini --- target/i386/sev.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/sev.c b/target/i386/sev.c index 3ab8b3c28b7..2a0f94d390d 100644 --- a/target/

[PULL 00/16] meson, i386 changes for 2024-07-04

The following changes since commit 1a2d52c7fcaeaaf4f2fe8d4d5183dccaeab67768: Merge tag 'pull-request-2024-07-02' of https://gitlab.com/thuth/qemu into staging (2024-07-02 15:49:08 -0700) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you t

[PULL 15/16] target/i386: add support for masking CPUID features in confidential guests

Some CPUID features may be provided by KVM for some guests, independent of processor support, for example TSC deadline or TSC adjust. If these are not supported by the confidential computing firmware, however, the guest will fail to start. Add support for removing unsupported features from "-cpu

Re: [PATCH 0/3] plugins: Few debugging cleanups

Philippe Mathieu-Daudé writes: > - Assert cpu_index is assigned in INIT/EXIT hooks > - Free cpu->plugin_state > - Restrict qemu_plugin_vcpu_init__async() to plugins/ > > Philippe Mathieu-Daudé (3): > plugins: Ensure vCPU index is assigned in init/exit hooks > plugins: Free CPUPluginState befo

Re: [PATCH v7] virtio-net: Fix network stall at the host side waiting for kick

Hi, Michael > My suggestion: > > > change virtqueue_get_avail_bytes to return the shadow > in an opaque unsigned value. > > > add virtqueue_poll that gets this opaque and tells us whether any new > buffers became available in the queue since that value> > was returned. > accordingly, virtio

Re: [PATCH v1 1/2] physmem: Bail out qemu_ram_block_from_host() for invalid ram addrs

"Edgar E. Iglesias" writes: > From: "Edgar E. Iglesias" > > Bail out in qemu_ram_block_from_host() when > xen_ram_addr_from_mapcache() does not find an existing > mapping. > > Signed-off-by: Edgar E. Iglesias > --- > system/physmem.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a

Re: [PATCH 2/2] system/vl.c: parse all -accel options

Paolo Bonzini writes: > On Mon, Jul 1, 2024 at 4:34 PM Philippe Mathieu-Daudé > wrote: >> Reviewed-by: Philippe Mathieu-Daudé > > In principle, a Reviewed-by tag is just stating that you don't know of > any issues that would prevent the patch being included. However, as a > frequent participan

Re: [PATCH] hw/loongarch/boot.c: fix out-of-bound reading

在 2024/6/28 下午8:39, Dmitry Frolov 写道: memcpy() is trying to READ 512 bytes from memory, pointed by info->kernel_cmdline, which was (presumable) allocated by g_strdup(""); Found with ASAN, making check with enabled sanitizers. Signed-off-by: Dmitry Frolov --- hw/loongarch/boot.c | 2 +- 1 fil

Re: [PATCH] spapr: Migrate ail-mode-3 spapr cap

On Mon Jul 1, 2024 at 5:10 PM AEST, Michael Tokarev wrote: > 06.06.2024 14:26, Michael Tokarev wrote: > > 06.05.2024 14:56, Nicholas Piggin wrote: > >> This cap did not add the migration code when it was introduced. This > >> results in migration failure when changing the default using the > >> com

[PATCH] i386/cpu: Drop the check of phys_bits in host_cpu_realizefn()

The check of cpu->phys_bits to be in range between [32, TARGET_PHYS_ADDR_SPACE_BITS] in host_cpu_realizefn() is duplicated with check in x86_cpu_realizefn(). Since the ckeck in x86_cpu_realizefn() is called later and can cover all teh x86 case. Remove the one in host_cpu_realizefn(). Signed-off-b

Re: [PULL 02/12] tests/qtest/migration-test: enable on s390x with TCG

On Tue Jul 2, 2024 at 8:33 PM AEST, Thomas Huth wrote: > From: Nicholas Piggin > > s390x with TCG is more stable now. Enable it. Ah, you did a more complete version of my flic fix that migrates all the state. I didn't see that go by but yeah I suspect that was probably the correct thing to do. Th

Re: [PATCH v7] virtio-net: Fix network stall at the host side waiting for kick

On Thu, Jul 04, 2024 at 10:20:15AM +, Yang Dongshan wrote: > Hi, Michael > > > My suggestion: > > > > > > change virtqueue_get_avail_bytes to return the shadow > > in an opaque unsigned value. > > > > > > add virtqueue_poll that gets this opaque and tells us whether any new > > buffers bec

RE: [PATCH RFC V3 13/29] arm/virt: Make ARM vCPU *present* status ACPI *persistent*

HI Nick, Thanks for taking time to review. Please find my replies inline. > From: Nicholas Piggin > Sent: Thursday, July 4, 2024 3:49 AM > To: Salil Mehta ; qemu-devel@nongnu.org; > qemu-...@nongnu.org; m...@redhat.com > > On Fri Jun 14, 2024 at 9:36 AM AEST, Salil Mehta wrote: > > ARM a

[PATCH v2 2/4] target/i386: Add CPUID leaf 0xC000_0001 EDX definitions

Add new CPUID feature flags for various Zhaoxin PadLock extensions. These definitions will be used for Zhaoxin CPU models. Signed-off-by: EwanHai --- target/i386/cpu.h | 21 + 1 file changed, 21 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 07e8353f3

[PATCH v2 4/4] target/i386: Update CMPLegacy handling for Zhaoxin CPUs

Zhaoxin CPUs handle the CMPLegacy bit in the same way as Intel CPUs. This patch simplifies the existing logic by using the IS_XXX_CPU macro and includes checks for Zhaoxin vendor to align their behavior with Intel. Signed-off-by: EwanHai --- target/i386/cpu.c | 4 +--- 1 file changed, 1 insertio

[PATCH v2 1/4] target/i386: Add support for Zhaoxin CPU vendor identification

Zhaoxin currently uses two vendors: "Shanghai" and "Centaurhauls". It is important to note that the latter now belongs to Zhaoxin. Therefore, this patch replaces CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1. The previous CPUID_VENDOR_VIA macro was only defined but never used in QEMU, making this ch

[PATCH v2 0/4] Add support for Zhaoxin Yongfeng CPU model and other improvements

### Summary of changes EwanHai (4): target/i386: Add support for Zhaoxin CPU vendor identification target/i386: Add CPUID leaf 0xC000_0001 EDX definitions target/i386: Introduce Zhaoxin Yongfeng CPU model target/i386: Update CMPLegacy handling for Zhaoxin CPUs target/i386/cpu.c | 128 +++

[PATCH v2 3/4] target/i386: Introduce Zhaoxin Yongfeng CPU model

Introduce support for the Zhaoxin Yongfeng CPU model. The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU. This new cpu model ensure that QEMU can correctly emulate the Zhaoxin Yongfeng CPU, providing accurate functionality and performance characteristics. Signed-off-by: EwanHai --- target/

  1   2   3   4   >