在2024年7月1日七月 上午7:44，maobibo写道：
> Also this patch is problematic on LoongArch.
>
> The original patch is to search physical cpuid rather than logic cpuid.
>
> We want to make ipi module better and better, however now it comes back
> to initial state at the beginning :(
Isn't arch_id the "physic
On 01.07.24 09:55, Michael Tokarev wrote:
01.07.2024 09:54, Vladimir Sementsov-Ogievskiy wrote:
+ const char *t = "accept-ranges : bytes "; /* A lowercase template */
Note: you make parser less strict: you allow "bytes" to be uppercase (was allowed
only for accept-ranges", and you allow w
在2024年7月1日七月 上午2:35，maobibo写道：
[...]
>
> How about split loongson_ipi.c into
> loongson_ipi_base.c/loongson_ipi_loongson.c/loongson_ipi_loongarch.c,
>
> File loongson_ipi_base.c contains the common code, loongson_ipi_xxx.c
> contains arch specific. Soon we will submit irqchip in kernel functio
06.06.2024 14:26, Michael Tokarev wrote:
06.05.2024 14:56, Nicholas Piggin wrote:
This cap did not add the migration code when it was introduced. This
results in migration failure when changing the default using the
command line.
Cc: qemu-sta...@nongnu.org
Fixes: ccc5a4c5e10 ("spapr: Add SPAPR_
On 2024/7/1 下午3:01, Jiaxun Yang wrote:
在2024年7月1日七月 上午7:44，maobibo写道：
Also this patch is problematic on LoongArch.
The original patch is to search physical cpuid rather than logic cpuid.
We want to make ipi module better and better, however now it comes back
to initial state at the beginn
On 2024/7/1 下午3:08, Jiaxun Yang wrote:
在2024年7月1日七月 上午2:35，maobibo写道：
[...]
How about split loongson_ipi.c into
loongson_ipi_base.c/loongson_ipi_loongson.c/loongson_ipi_loongarch.c,
File loongson_ipi_base.c contains the common code, loongson_ipi_xxx.c
contains arch specific. Soon we will
On 2024/7/1 下午2:57, Jiaxun Yang wrote:
在2024年5月30日五月 上午7:49，Bibo Mao写道：
Loongson Binary Translation (LBT) is used to accelerate binary
translation, which contains 4 scratch registers (scr0 to scr3), x86/ARM
eflags (eflags) and x87 fpu stack pointer (ftop).
Now LBT feature is added in kvm m
> From: "项文成"
> Date: Thu, Jun 13, 2024, 14:51
> Subject: [PATCH] vhost-user: Skip unnecessary duplicated
> VHOST_USER_SET_LOG_BASE requests
> To:
> Cc: , "BillXiang"
> From: BillXiang
>
> The VHOST_USER_SET_LOG_BASE requests should be categorized into
> non-vring specific messages, and sho
Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
switched using of address_space_read_cached() to virito_lduw_phys_cached()
to access packed descriptor event.
When we used address_space_read_cached(), we needed to call
virtio_tswap16s() to handle the endianess of the field,
On Fri, Jun 28, 2024 at 03:53:09PM GMT, Peter Maydell wrote:
On Tue, 25 Jun 2024 at 08:18, Stefano Garzarella wrote:
On Mon, Jun 24, 2024 at 04:19:52PM GMT, Peter Maydell wrote:
>On Mon, 24 Jun 2024 at 16:11, Stefano Garzarella wrote:
>>
>> CCing Jason.
>>
>> On Mon, Jun 24, 2024 at 4:30 PM X
On 28/06/2024 20.01, Jared Rossi wrote:
On 6/24/24 1:55 AM, Thomas Huth wrote:
[...]
I think it should be fine, both functions are basically just a wrapper
around the write() function in sclp.c, with sclp_print() being rather dumb
while printf() is doing the usual string formatting before w
On 09:00 Fri 28 Jun , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single blo
On Mon, Jul 1, 2024 at 3:52 PM Stefano Garzarella wrote:
>
> Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
> switched using of address_space_read_cached() to virito_lduw_phys_cached()
> to access packed descriptor event.
>
> When we used address_space_read_cached(), we n
On Fri, Jun 28, 2024 at 09:00:42AM +0200, Philippe Mathieu-Daudé wrote:
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but
在2024年7月1日七月 上午8:22，maobibo写道：
> On 2024/7/1 下午3:01, Jiaxun Yang wrote:
>>
>>
>> 在2024年7月1日七月 上午7:44，maobibo写道：
>>> Also this patch is problematic on LoongArch.
>>>
>>> The original patch is to search physical cpuid rather than logic cpuid.
>>>
>>> We want to make ipi module better and better,
On Fri, 28 Jun 2024 03:04:28 +
"Gao,Shiyuan" wrote:
> > > that OS cannot get control of SHPC hotplug and hotplug device to
> > > the PCI bridge will fail when we use SHPC Native type:
> > >
> > > [3.336059] shpchp :00:03.0: Requesting control of SHPC hotplug via
> > >OSHP (\_SB_.PCI0.S
在2024年7月1日七月 上午8:32，maobibo写道：
[...]
>>>
>>> +static void loongarch_cpu_check_lbt(CPUState *cs, Error **errp)
>>> +{
>>> +CPULoongArchState *env = cpu_env(cs);
>>> +LoongArchCPU *cpu = LOONGARCH_CPU(cs);
>>> +bool kvm_supported;
>>> +
>>> +kvm_supported = kvm_feature_supported(cs
项文成 writes:
> From: BillXiang
>
> The VHOST_USER_SET_LOG_BASE requests should be categorized into
> non-vring specific messages, and should be sent only once.
> If send more than once, dpdk will munmap old log_addr which may has
> been used and cause segmentation fault.
This looks fine to me bu
The 2 first patches are fixes of
cf2647a76e ("virtio-iommu: Compute host reserved regions")
They can be taken separately of the rest.
Then the series uses the HostIOMMUDevice interface to fetch
information about the page size mask supported along the assigned
device and propagate it to the virtio-
On Wed, 26 Jun 2024 17:53:52 +
Salil Mehta wrote:
> Hi Gavin,
>
> > From: Gavin Shan
> > Sent: Wednesday, June 26, 2024 5:13 AM
> > To: Salil Mehta ; Igor Mammedov
> >
> >
> > Hi Salil and Igor,
> >
> > On 6/26/24 9:51 AM, Salil Mehta wrote:
> > > On Wed, Jun 5, 2024 at 3:03 P
Everything is now in place to use the Host IOMMU Device callbacks
to retrieve the page size mask usable with a given assigned device.
This new method brings the advantage to pass the info much earlier
to the virtual IOMMU and before the IOMMU MR gets enabled. So let's
remove the call to memory_regi
The error handle argument is not used anywhere. let's remove it.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
---
include/sysemu/host_iommu_device.h | 3 +--
hw/vfio/container.c| 2 +-
hw/vfio/iommufd.c | 2 +-
hw/virtio/v
This callback will be used to retrieve the page size mask supported
along a given Host IOMMU device.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
---
include/hw/vfio/vfio-container-base.h | 7 +++
include/sysemu/host_iommu_device.h| 8
On 2024/7/1 下午4:29, Jiaxun Yang wrote:
在2024年7月1日七月 上午8:22，maobibo写道：
On 2024/7/1 下午3:01, Jiaxun Yang wrote:
在2024年7月1日七月 上午7:44，maobibo写道：
Also this patch is problematic on LoongArch.
The original patch is to search physical cpuid rather than logic cpuid.
We want to make ipi module b
In case no IOMMUPciBus/IOMMUDevice are found we need to properly
set the error handle and return.
Fixes : Coverity CID 1549006
Signed-off-by: Eric Auger
Fixes: cf2647a76e ("virtio-iommu: Compute host reserved regions")
Reviewed-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
---
hw/virtio/vir
Introduce vfio_container_get_iova_ranges() to retrieve the usable
IOVA regions of the base container and use it in the Host IOMMU
device implementations of get_iova_ranges() callback.
We also fix a UAF bug as the list was shallow copied while
g_list_free_full() was used both on the single call sit
In 94df5b2180d6 ("virtio-iommu: Fix 64kB host page size VFIO device
assignment"), in case of bypass mode, we transiently enabled the
IOMMU MR to allow the set_page_size_mask() to be called and pass
information about the page size mask constraint of cold plugged
VFIO devices. Now we do not use the I
Retrieve the Host IOMMU Device page size mask when this latter is set.
This allows to get the information much sooner than when relying on
IOMMU MR set_page_size_mask() call, whcih happens when the IOMMU MR
gets enabled. We introduce check_page_size_mask() helper whose code
is inherited from curren
On Thu, 20 Jun 2024 17:03:16 +0100
Jonathan Cameron wrote:
> These are very similar to the recently added Generic Initiators
> but instead of representing an initiator of memory traffic they
> represent an edge point beyond which may lie either targets or
> initiators. Here we add these ports su
Richard Henderson writes:
> Fix a typo in the argument movement.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c
On Wed 12 Jun 2024 02:00:19 PM +03, Manos Pitsidianakis wrote:
Hi, thanks for the review and sorry for taking so long to reply, I was
on vacation.
>> scripts/qcow2-to-stdout.py | 330 +
>> 1 file changed, 330 insertions(+)
>> create mode 100755 scripts/qcow2-to-
On Mon, 1 Jul 2024 at 08:52, Stefano Garzarella wrote:
>
> Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
> switched using of address_space_read_cached() to virito_lduw_phys_cached()
> to access packed descriptor event.
>
> When we used address_space_read_cached(), we nee
On Mon, 1 Jul 2024 at 07:49, Marcin Juszkiewicz
wrote:
>
> W dniu 30.06.2024 o 16:37, Ard Biesheuvel pisze:
> > On Thu, 20 Jun 2024 at 12:20, Marcin Juszkiewicz
> > wrote:
> >>
> >> Update firmware to have graphics card memory fix from EDK2 commit
> >> c1d1910be6e04a8b1a73090cf2881fb698947a6e:
>
On Fri, 28 Jun 2024 15:34:58 +0100
Alex Bennée wrote:
> Alex Bennée writes:
>
> > Incorrect brace positions causes an unintended overflow on 32 bit
> > builds and shenanigans result.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
> > Suggested-by: Mark Cave-Ayland
> > Sig
On 20/06/2024 18.57, Daniel P. Berrangé wrote:
This changes the DEFINE_Q35_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice in
On 20/06/2024 18.57, Daniel P. Berrangé wrote:
This changes the DEFINE_I440FX_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice
John Snow writes:
> On Fri, Jun 28, 2024, 3:55 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Sphinx does not like sections without titles, because it wants to
>> > convert every section into a reference. When there is no title, it
>> > struggles to do this and transforms the tree i
On 2024/7/1 下午4:42, Jiaxun Yang wrote:
在2024年7月1日七月 上午8:32，maobibo写道：
[...]
+static void loongarch_cpu_check_lbt(CPUState *cs, Error **errp)
+{
+CPULoongArchState *env = cpu_env(cs);
+LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+bool kvm_supported;
+
+kvm_supported = kvm_feature
> From: "Alex Bennée"
> Date: Mon, Jul 1, 2024, 16:49
> Subject: Re: [PATCH] vhost-user: Skip unnecessary duplicated
> VHOST_USER_SET_LOG_BASE requests
> To: "项文成"
> Cc: ,
> 项文成 writes:
>
> > From: BillXiang
> >
> > The VHOST_USER_SET_LOG_BASE requests should be categorized into
> > non-vr
> > > > the PCI bridge will fail when we use SHPC Native type:
> > > >
> > > > [3.336059] shpchp :00:03.0: Requesting control of SHPC hotplug
> > > >via OSHP (\_SB_.PCI0.S28_)
> > > > [3.337408] shpchp :00:03.0: Requesting control of SHPC hotplug
> > > >via OSHP (\_SB_.PCI0)
> > > >
>-Original Message-
>From: Eric Auger
>Subject: [PATCH v2 5/7] virtio-iommu : Retrieve page size mask on
>virtio_iommu_set_iommu_device()
>
>Retrieve the Host IOMMU Device page size mask when this latter is set.
>This allows to get the information much sooner than when relying on
>IOMMU
Richard Henderson writes:
> Fix a typo in the argument movement.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
> Signed-off-by: Richard Henderson
> ---
> tcg/optimize.c
On Mon, Jul 1, 2024 at 9:52 AM Stefano Garzarella wrote:
>
> Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
> switched using of address_space_read_cached() to virito_lduw_phys_cached()
> to access packed descriptor event.
>
> When we used address_space_read_cached(), we n
When a VFIO device is hoplugged in a VM using virtio-iommu, IOMMUPciBus
and IOMMUDevice cache entries are created in the .get_address_space()
handler of the machine IOMMU device. However, these entries are never
destroyed, not even when the VFIO device is detached from the machine.
This can lead to
On 2024/06/29 22:08, BALATON Zoltan wrote:
On Thu, 27 Jun 2024, Akihiko Odaki wrote:
This fixes qemu_irq array leak.
Signed-off-by: Akihiko Odaki
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8582ac03
On Mon, Jul 01, 2024 at 11:53:34AM +0200, Eugenio Perez Martin wrote:
> On Mon, Jul 1, 2024 at 9:52 AM Stefano Garzarella wrote:
> >
> > Commit d152cdd6f6 ("virtio: use virtio accessor to access packed event")
> > switched using of address_space_read_cached() to virito_lduw_phys_cached()
> > to ac
On 2024/07/01 4:00, Richard Henderson wrote:
Supercedes: 20240629-tcg-v3-0-fa57918bd...@daynix.com
("[PATCH v3 0/7] tests/tcg/aarch64: Fix inline assemblies for clang")
On top of Akihiko's patches for aarch64, additional changes are
required for arm, both as a host and as a guest.
For the whol
Hi Cédric,
On 7/1/24 12:14, Cédric Le Goater wrote:
> When a VFIO device is hoplugged in a VM using virtio-iommu, IOMMUPciBus
> and IOMMUDevice cache entries are created in the .get_address_space()
> handler of the machine IOMMU device. However, these entries are never
> destroyed, not even when t
Hi,
All R-b now, it looks good to merge. Thanks for all the effort!
Michael, are you taking it through your tree?
On Sun, Jun 23, 2024 at 7:23 PM Dmitry Osipenko <
dmitry.osipe...@collabora.com> wrote:
> Hello,
>
> This series enables Vulkan Venus context support on virtio-gpu.
>
> All virglren
Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs
but not nested instances.
This patch series adds support for nested translation in SMMUv3,
this is controlled by property “arm-smmuv3.stage=nested”, and
advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2)
Main changes(architec
According to the SMMU architecture specification (ARM IHI 0070 F.b),
in “3.4 Address sizes”
The address output from the translation causes a stage 1 Address Size
fault if it exceeds the range of the effective IPA size for the given CD.
However, this check was missing.
There is already a s
Currently, translation stage is represented as an int, where 1 is stage-1 and
2 is stage-2, when nested is added, 3 would be confusing to represent nesting,
so we use an enum instead.
While keeping the same values, this is useful for:
- Doing tricks with bit masks, where BIT(0) is stage-1 and BIT
The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
class of events faults as:
CLASS: The class of the operation that caused the fault:
- 0b00: CD, CD fetch.
- 0b01: TTD, Stage 1 translation table fetch.
- 0b10: IN, Input address
However, this value was not set and left as 0 which
SMMUv3 OAS is currently hardcoded in the code to 44 bits, for nested
configurations that can be a problem, as stage-2 might be shared with
the CPU which might have different PARANGE, and according to SMMU manual
ARM IHI 0070F.b:
6.3.6 SMMU_IDR5, OAS must match the system physical address size.
Soon, smmuv3_do_translate() will be used to translate the CD and the
TTBx, instead of re-writting the same logic to convert the returned
cached entry to an address, add a new macro CACHED_ENTRY_TO_ADDR.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 3 +--
include/hw/arm/smmu-co
ASID and VMID used to be uint16_t in the translation config, however,
in other contexts they can be int as -1 in case of TLB invalidation,
to represent all (don’t care).
When stage-2 was added asid was set to -1 in stage-2 and vmid to -1
in stage-1 configs. However, that meant they were set as (655
With nesting, we would need to invalidate IPAs without
over-invalidating stage-1 IOVAs. This can be done by
distinguishing IPAs in the TLBs by having ASID=-1.
To achieve that, rework the invalidation for IPAs to have a
separate function, while for IOVA invalidation ASID=-1 means
invalidate for all
In the next patch, combine_tlb() will be added which combines 2 TLB
entries into one for nested translations, which chooses the granule
and level from the smallest entry.
This means that with nested translation, an entry can be cached with
the granule of stage-2 and not stage-1.
However, currentl
For the following events (ARM IHI 0070 F.b - 7.3 Event records):
- F_TRANSLATION
- F_ACCESS
- F_PERMISSION
- F_ADDR_SIZE
If fault occurs at stage 2, S2 == 1 and:
- If translating an IPA for a transaction (whether by input to
stage 2-only configuration, or after successful stage 1 translation
When nested translation is requested, do the following:
- Translate stage-1 table address IPA into PA through stage-2.
- Translate stage-1 table walk output (IPA) through stage-2.
- Create a single TLB entry from stage-1 and stage-2 translations
using logic introduced before.
For stage-1 table
smmuv3_translate() does everything from STE/CD parsing to TLB lookup
and PTW.
Soon, when nesting is supported, stage-1 data (tt, CD) needs to be
translated using stage-2.
Split smmuv3_translate() to 3 functions:
- smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW,
TLB insertio
IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
SMMU instances we consider the input address as the IOVA, but when
nesting is used, we can't mix stage-1 and stage-2 addresses, so for
nesting only stage-1 is considered the IOVA and would be notified.
Signed-off-by: Mostafa Saleh
---
h
Soon, Instead of doing TLB invalidation by ASID only, VMID will be
also required.
Add smmu_iotlb_inv_asid_vmid() which invalidates by both ASID and VMID.
However, at the moment this function is only used in SMMU_CMD_TLBI_NH_ASID
which is a stage-1 command, so passing VMID = -1 keeps the original
b
This patch adds support for nested (combined) TLB entries.
The main function combine_tlb() is not used here but in the next
patches, but to simplify the patches it is introduced first.
Main changes:
1) New field added in the SMMUTLBEntry struct: parent_perm, for
nested TLB, holds the stage-2 pe
Previously, to check if faults are enabled, it was sufficient to check
the current stage of translation and check the corresponding
record_faults flag.
However, with nesting, it is possible for stage-1 (nested) translation
to trigger a stage-2 fault, so we check SMMUPTWEventInfo as it would
have t
Everything is in place, consolidate parsing of STE cfg and setting
translation stage.
Advertise nesting if stage requested is "nested".
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 35 ++-
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/hw/ar
QEMU doesn's support memory attributes, so FWB is NOP, this
might change in the future if memory attributre would be supported.
Signed-off-by: Mostafa Saleh
---
hw/arm/smmuv3.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 807f26f2da..88378e8
Hi Berto :)
On Mon, 1 Jul 2024 at 11:56, Alberto Garcia wrote:
>
> On Wed 12 Jun 2024 02:00:19 PM +03, Manos Pitsidianakis wrote:
>
> Hi, thanks for the review and sorry for taking so long to reply, I was
> on vacation.
>
> >> scripts/qcow2-to-stdout.py | 330 +
Some commands need rework for nesting, as they used to assume S1
and S2 are mutually exclusive:
- CMD_TLBI_NH_ASID: Consider VMID if stage-2 is supported
- CMD_TLBI_NH_ALL: Consider VMID if stage-2 is supported, otherwise
invalidate everything, this required a new vmid invalidation
function fo
According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
In "5.2 Stream Table Entry":
[51:6] S1ContextPtr
If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by
stage 2 and the programmed value must be within the range of the IAS.
In "5.4.1 CD notes":
The transla
Hi Zheyu,
On 30/6/24 17:14, Zheyu Ma wrote:
This commit handles invalid address accesses gracefully in both read and write
functions. Instead of asserting and aborting, it logs an error message and
returns
a neutral value for read operations and does nothing for write operations.
Error log:
ER
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This calls the MACHINE_VER_DEPRECATION() macro in the definition of
all machine type classes which support versioning. This ensures
that they will automatically get deprecation info set when they
reach the appropriate point in their lifecycle.
Reviewed
On 20/6/24 18:57, Daniel P. Berrangé wrote:
The automatic deprecation mechanism introduced in the preceeding patches
will mark every spapr machine upto and including 2.12 as deprecated. As
such we can revert the manually added deprecation which was a subset:
commit 1392617d35765d5d912625fbb5c
On 20/6/24 18:57, Daniel P. Berrangé wrote:
The automatic deprecation mechanism introduced in the preceeding patches
will mark every i440fx machine upto and including 2.12 as deprecated. As
such we can revert the manually added deprecation introduced in:
commit 792b4fdd4eb8197bd6eb9e80a1dfaf0
Hi Salil,
> On 13 Jun 2024, at 23:36, Salil Mehta wrote:
>
> PROLOGUE
>
>
> To assist in review and set the right expectations from this RFC, please first
> read the sections *APPENDED AT THE END* of this cover letter:
>
> 1. Important *DISCLAIMER* [Section (X)]
> 2. Work presented at
There's one case where `reader_count` is accessed non-atomically. This
was likely seen as being "guarded by a mutex" held in that block, but
other access to this does not actually depend on the mutex and already
uses atomics.
Additionally this replaces the pattern of atomic_set(atomic_read() +
1)
I spotted the weird-looking pattern of:
atomic_set(atomic_load() N)
in a few palces and one variable in the graph-lock code which was used with
atomics except for a single case, which also seemed suspicious.
I'm not sure if there are any known compiler-optimizations or ordering
semantics alre
Replaces the pattern `atomic_store(atomic_load() something)`
pattern with its direct atomic function.
Signed-off-by: Wolfgang Bumiller
---
Note: these previously used RELEASE ordering for the store and `relaxed`
ordering for the reads, while the replacement uses SEQ_CST, as there are no
other wr
On Sat, 29 Jun 2024 at 07:26, Akihiko Odaki wrote:
>
> macOS versions older than 12.0 are no longer supported.
>
> docs/about/build-platforms.rst says:
> > Support for the previous major version will be dropped 2 years after
> > the new major version is released or when the vendor itself drops
> >
On Sat, 29 Jun 2024 at 11:46, Inès Varhol wrote:
>
> The QTest `test_irq_pin_multiplexer` makes the assumption that the
> reset state of irq line 15 is low, which is false since STM32L4x5 GPIO
> was implemented (the reset state of pin GPIOA15 is high because there's
> pull-up and it results in the
On Sat, 29 Jun 2024 at 12:08, Inès Varhol wrote:
>
> STM32L4x5 EXTI was incorrectly expecting alternating interrupts.
> This patch adds a new field to track IRQ levels to actually
> *detect* edges.
> It also corrects existing QTests which were modifying the IRQ lines'
> levels.
>
> Signed-off-by:
On Sat, 29 Jun 2024 at 13:51, Akihiko Odaki wrote:
>
> kvm-steal-time and sve properties are added for KVM even if the
> corresponding features are not available. Always add pmu property too.
>
> Signed-off-by: Akihiko Odaki
> ---
> target/arm/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
On Fri, 2024-06-28 at 12:23 +0100, Daniel P. Berrangé wrote:
> On Fri, Jun 28, 2024 at 12:09:59PM +0100, Roy Hopkins wrote:
> > On Mon, 2024-06-24 at 15:00 +0100, Daniel P. Berrangé wrote:
> > > On Fri, Jun 21, 2024 at 03:29:07PM +0100, Roy Hopkins wrote:
> > > > An IGVM file contains configuration
On 2024/07/01 20:43, Peter Maydell wrote:
On Sat, 29 Jun 2024 at 07:26, Akihiko Odaki wrote:
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
Support for the previous major version will be dropped 2 years after
the new major version is released or
On 30/6/24 21:00, Richard Henderson wrote:
This avoids a memcpy to the stack when compiled with clang.
Since we don't enable optimization, nor provide memcpy,
this results in an undefined symbol error at link time.
Signed-off-by: Richard Henderson
---
tests/tcg/minilib/printf.c | 2 +-
1 fil
On 2024/07/01 20:54, Peter Maydell wrote:
On Sat, 29 Jun 2024 at 13:51, Akihiko Odaki wrote:
kvm-steal-time and sve properties are added for KVM even if the
corresponding features are not available. Always add pmu property too.
Signed-off-by: Akihiko Odaki
---
target/arm/cpu.c | 3 ++-
1
On Sun, 30 Jun 2024 at 18:00, Zheyu Ma wrote:
>
> The PL011 TRM says that "The 16-bit integer is written to the Integer Baud
> Rate
> Register, UARTIBRD". Updated the handling of the UARTIBRD register to ensure
> only 16-bit values are written to it.
Thanks for this patch.
I think we could impr
I have no issues with these APIs, but I'm not a QMP expert so others
should review those bits.
For the vhost-user-blk code:
Acked-by: Raphael Norwitz
On Tue, Jun 25, 2024 at 8:19 AM Vladimir Sementsov-Ogievskiy
wrote:
>
> v5:
> 03: drop extra check on is is runstate running
>
>
> Vladimir Seme
On Sun, 30 Jun 2024 at 17:33, Zheyu Ma wrote:
>
> The musb_reset function was causing a memory leak by not properly freeing
> the memory associated with USBPacket instances before reinitializing them.
> This commit addresses the memory leak by adding calls to usb_packet_cleanup
> for each USBPacke
Extend copy command to copy user data across different namespaces via
support for specifying a namespace for each source range
Signed-off-by: Arun Kumar
---
Notes:
v1->v2: updated commit message
hw/nvme/ctrl.c | 355 ---
include/block/nvme.h |
On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote:
>
> To allow embedding a qemu_irq in a struct move its definition to the
> header and add a function to init it in place without allocating it.
>
> Signed-off-by: BALATON Zoltan
Yes, I think this makes sense, and I'm not quite sure
why we don't
Hi Cédric,
On 7/1/24 12:14, Cédric Le Goater wrote:
> When a VFIO device is hoplugged in a VM using virtio-iommu, IOMMUPciBus
> and IOMMUDevice cache entries are created in the .get_address_space()
> handler of the machine IOMMU device. However, these entries are never
> destroyed, not even when t
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This changes the DEFINE_CCW_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number twice in two
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This changes the DEFINE_VIRT_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
A DEFINE_VIRT_MACHINE_AS_LATEST helper is added so that it
is not required to pass 'f
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This changes the DEFINE_VIRT_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
Reviewed-by: Thomas Huth
Signed-off-by: Daniel P. Berrangé
---
hw/arm/virt.c | 28
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This changes the DEFINE_I440FX_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice in
On Sat, 29 Jun 2024 at 21:01, BALATON Zoltan wrote:
>
> To avoid a warning about unfreed qemu_irq embed the i8259 irq in the
> device state instead of allocating it.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/isa/vt82c686.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> dif
On 20/6/24 18:57, Daniel P. Berrangé wrote:
This changes the DEFINE_Q35_MACHINE macro to use the common
helpers for constructing versioned symbol names and strings,
bringing greater consistency across targets.
The added benefit is that it avoids the need to repeat the
version number thrice in th
Hi,
we got a user report about bootindex for an 'usb-storage' device not
working anymore [0] and I reproduced it and bisected it to this patch.
Am 31.01.24 um 14:06 schrieb Kevin Wolf:
> @@ -399,11 +397,10 @@ SCSIDevice *scsi_bus_legacy_add_drive(SCSIBus *bus,
> BlockBackend *blk,
> object_
Hi all,
Following this commit, a test which install Debian in a guest with OVMF
as firmware started to fail. QEMU exit with an error when GRUB is
running on the freshly installed Debian (I don't know if GRUB is
starting Linux or not).
The error is:
Bad ram offset
Some logs:
h
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