On 2024/06/28 16:27, Mark Cave-Ayland wrote:
On 27/06/2024 14:37, Akihiko Odaki wrote:
This fixes qemu_irq array leak.
Signed-off-by: Akihiko Odaki
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8
On 2024/06/29 16:38, Akihiko Odaki wrote:
On 2024/06/28 16:27, Mark Cave-Ayland wrote:
On 27/06/2024 14:37, Akihiko Odaki wrote:
This fixes qemu_irq array leak.
Signed-off-by: Akihiko Odaki
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw
On Fri, 28 Jun 2024 22:12, Pierrick Bouvier wrote:
I've been able to build rust device on windows, with a few tweaks
needed.
- specificy the target for libclang (used by bindgen), which targets
MSVC by default (so different set of headers)
- additional headers (libclang searches its own heade
On 2024/06/29 2:19, Richard Henderson wrote:
On 6/27/24 06:58, Akihiko Odaki wrote:
clang version 18.1.6 assumes a register is 64-bit by default and
complains if a 32-bit value is given. Explicitly specify register width
when passing a 32-bit value.
Signed-off-by: Akihiko Odaki
Reviewed-by: Phi
sme-smopa-2.c requires sme-i16i64 but the compiler option used not to
specify it. Instead, the extension was specified with the inline
assembly, resulting in mixing assembly code targeting sme-i1664 and C
code that does not target sme-i1664.
clang version 18.1.6 does not support such mixing so pro
clang version 18.1.6 does not allow specifying an integer as the value
of a single-precision register. Manually bit-cast into float with vmov
first.
Signed-off-by: Akihiko Odaki
---
tests/tcg/arm/fcvt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/arm/fcvt.c b
The availability of -Wa,-march=armv9-a+sme was checked but it was never
used. Use it for SME tests.
Signed-off-by: Akihiko Odaki
---
tests/tcg/aarch64/Makefile.target | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/aarch64/Makefile.target
b/tests/tcg/aarch64/Makefile.target
index
clang version 18.1.6 assumes a register is 64-bit by default and
complains if a 32-bit value is given. Explicitly specify register width
when passing a 32-bit value.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
tests/tcg/aarch64/bti-1.c |
irg expects 64-bit integers. Passing a 32-bit integer results in
compilation failure with clang version 18.1.6.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
tests/tcg/aarch64/mte-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/mte-1.c
clang version 18.1.6 does not support x constraint for AArch64.
Use w instead.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
tests/tcg/arm/fcvt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/arm/fcvt.c b/tests/tcg/arm/fcvt.c
inde
clang version 18.1.6 does not respect -Wa,-march=armv9-a+sme without
-fno-integrated-as. Use it when available.
Signed-off-by: Akihiko Odaki
---
tests/tcg/aarch64/Makefile.target | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/Makefile.target
b/tests
Unlike GCC, clang checks if the operands in assembly matches with the
type in C. It also does not support "x" constraint for AArch64 and
complains about them.
Signed-off-by: Akihiko Odaki
---
Changes in v3:
- Added patch "tests/tcg/aarch64: Use -fno-integrated-as".
- Added patch "tests/tcg/aarch6
The QTest `test_irq_pin_multiplexer` makes the assumption that the
reset state of irq line 15 is low, which is false since STM32L4x5 GPIO
was implemented (the reset state of pin GPIOA15 is high because there's
pull-up and it results in the irq line 15 also being high at reset).
It wasn't triggerin
STM32L4x5 EXTI was incorrectly expecting alternating interrupts.
This patch adds a new field to track IRQ levels to actually
*detect* edges.
It also corrects existing QTests which were modifying the IRQ lines'
levels.
Signed-off-by: Inès Varhol
Inès Varhol (2):
hw/misc: In STM32L4x5 EXTI, corr
EXTI's new field `irq_levels` tracks irq levels between tests when using
`global_qtest`.
This happens in `stm32l4x5_exti-test.c`, `stm32l4x5_syscfg-test.c` and
`stm32l4x5_gpio-test.c` (`dm163.c` doesn't use `global_qtest`).
To ensure that `irq_levels` has the same value before and after each
QTest
The implementation of configurable interrupts (interrupts supporting
edge selection) was incorrectly expecting alternating input levels :
this commits adds a new status field `irq_levels` to actually detect
edges.
Signed-off-by: Inès Varhol
---
include/hw/misc/stm32l4x5_exti.h | 2 ++
hw/misc/s
Hi
On Fri, Jun 28, 2024 at 1:32 PM Zhenzhong Duan
wrote:
> EDID related device region info is leaked in three paths:
> 1. In vfio_get_dev_region_info(), when edid info isn't find, the last
> device region info is leaked.
> 2. In vfio_display_edid_init() error path, edid info is leaked.
> 3. In V
On Fri, Jun 28, 2024 at 1:31 PM Zhenzhong Duan
wrote:
> vfio_display_edid_init() can fail for many reasons and return silently.
> It would be good to report the error.
>
> Old mdev driver may not support vfio edid region and we allow to go
> through in this case.
>
> vfio_display_edid_update() is
On Thu, Jun 27, 2024 at 3:19 PM Akihiko Odaki
wrote:
> Signed-off-by: Akihiko Odaki
>
Reviewed-by: Marc-André Lureau
> ---
> include/ui/console.h| 4 ++--
> hw/display/ati.c| 2 +-
> hw/display/virtio-gpu.c | 3 +--
> hw/display/vmware_vga.c | 2 +-
> ui/console.c
On Thu, Jun 27, 2024 at 3:19 PM Akihiko Odaki
wrote:
> Remove dpy_cursor_define_supported() as it brings no benefit today and
> it has a few inherent problems.
>
> All graphical displays except egl-headless support cursor composition
> without DMA-BUF, and egl-headless is meant to be used in conj
On Mon, Jun 24, 2024 at 2:11 PM Phil Dennis-Jordan
wrote:
> Mouse cursors with 8 bit alpha were downsampled to 1-bit opacity maps by
> turning alpha values of 255 into 1 and everything else into 0. This
> means that mostly-opaque pixels ended up completely invisible.
>
> This patch changes the be
target/arm/kvm.c checked PMU availability but claimed PMU is
available even if it is not. In fact, Asahi Linux supports KVM but lacks
PMU support. Only advertise PMU availability only when it is really
available.
Fixes: dc40d45ebd8e ("target/arm/kvm: Move kvm_arm_get_host_cpu_features and
unexpor
Asahi Linux supports KVM but lacks PMU support.
Signed-off-by: Akihiko Odaki
---
tests/qtest/arm-cpu-features.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 966c65d5c3e4..cfd6f7735354 10064
+-
tests/qtest/arm-cpu-features.c | 13 -
3 files changed, 11 insertions(+), 7 deletions(-)
---
base-commit: 046a64b9801343e2e89eef10c7a48eec8d8c0d4f
change-id: 20240629-pmu-ad5f67e2c5d0
Best regards,
--
Akihiko Odaki
kvm-steal-time and sve properties are added for KVM even if the
corresponding features are not available. Always add pmu property too.
Signed-off-by: Akihiko Odaki
---
target/arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index
On Thu, 27 Jun 2024, Akihiko Odaki wrote:
This fixes qemu_irq array leak.
Signed-off-by: Akihiko Odaki
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8582ac0322eb..629d2d568137 100644
--- a/hw/isa/vt82c
Existing code was long, unclear and twisty.
Signed-off-by: Michael Tokarev
---
block/curl.c | 44 ++--
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/block/curl.c b/block/curl.c
index 419f7c89ef..9802d0319d 100644
--- a/block/curl.c
+++ b/
On 6/28/24 10:28, Paolo Bonzini wrote:
The following changes since commit 28b8a57ad63670aa0ce90334523dc552b13b4336:
Merge tag 'pull-riscv-to-apply-20240627-1'
ofhttps://github.com/alistair23/qemu into staging (2024-06-27 07:36:16 -0700)
are available in the Git repository at:
https://g
On 6/29/24 01:56, Akihiko Odaki wrote:
clang version 18.1.6 does not allow specifying an integer as the value
of a single-precision register. Manually bit-cast into float with vmov
first.
Signed-off-by: Akihiko Odaki
---
tests/tcg/arm/fcvt.c | 4 +++-
1 file changed, 3 insertions(+), 1 delet
On 6/29/24 05:50, Akihiko Odaki wrote:
Akihiko Odaki (3):
tests/arm-cpu-features: Do not assume PMU availability
target/arm: Always add pmu property
target/arm/kvm: Report PMU unavailability
Reviewed-by: Richard Henderson
r~
On Fri, 28 Jun 2024 at 19:13, Gustavo Romero wrote:
> Re-reading it after your clarifications makes it clear, but the first time
> Phil pointed it out the phrases:
>
> "[...] since the .c file will have already included it." and
> "Headers should normally include everything they need beyond osdep.
To avoid a warning about unfreed qemu_irq embed the i8259 irq in the
device state instead of allocating it.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8582ac0322..83405
To allow embedding a qemu_irq in a struct move its definition to the
header and add a function to init it in place without allocating it.
Signed-off-by: BALATON Zoltan
---
hw/core/irq.c| 25 +++--
include/hw/irq.h | 18 ++
2 files changed, 29 insertions(+)
This is an alternative appriach to solve the qemu_irq leak in
vt82c686. Allowing embedding an irq and init it in place like done
with other objects may allow cleaner fix for similar issues and I also
plan to use this for adding qemu_itq to pegasos2 machine state for
which gpio would not work.
BALA
On 6/26/24 16:37, Pierrick Bouvier wrote:
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Signed-off-by: Pierrick Bouvier
---
tests/tcg/Makefile.target | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Hende
We have sent their implementations separately, and we have received few
objective
comments except for some ISA extensions order. So, I have put them together
as one patch set to make it easier for merging.
v1->v2:
1. Fix the isa orders.
2. Make zimop/zcmop/zama16b/zabha depend on priviled
Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
additionally defines 8 MOP instructions named MOP.RR.n, where n
is an integer between 0 and 7.
These 40 MOPs i
Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
the reserved encoding space corresponding to C.LUI xn, 0.
Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
are defined to not write any re
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
disas/riscv.c | 100 ++
1 file changed, 100 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 90d6b26de9..3ecbdcbe8d 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -906,6 +90
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei
Acked-by: Ali
Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to AMOs, loads
and stores defined in the base ISAs, and loads and stores of no more
than XLEN bits defined in the F, D, and Q exten
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 21 -
target/riscv/translate.c| 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.in
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131
target/riscv/translate.c| 4 +-
4 fil
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/translate.c| 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
b
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8a4801d4
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5219b44176..8cd52e6801 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -117,6 +117,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
I
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2e315b4936..05b663ebfe 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6 +954
On 6/28/24 05:42, Alex Bennée wrote:
From: Akihiko Odaki
The test cases for "converting double-precision to single-precision"
emits float but the result variable was typed as uint32_t and corrupted
the printed values. Propertly type it as float.
Signed-off-by: Akihiko Odaki
Fixes: 8ec8a55e3fc
On 6/28/24 17:58, Brad Smith wrote:
util/cpuinfo-ppc: Add FreeBSD support
Signed-off-by: Brad Smith
---
v2: Use ifndef with PPC_FEATURE2_ARCH_3_1
util/cpuinfo-ppc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Thanks, and queued.
r~
From: Jeuk Kim
The following changes since commit 3665dd6bb9043bef181c91e2dce9e1efff47ed51:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-06-28 16:09:38 -0700)
are available in the Git repository at:
https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-202
From: Minwoo Im
This patch fixes two points reported in coverity scan report [1]. Check
the MMIO access address with (addr + size), not just with the start offset
addr to make sure that the requested memory access not to exceed the
actual register region. We also updated (uint8_t *) to (uint32_
From: thomas
Patch 06b12970174 ("virtio-net: fix network stall under load")
added double-check to test whether the available buffer size
can satisfy the request or not, in case the guest has added
some buffers to the avail ring simultaneously after the first
check. It will be lucky if the availab
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