[PATCH v7 00/11] Add RISC-V ISA extension smcntrpmf support

- target/riscv/op_helper.c | 17 +-- target/riscv/pmu.c| 181 --- target/riscv/pmu.h| 4 + 10 files changed, 543 insertions(+), 145 deletions(-) --- base-commit: 842a3d79a0e37cd3d685c4728308fac0d9bfd0bb change-id: 20240626-smcntrpmf_v7-3b275d1da117 -- Regards, Atish patra

[PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support

From: Kaiwen Xue QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: At

[PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret

Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires Smcntrpmf while the other one requires Sscofpmf to be enabled. The cycle/instr

[PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.

From: Rajnesh Kanwal Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() functions. This is to make complete mode change information available through a single function. This allows to easily differentiate between HS->VS, VS->HS and VS->VS transitions when executing state update code

[PATCH v7 07/11] target/riscv: Save counter values during countinhibit update

Currently, if a counter monitoring cycle/instret is stopped via mcountinhibit we just update the state while the value is saved during the next read. This is not accurate as the read may happen many cycles after the counter is stopped. Ideally, the read should return the value saved when the counte

[PATCH v7 08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren

scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/csr.c | 12 ++--

[PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b

[PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit

From: Rajnesh Kanwal Currently we start timer counter from write_mhpmcounter path only without checking for mcountinhibit bit. This changes adds mcountinhibit check and also programs the counter from write_mcountinhibit as well. When a counter is stopped using mcountinhibit we simply update the

[PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled

The timer is setup function is invoked in both hpmcounter write and mcountinhibit write path. If the OF bit set, the LCOFI interrupt is disabled. There is no benefitting in setting up the qemu timer until LCOFI is cleared to indicate that interrupts can be fired again. Signed-off-by: Atish Patra

[PATCH v7 10/11] target/riscv: More accurately model priv mode filtering.

From: Rajnesh Kanwal In case of programmable counters configured to count inst/cycles we often end-up with counter not incrementing at all from kernel's perspective. For example: - Kernel configures hpm3 to count instructions and sets hpmcounter to -1 and all modes except U mode are inhibi

[PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35 insertion

[PATCH v7 02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- tar

[PATCH v3] timer: Fix a race condition between timer's callback and destroying code

`timerlist_run_timers` provides no mechanism to make sure the data pointed by `opaque` is valid when calling timer's callback: there could be another thread running which is destroying timer's opaque data. With this change `timer_del` becomes blocking if timer's callback is running and it will be

Re: [PATCH v2 2/5] migration: Add migration parameters for QATzip

> On Mar 28, 2024, at 12:23 AM, Liu, Yuan1 wrote: > >> -Original Message- >> From: Bryan Zhang >> Sent: Wednesday, March 27, 2024 6:42 AM >> To: qemu-devel@nongnu.org >> Cc: pet...@redhat.com; faro...@suse.de; Liu, Yuan1 ; >> berra...@redhat.com; Zou, Nanhai ; >> hao.xi...@linux.dev;

Re: [PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

On Wed, Jun 26, 2024 at 11:25 PM Alvin Chang via wrote: > > From: Alvin Chang via Something is still strange with your From Alistair > > According to RISC-V Debug specification version 0.13 [1] (also applied > to version 1.0 [2] but it has not been ratified yet), there are several > common mat

[PATCH v2] util: fix building on OpenBSD/powerpc

util: fix building on OpenBSD/powerpc Signed-off-by: Brad Smith --- v2: Keep headers in the same order as they originally were. util/cpuinfo-ppc.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c index b2d8893a06..

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

From: Alvin Chang According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for che

[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the t

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

From: Alvin Chang via We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alis

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

From: Alvin Chang via According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger

RE: [PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

> -Original Message- > From: Alistair Francis > Sent: Thursday, June 27, 2024 10:18 AM > To: Alvin Che-Chia Chang(張哲嘉) > Cc: qemu-ri...@nongnu.org; qemu-devel@nongnu.org; > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com; > dbarb...@ventanamicro.com; zhiwei_...@linux

Re: [PATCH v3 1/4] hw/intc: Remove loongarch_ipi.c

在 2024/6/26 下午8:10, Philippe Mathieu-Daudé 写道: Hi Bibo, On 26/6/24 06:11, maobibo wrote: On 2024/6/5 上午10:15, Jiaxun Yang wrote: It was missed out in previous commit. Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi") Signed-off-by: Jiaxun Yang ---   hw/intc/loongarch_ip

Re: [PATCH v5 2/6] hw/ssi: Add SPI model

> An existing QEMU SSI framework is used and SSI_BUS is created. > > Signed-off-by: Chalapathi V Reviewed-by: Caleb Schlossin Thanks, Caleb Schlossin From: Chalapathi V Sent: Wednesday, June 26, 2024 4:05 AM To: qemu-devel@nongnu.org Cc: qemu-...@nongnu.org ;

PING: [PATCH v6 00/10] Support persistent reservation operations

Hi, @Stefan, many thanks to you for reviewing the code. @Klaus, the block layer code has been reviewed by Stefan. Please help review the nvme layer code. @Paolo, Please help review the scsi layer code and iscsi driver code. Thank you! On 2024/6/13 15:13, Changqi Lu wrote: > Hi, > > patch v6 has

Re: [PATCH v5 6/6] tests/qtest: Add pnv-spi-seeprom qtest

> In this commit Write a qtest pnv-spi-seeprom-test to check the > SPI transactions between spi controller and seeprom device. > > Signed-off-by: Chalapathi V > Acked-by: Cédric Le Goater Reviewed-by: Caleb Schlossin Thanks, Caleb Schlossin From: Chalapathi V

RE: [PATCH 4/7] HostIOMMUDevice: Introduce get_page_size_mask() callback

Hi Eric, >-Original Message- >From: Eric Auger >Subject: [PATCH 4/7] HostIOMMUDevice: Introduce get_page_size_mask() >callback > >This callback will be used to retrieve the page size mask supported >along a given Host IOMMU device. > >Signed-off-by: Eric Auger >--- > include/hw/vfio/vfio

[PATCH v6 0/3] RISC-V: Modularize common match conditions for trigger

According to RISC-V Debug specification ratified version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels of the trigger is common match conditions for all the types of the trigger. This series modularize the code for checking the privilege

[PATCH v6 1/3] target/riscv: Add functions for common matching conditions of trigger

According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepa

[PATCH v6 3/3] target/riscv: Apply modularized matching conditions for icount trigger

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang Acked-by: Alistair Francis --- targe

[PATCH v6 2/3] target/riscv: Apply modularized matching conditions for watchpoint

We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 trigger

RE: [PATCH v2 6/7] tests/plugin/mem: add option to print memory accesses

Hi, Pierrick > +static void print_access(unsigned int cpu_index, qemu_plugin_meminfo_t > meminfo, > + uint64_t vaddr, void *udata) > +{ > +unsigned size = 8 << qemu_plugin_mem_size_shift(meminfo); > +const char *type = qemu_plugin_mem_is_store(meminfo) ? "store" : "

Re: [RFC PATCH 6/7] migration/multifd: Move payload storage out of the channel parameters

On 6/21/2024 5:21, Fabiano Rosas wrote:> Multifd currently has a simple scheduling mechanism that distributes > work to the various channels by providing the client (producer) with a > memory slot and swapping that slot with free slot from the next idle > channel (consumer). Or graphically: > > []

[PATCH 2/2] MAINTAINERS: Add myself as a reviewer of LoongArch virt machine

I would like to be informed on changes made to the LoongArch virt machine. I'm fairly familiar with Loongson-3 series platform hardware and doing firmwre (U-Boot) development as hobbyist on LoongArch virt platform, so I believe I can give positive review input to changes on that machine. Signed-o

[PATCH v5 1/9] gdbstub: Clean up process_string_cmd

Change 'process_string_cmd' to return true on success and false on failure, instead of 0 and -1. Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- gdbstub/gdbstub.c | 40 1 file changed, 20 insertions(+), 20 delet

[PATCH v5 8/9] gdbstub: Add support for MTE in user mode

This commit implements the stubs to handle the qIsAddressTagged, qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' subcommands to work with QEMU gdbstub on aarch64 user mode. It also implements the get/set functions for the special GDB MTE register 'tag_ctl', used to control the MTE f

[PATCH 1/2] hw/intc/loongson_ipi: Gate MMIO regions creation with property

Commit 49eba52a52fe ("hw/intc/loongson_ipi: Provide per core MMIO address spaces") implemented per core MMIO spaces for IPI registers. However on LoongArch system emulation with high core count it may exhaust QDEV_MAX_MMIO and trigger assertion. Given that MMIO region is unused for LoongArch syst

[PATCH v5 9/9] tests/tcg/aarch64: Add MTE gdbstub tests

Add tests to exercise the MTE stubs. The tests will only run if a version of GDB that supports MTE is available in the test environment. Signed-off-by: Gustavo Romero --- configure | 4 ++ tests/tcg/aarch64/Makefile.target | 14 +++- tests/tcg/aarch64/gdbstub/tes

[PATCH v5 0/9] Add MTE stubs for aarch64 user mode

This patchset adds the stubs necessary to support GDB memory tagging commands on QEMU aarch64 user mode. These new stubs handle the qIsAddressTagged, qMemTag, and QMemTag packets, which allow GDB memory tagging subcommands 'check', 'print-allocation-tag', and 'set-allocation-tag' to work. The rema

[PATCH v5 4/9] target/arm: Fix exception case in allocation_tag_mem_probe

If page in 'ptr_access' is inaccessible and probe is 'true' allocation_tag_mem_probe should not throw an exception, but currently it does, so fix it. Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 3 +++ 1 file changed, 3

[PATCH v5 6/9] target/arm: Factor out code for setting MTE TCF0 field

Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-of

[PATCH 0/2] hw/intc/loongson_ipi: Fix for LoongArch

Signed-off-by: Jiaxun Yang --- Jiaxun Yang (2): hw/intc/loongson_ipi: Gate MMIO regions creation with property MAINTAINERS: Add myself as a reviewer of LoongArch virt machine MAINTAINERS| 1 + hw/intc/loongson_ipi.c | 23 ++- hw/mips/l

[PATCH v5 5/9] target/arm: Make some MTE helpers widely available

Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 45 - target/arm/tcg/mte_helper.h | 66 +

[PATCH v5 7/9] gdbstub: Make get cpu and hex conversion functions non-internal

Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they are not confined to use only in gdbstub.c. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- gdbstub/internals.h| 2 -- include/exec/gdbstub.h | 5 + include/gdbstub/commands.h | 6 ++ 3 fil

[PATCH v5 3/9] gdbstub: Add support for target-specific stubs

Currently, it's not possible to have stubs specific to a given target, even though there are GDB features which are target-specific, like, for instance, memory tagging. This commit introduces gdb_extend_qsupported_features, gdb_extend_query_table, and gdb_extend_set_table functions as interfaces t

[PATCH v5 2/9] gdbstub: Move GdbCmdParseEntry into a new header file

Move GdbCmdParseEntry and its associated types into a separate header file to allow the use of GdbCmdParseEntry and other gdbstub command functions outside of gdbstub.c. Since GdbCmdParseEntry and get_param are now public, kdoc GdbCmdParseEntry and rename get_param to gdb_get_cmd_param. This comm

Re: [PATCH v1] memory tier: consolidate the initialization of memory tiers

June 25, 2024 at 1:46 AM, "Huang, Ying" wrote: Hi Huang, Ying, I'm working on the v2 according to Andrew's and your feedback. Thank you for your confirmation. > > "Ho-Ren Chuang" writes: > > > > > June 24, 2024 at 1:27 AM, "Huang, Ying" wrote: > > > > Hi Huang, Ying, > > > > Thanks fo

[PATCH] tcg/riscv: Fix building on OpenBSD/riscv64

tcg/riscv: Fix building on OpenBSD/riscv64 Use ucontext_t/struct sigcontext member name from machine/signal.h instead of Linux specific name. Signed-off-by: Brad Smith --- tcg/riscv/tcg-target.c.inc | 5 + 1 file changed, 5 insertions(+) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/

[PATCH] hw/core/loader: allow loading larger ROMs

The read() syscall is not guaranteed to return all data from a file. The default ROM loader implementation currently does not take this into account, instead failing if all bytes are not read at once. This change wraps the read() syscall in a do/while loop to ensure all bytes of the ROM are read.

Re: [PATCH v4 5/9] target/arm: Make some MTE helpers widely available

Hi Phil, Richard On 6/24/24 4:47 AM, Philippe Mathieu-Daudé wrote: Hi Gustavo, On 24/6/24 07:30, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Again, you can make them available externally by removing the static

Re: [PATCH] hw/i386/intel_iommu: Block CFI when necessary

On Wed, Jun 26, 2024 at 2:15 PM cmd wrote: > Hi, > > On 25/06/2024 13:28, Yuke Peng wrote: > > According to Intel VT-d specification 5.1.4, CFI must be blocked when > > Extended Interrupt Mode is enabled or Compatibility format interrupts > > are disabled. > > > > Signed-off-by: Yuke Peng > > --

Re: [PATCH] hw/i386/intel_iommu: Block CFI when necessary

On 27/06/2024 07:08, Yuke Peng wrote: On Wed, Jun 26, 2024 at 2:15 PM cmd wrote: Hi, On 25/06/2024 13:28, Yuke Peng wrote: > According to Intel VT-d specification 5.1.4, CFI must be blocked when > Extended Interrupt Mode is enabled or Compatibility format interrupts

Re: [PATCH v2 6/7] tests/plugin/mem: add option to print memory accesses

Hi Xingtao, On 6/26/24 20:17, Xingtao Yao (Fujitsu) wrote: Hi, Pierrick +static void print_access(unsigned int cpu_index, qemu_plugin_meminfo_t meminfo, + uint64_t vaddr, void *udata) +{ +unsigned size = 8 << qemu_plugin_mem_size_shift(meminfo); +const char *typ

Re: [PATCH v5 5/9] target/arm: Make some MTE helpers widely available

On 27/6/24 06:13, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 45 - target/arm/tcg/mte_hel

Re: [PATCH v5 2/9] gdbstub: Move GdbCmdParseEntry into a new header file

On 27/6/24 06:13, Gustavo Romero wrote: Move GdbCmdParseEntry and its associated types into a separate header file to allow the use of GdbCmdParseEntry and other gdbstub command functions outside of gdbstub.c. Since GdbCmdParseEntry and get_param are now public, kdoc GdbCmdParseEntry and rename

RE: [PATCH v2 6/7] tests/plugin/mem: add option to print memory accesses

> -Original Message- > From: Pierrick Bouvier > Sent: Thursday, June 27, 2024 1:29 PM > To: Yao, Xingtao/姚 幸涛 ; qemu-devel@nongnu.org > Cc: Alexandre Iooss ; Philippe Mathieu-Daudé > ; Mahmoud Mandour ; Paolo > Bonzini ; Eduardo Habkost ; > Richard Henderson ; Alex Bennée > > Subject: R

Re: [PATCH v5 6/9] target/arm: Factor out code for setting MTE TCF0 field

On 27/6/24 06:13, Gustavo Romero wrote: Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this

[PATCH v10 00/12] hw/pci: SR-IOV related fixes and improvements

I submitted a RFC series[1] to add support for SR-IOV emulation to virtio-net-pci. During the development of the series, I fixed some trivial bugs and made improvements that I think are independently useful. This series extracts those fixes and improvements from the RFC series. [1]: https://patche

[PATCH v10 06/12] pcie_sriov: Reuse SR-IOV VF device instances

Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 5 --- incl

[PATCH v10 03/12] hw/ppc/spapr_pci: Do not reject VFs created after a PF

A PF may automatically create VFs and the PF may be function 0. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index f63182a03c41..ed4454bbf79e 100644 --- a/hw/ppc/spapr_pci.c +++

[PATCH v10 02/12] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

Disabled means it is a disabled SR-IOV VF or it is powered off, and hidden from the guest. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7cf9904c3546..f63182a03c41 100644 --- a/hw/ppc/spap

[PATCH v10 04/12] pcie_sriov: Do not manually unrealize

A device gets automatically unrealized when being unparented. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 4 1 file changed, 4 deletions(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index e9b23221d713..499becd5273f 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_

[PATCH v10 07/12] pcie_sriov: Release VFs failed to realize

Release VFs failed to realize just as we do in unregister_vfs(). Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri

[PATCH v10 08/12] pcie_sriov: Remove num_vfs from PCIESriovPF

num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 1 - hw/pci/pcie_sriov.c | 28 hw/pci/trace-events | 2 +- 3 files changed, 21 insertions(+), 10 deletions

[PATCH v10 01/12] hw/pci: Rename has_power to enabled

The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 7 ++- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c| 14 +++--- hw/pci/pci_host

[PATCH v10 10/12] hw/pci: Replace -1 with UINT32_MAX for romsize

romsize is an uint32_t variable. Specifying -1 as an uint32_t value is obscure way to denote UINT32_MAX. Worse, if int is wider than 32-bit, it will change the behavior of a construct like the following: romsize = -1; if (romsize != -1) { ... } When -1 is assigned to romsize, -1 will be impli

Re: [PATCH v5 7/9] gdbstub: Make get cpu and hex conversion functions non-internal

On 27/6/24 06:13, Gustavo Romero wrote: Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they are not confined to use only in gdbstub.c. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- gdbstub/internals.h| 2 -- include/exec/gdbstub.h | 5 +

[PATCH v10 05/12] pcie_sriov: Ensure VF function number does not overflow

pci_new() aborts when creating a VF with a function number equals to or is greater than PCI_DEVFN_MAX. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 8 +--- include/hw/pci/pcie_sriov.h | 5 +++-- hw/net/igb.c| 13 ++--- hw/nvme/ctrl.c |

[PATCH v10 12/12] hw/qdev: Remove opts member

It is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- include/hw/qdev-core.h | 4 hw/core/qdev.c | 1 - system/qdev-monitor.c | 12 +++- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/i

[PATCH v10 09/12] pcie_sriov: Register VFs after migration

pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- in

[PATCH v10 11/12] hw/pci: Convert rom_bar into OnOffAuto

rom_bar is tristate but was defined as uint32_t so convert it into OnOffAuto. Signed-off-by: Akihiko Odaki --- docs/igd-assign.txt | 2 +- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c | 4 ++-- hw/vfio/pci-quirks.c | 2 +- hw/vfio/pci

RE: [PATCH] hw/core/loader: allow loading larger ROMs

Hi, Gregor > > The read() syscall is not guaranteed to return all data from a file. The > default ROM loader implementation currently does not take this into account, > instead failing if all bytes are not read at once. This change wraps the > read() syscall in a do/while loop to ensure all bytes

Re: [PATCH v2 03/21] docs/qapidoc: remove unused intersperse function

On Thu, Jun 27, 2024, 2:02 AM Markus Armbruster wrote: > John Snow writes: > > > This function has been unused since fd62bff901b. > > > > Signed-off-by: John Snow > > Reviewed-by: Markus Armbruster > > I assume you won't mind me adding a bit of polish: "since commit > fd62bff901b (sphinx/qapid

Re: [PATCH 0/3] target/i386/sev: Fix 32-bit host build issues

On 26/6/24 21:49, Richard Henderson wrote: Richard Henderson (3): target/i386/sev: Cast id_auth_uaddr through uintptr_t target/i386/sev: Use size_t for object sizes target/i386/sev: Fix printf formats Series: Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v5 7/9] gdbstub: Make get cpu and hex conversion functions non-internal

On 27/6/24 08:10, Philippe Mathieu-Daudé wrote: On 27/6/24 06:13, Gustavo Romero wrote: Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they are not confined to use only in gdbstub.c. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson ---   gdbstub/internals.h  

Re: [PATCH v2 05/21] qapi/parser: preserve indentation in QAPIDoc sections

On Thu, Jun 27, 2024, 2:25 AM Markus Armbruster wrote: > John Snow writes: > > > Change get_doc_indented() to preserve indentation on all subsequent text > > lines, and create a compatibility dedent() function for qapidoc.py that > > removes indentation the same way get_doc_indented() did. > > >

Re: [PATCH 0/2] hw/intc/loongson_ipi: Fix for LoongArch

On 27/6/24 06:13, Jiaxun Yang wrote: Signed-off-by: Jiaxun Yang --- Jiaxun Yang (2): hw/intc/loongson_ipi: Gate MMIO regions creation with property MAINTAINERS: Add myself as a reviewer of LoongArch virt machine Maybe s/has-mmio/use-mmio/? Otherwise series: Reviewed-by: Philippe

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