On Tue, Jun 25, 2024 at 6:21 AM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> Generate device tree entry for riscv-iommu PCI device, along with
> mapping all PCI device identifiers to the single IOMMU device instance.
>
> Signed-off-by: Tomasz Jeznach
> Signed-off-by: Daniel Henriq
The crash was reported in MAC OS and NixOS, here is the link for this bug
https://gitlab.com/qemu-project/qemu/-/issues/2334
https://gitlab.com/qemu-project/qemu/-/issues/2321
The root cause is the function virtio_pci_set_guest_notifiers() was not called
in the virtio_input device.So the vector_ir
From: Dongwon Kim
Negative page number means the page with that number does not
belong to the notebook so it shouldn't be used as a valid page
number in gd_vc_find_by_page. This function should just return
null in such case.
This change, however, will cause a segfault during detaching
/untabifyi
A nested SMMU must use iommufd ioctls to communicate with the host-level
SMMU instance for 2-stage translation support. Add an iommufd link to the
ARM virt-machine, allowing QEMU command to pass in an iommufd object.
Signed-off-by: Nicolin Chen
---
hw/arm/virt.c | 14 ++
incl
I’m sorry, but currently Zhaoxin has not released any specs or
datasheets related
to the current patch. Zhaoxin CPUs are compatible with the x86 architecture,
particularly with Intel. For example, you can refer to the Intel SDM
(Software
Developer’s Manual). Regarding the current patch, except f
On Wed, Jun 26, 2024 at 12:44:29AM +0200, Maciej S. Szmigiero wrote:
> On 25.06.2024 19:25, Peter Xu wrote:
> > On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote:
> > > Hi Peter,
> >
> > Hi, Maciej,
> >
> > >
> > > On 23.06.2024 22:27, Peter Xu wrote:
> > > > On Tue, Jun 18, 20
On Tue, 25 Jun 2024 19:18, Zhao Liu wrote:
Hi Manos,
On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote:
Date: Wed, 19 Jun 2024 23:14:02 +0300
From: Manos Pitsidianakis
Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with
x-pl011-rust in arm virt machine
X-Maile
A following patch will add a new MMIO region for nested SMMU instances.
This macro will be repeatedly used to set offsets and MMIO sizes in both
virt and virt-acpi-build.
Signed-off-by: Nicolin Chen
---
hw/arm/virt.c | 2 +-
include/hw/arm/virt.h | 3 +++
2 files changed, 4 insertions(+
Hi all,
This is a draft solution adding multiple nested SMMU instances to VM.
The main goal of the series is to collect opinions, to figure out a
reasonable solution that would fit our needs.
I understood that there are concerns regarding this support, from our
previous discussion:
https://lore.k
Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
instance(s). Add a helper to read the sysfs for the number of instances.
Log them in a vms list using a new struct VirtNestedSmmu.
This will be used by a following patch to assign a passthrough device to
corresponding nested
Hi,
On Monday, June 24, 2024 5:06:42 PM GMT+5:30 Eugenio Perez Martin wrote:
> [...]
> > > > /* Shadow virtqueue to relay notifications */
> > > > typedef struct VhostShadowVirtqueue {
> > > >
> > > > +/* Virtio queue shadowing */
> > > > +VirtQueue *vq;
> > > > +
> > > > +/* Virtio
Hi Rajnesh,
On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.
This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and counter
On 6/21/24 8:40 PM, Cédric Le Goater wrote:
On 6/21/24 4:47 PM, Shivaprasad G Bhat wrote:
On 6/21/24 2:19 PM, Cédric Le Goater wrote:
Could you please describe the host/guest OS, hypervisor, processor
and adapter ?
Here is the environment info,
pSeries:
Host : Power10 PowerVM Lpar
Ke
On 2024/6/5 上午10:15, Jiaxun Yang wrote:
It was missed out in previous commit.
Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c | 347
1 file changed, 347 deletions(
Hi Salil and Igor,
On 6/26/24 9:51 AM, Salil Mehta wrote:
On Wed, Jun 5, 2024 at 3:03 PM Igor Mammedov mailto:imamm...@redhat.com>> wrote:
On Sun, 2 Jun 2024 18:03:05 -0400
"Michael S. Tsirkin" mailto:m...@redhat.com>> wrote:
> On Thu, May 30, 2024 at 12:42:33AM +0100, Salil Mehta
This patch corrects minor typographical errors to ensure the ASCII art
aligns with the explanations provided. Specifically, it fixes an
incorrect root port reference and removes redundant words.
Signed-off-by: Hyeongtak Ji
---
docs/system/devices/cxl.rst | 6 +++---
1 file changed, 3 insertions
On 2024-06-23 6:08 p.m., Richard Henderson wrote:
On 6/23/24 10:55, Richard Henderson wrote:
On 6/22/24 19:12, Brad Smith wrote:
+ if (sysctl(mib, 2, &isar0, &len, NULL, 0) != -1) {
+ if (ID_AA64ISAR0_ATOMIC(isar0) >= ID_AA64ISAR0_ATOMIC_IMPL)
+ info |= CPUINFO_LSE;
+ if (ID
On 2024-06-23 6:03 p.m., Richard Henderson wrote:
On 6/23/24 10:53, Richard Henderson wrote:
On 6/22/24 19:03, Brad Smith wrote:
util: fix building on OpenBSD/powerpc
Signed-off-by: Brad Smith
---
util/cpuinfo-ppc.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
John Snow writes:
> Eliminate the "Example" sections in QAPI doc blocks, converting them
> into QMP example code blocks. This is generally done in this patch by
> converting "Example:" or "Examples:" lines into ".. code-block:: QMP"
> lines.
[...]
> diff --git a/qapi/migration.json b/qapi/migra
You asked for a summary of my review findings. Here it is:
* PATCH 01: DO-NOT-MERGE, not reviewed
* PATCH 02, 05..07, 10..12: R-by or A-by
* PATCH 03: R-by with straightforward minor adjustments
* PATCH 04, 08: R-by with commit message and doc tweaks
* PATCH 09:
- Commit message tweaks
On Wed, Jun 26, 2024 at 11:22:46AM +1000, Alistair Francis wrote:
>
> On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote:
> >
> > Hi Alistair,
> >
> > IOPMP can applies all device. In this patch series, PCI devices on the
> > bridge
> > can connect to IOPMP by pci_setup_iommu(), but other devices
Hi Rajnesh,
On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.
This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable an
在 2024/6/22 4:44, Luck, Tony 写道:
So who actually cares about recovering poisoned volatile memory?
I'd like to understand more on how significant a use case this is.
Whilst I can conjecture that its an extreme case of wanting to avoid
loosing the ability to create 1GiB or larger pages due to po
Hi,
On 25/06/2024 13:28, Yuke Peng wrote:
According to Intel VT-d specification 5.1.4, CFI must be blocked when
Extended Interrupt Mode is enabled or Compatibility format interrupts
are disabled.
Signed-off-by: Yuke Peng
---
hw/i386/intel_iommu.c | 28
h
Hi Rajnesh,
On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depen
On Tue, Jun 4, 2024 at 2:42 PM Alvin Chang via wrote:
The `From` address is mangled here. It shows it was sent from the list
instead of your actual email address.
Do you mind looking into your email setup and see if you can fix it?
Alistair
>
> According to RISC-V Debug specification version 0
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