Re: [PATCH 0/4] Add support for Zhaoxin Yongfeng CPU model and other improvements

Hi EwanHai, On Tue, Jun 25, 2024 at 05:19:01AM -0400, EwanHai wrote: > Date: Tue, 25 Jun 2024 05:19:01 -0400 > From: EwanHai > Subject: [PATCH 0/4] Add support for Zhaoxin Yongfeng CPU model and other > improvements > X-Mailer: git-send-email 2.34.1 > > This patch series introduces support for

Re: [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed

On 6/25/24 05:41, Peter Maydell wrote: On Tue, 25 Jun 2024 at 06:09, Richard Henderson wrote: The last insns in this block, MLA and MLS, were converted with f80701cb44d, and this code should have been removed then. "MLA, MLS, SQDMULH, SQRDMULH, were converted with f80701cb44d and f80701cb44d

Re: [PATCH 13/13] target/arm: Delete dead code from disas_simd_indexed

On Tue, 25 Jun 2024 at 15:18, Richard Henderson wrote: > > On 6/25/24 05:41, Peter Maydell wrote: > > On Tue, 25 Jun 2024 at 06:09, Richard Henderson > > wrote: > >> > >> The last insns in this block, MLA and MLS, were converted > >> with f80701cb44d, and this code should have been removed then.

Re: [PATCH] tests/avocado: add hotplug_blk test

ping2 On 09.04.24 09:58, Vladimir Sementsov-Ogievskiy wrote: Introduce a test, that checks that plug/unplug of virtio-blk device works. (the test is developed by copying hotplug_cpu.py, so keep original copyright) Signed-off-by: Vladimir Sementsov-Ogievskiy -- Best regards, Vladimir

Re: [PATCH v3 14/15] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Tue, Jun 25, 2024 at 04:06:58PM +0200, Igor Mammedov wrote: > On Tue, 25 Jun 2024 17:59:33 +0530 > Sunil V L wrote: > > > On Tue, Jun 25, 2024 at 02:05:58PM +0200, Igor Mammedov wrote: > > > On Tue, 25 Jun 2024 13:19:59 +0200 > > > Igor Mammedov wrote: > > > > > > > On Fri, 21 Jun 2024 17:

[RFC PATCH] testing: restore some testing for i686

The commit 4f9a8315e6 (gitlab-ci.d/crossbuilds: Drop the i386 system emulation job) was a little too aggressive dropping testing for 32 bit system builds. Partially revert but using the debian-i686 cross build images this time as fedora has deprecated the 32 bit stuff. Reported-by: Richard Henders

[PATCH v4 11/16] meson.build: Add RISC-V to the edk2-target list

so that ACPI table test can be supported. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 97e00d6f59..b54b0463a4 100644 --- a/meson.build +++ b/

[PATCH v4 14/16] tests/qtest/bios-tables-test: Add empty ACPI data files for RISC-V

As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data files for RISC-V ACPI tables and add the entries in bios-tables-test-allowed-diff.h. Signed-off-by: Sunil V L Acked-by: Alistair Francis Reviewed-by: Igor Mammedov --- tests/data/acpi/riscv64/virt/APIC |

Re: [RFC PATCH] testing: restore some testing for i686

On 25/06/2024 16.54, Alex Bennée wrote: The commit 4f9a8315e6 (gitlab-ci.d/crossbuilds: Drop the i386 system emulation job) was a little too aggressive dropping testing for 32 bit system builds. FWIW: It was necessary at that point in time since we were constantly running out of CI minutes, an

[PATCH v4 13/16] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V

Update the list of supported architectures to include RISC-V. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov --- tests/data/acpi/rebuild-expected-aml.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/data/acpi/rebuild-expected-

Re: [PATCH 1/2] ui/cocoa: Add cursor composition

On Mon, 18 Mar 2024 at 08:59, Akihiko Odaki wrote: > The common pattern to implement accelerated cursor composition is to > replace the cursor and warp it so that the replaced cursor is shown at > the correct position on the guest display. Unfortunately, ui/cocoa > cannot do the same because warpi

[PATCH v4 06/16] tests/qtest/bios-tables-test.c: Add support for arch in path

Since machine name can be common for multiple architectures (ex: virt), add "arch" in the path to search for expected AML files. Since the AML files are still under old path, add support for searching with and without arch in the path. Signed-off-by: Sunil V L Acked-by: Alistair Francis Reviewed

Re: [PATCH 18/32] hw/sd: Add emmc_cmd_APP_CMD() handler

On 25/6/24 17:13, Cédric Le Goater wrote: On 6/25/24 5:04 PM, Philippe Mathieu-Daudé wrote: Hi Cédric, On 3/7/23 15:24, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater ---   hw/sd/sd.c | 6 ++   1 file changed, 6 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 5ff132139ea

[PATCH v4 15/16] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

Add basic ACPI table test case for RISC-V. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tabl

[PATCH v4 07/16] tests/qtest/bios-tables-test.c: Set "arch" for aarch64 tests

To search for expected AML files under ${arch}/${machine} path, set this field for AARCH64 related test cases. Signed-off-by: Sunil V L Acked-by: Alistair Francis Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c | 8 1 file changed, 8 insertions(+) diff --git a/tests/qte

Re: [PATCH 18/32] hw/sd: Add emmc_cmd_APP_CMD() handler

Hi Cédric, On 3/7/23 15:24, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater --- hw/sd/sd.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 5ff132139ea9..95cb46b87519 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2207,6 +2207,11 @@ static sd_rsp_

[PATCH v4 09/16] tests/data/acpi: Move x86 ACPI tables under x86/${machine} path

To support multiple architectures using same machine name, create x86 folder and move all x86 related AML files for each machine type inside. Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov --- tests/data/acpi/{ => x86}/microvm/APIC | Bin tests/data/acpi/{ => x86}/microvm/APIC

[RFC PATCH v3 2/2] tests/qtest: QTest example for RISC-V CSR register

Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov --- tests/qtest/meson.build | 2 + tests/qtest/riscv-csr-test.c | 85 2 files changed, 87 insertions(+) create mode 100644 tests/qtest/riscv-csr-test.c diff --git a

[RFC PATCH v3 0/2] Support RISC-V CSR read/write in Qtest environment

These patches add functionality for unit testing RISC-V-specific registers. The first patch adds a Qtest backend, and the second implements a simple test. --- v3: - Refactor, delete additions to libqos framework --- Ivan Klokov (2): target/riscv: Add RISC-V CSR qtest support tests/qtest: Q

[RFC PATCH v3 1/2] target/riscv: Add RISC-V CSR qtest support

The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov --- target/riscv/cpu.c | 14 +++ targe

[PATCH v4 12/16] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs

Update list of images supported in unpack_edk2_blobs to enable RISC-V ACPI table testing. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov --- pc-bios/meson.build | 2 ++ tests/qtest/meson.build | 3 +++ 2 files changed, 5 insertions(+) diff --git a/pc-bio

[PATCH v4 10/16] tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path

Same machine name can be used by different architectures. Hence, create aarch64 folder and move all aarch64 related AML files for virt machine inside. Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov --- tests/data/acpi/{ => aarch64}/virt/APIC | Bin .../data/acpi/{ => aarch64}/v

Re: [RFC PATCH v3 2/5] rust: add bindgen step as a meson dependency

> > > + # > WARNING: Project specifies a minimum meson_version '>=0.63.0' > > > but > > > + # > uses features which were added in newer versions: > > > + # > * 0.64.0: {'fs.copyfile'} > > > + # > * 1.0.0: {'dependencies arg in rust.bindgen', 'module rust as > > > stable mo

Re: linux-user cannot allocate stack memory on riscv64 host due to non-zero guest_base

On 6/25/24 04:37, Andreas Schwab wrote: When running qemu-riscv64 on a riscv64 host executing a ET_EXEC riscv64 binary it cannot allocate memory for the stack: $ qemu-riscv64 -d page ./hello.riscv64 host mmap_min_addr=0x1 Locating guest address space @ 0x3ee000 page layout changed following

[PATCH v4 01/16] hw/riscv/virt.c: Make block devices default to virtio

RISC-V virt is currently missing default type for block devices. Without this being set, proper backend is not created when option like -cdrom is used. So, make the virt board's default block device type be IF_VIRTIO similar to other architectures. We also need to set no_cdrom to avoid getting a d

[PATCH v2] target/riscv: Add support for machine specific pmu's events

Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have different behavior. Signed-off-by: Alexei

Re: [PATCH 18/32] hw/sd: Add emmc_cmd_APP_CMD() handler

On 6/25/24 5:32 PM, Philippe Mathieu-Daudé wrote: On 25/6/24 17:13, Cédric Le Goater wrote: On 6/25/24 5:04 PM, Philippe Mathieu-Daudé wrote: Hi Cédric, On 3/7/23 15:24, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater ---   hw/sd/sd.c | 6 ++   1 file changed, 6 insertions(+) dif

[PATCH v4 00/16] Add support for RISC-V ACPI tests

Currently, bios-table-test doesn't support RISC-V. This series enables the framework changes required and basic testing. Things like NUMA related test cases will be added later. This needs refactoring/renaming of ARM64 and x86 bios table tests. Importantly, the test cases now look for the expected

[PATCH v4 02/16] uefi-test-tools/UefiTestToolsPkg: Add RISC-V support

Enable building the test application for RISC-V with appropriate dependencies updated. Signed-off-by: Sunil V L Acked-by: Gerd Hoffmann Acked-by: Alistair Francis Acked-by: Igor Mammedov --- tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +- 1 file changed, 5 insertions(+

[PATCH v4 16/16] tests/qtest/bios-tables-test: Add expected ACPI data files for RISC-V

As per the step 5 in the process documented in bios-tables-test.c, generate the expected ACPI AML data files for RISC-V using the rebuild-expected-aml.sh script and update the bios-tables-test-allowed-diff.h. These are all new files being added for the first time. Hence, iASL diff output is not ad

[PATCH v8] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

kvm_riscv_handle_sbi() may return not supported return code to not trigger qemu abort with vendor-specific sbi. Add new error path to provide proper error in case of qemu_chr_fe_read_all() may not return sizeof(ch), because exactly zero just means we failed to read input, which can happen, so tell

[PATCH] target/riscv: Add support for machine specific pmu's events

Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have different behavior. Signed-off-by: Alexei

[PATCH v4 03/16] uefi-test-tools: Add support for python based build script

edk2-funcs.sh which is used in this Makefile, was removed in the commit c28a2891f3 ("edk2: update build script"). It is replaced with a python based script. So, update the Makefile and add the configuration file as required to support the python based build script. Signed-off-by: Sunil V L Acked-

Re: [PATCH 18/32] hw/sd: Add emmc_cmd_APP_CMD() handler

On 6/25/24 5:04 PM, Philippe Mathieu-Daudé wrote: Hi Cédric, On 3/7/23 15:24, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater ---   hw/sd/sd.c | 6 ++   1 file changed, 6 insertions(+) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 5ff132139ea9..95cb46b87519 100644 --- a/hw/sd/sd.c +++

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On Tue, Jun 25, 2024 at 12:38:50PM +0100, Joao Martins wrote: > On 24/06/2024 20:41, Peter Xu wrote: > > On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote: > >> @@ -2659,6 +2698,18 @@ qemu_loadvm_section_start_full(QEMUFile *f, > >> MigrationIncomingState *mis, > >> if (!check_

[PATCH v4 08/16] tests/qtest/bios-tables-test.c: Set "arch" for x86 tests

To search for expected AML files under ${arch}/${machine} path, set this field for X86 related test cases. Signed-off-by: Sunil V L Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c | 77 -- 1 file changed, 64 insertions(+), 13 deletions(-) diff --gi

Re: Help improve 32-bit testing

Richard Henderson writes: > Hiya, > > I've just discovered a 32-bit build issue that is probably 3 weeks old. > > While we still support 32-bit builds at all, I would request that we > improve our cross-i686 testing. For instance: we have cross-i686-user > and cross-i686-tci. There is some syst

[PATCH v4 04/16] tests/data/uefi-boot-images: Add RISC-V ISO image

To test ACPI tables, edk2 needs to be booted with a disk image having EFI partition. This image is created using UefiTestToolsPkg. The image is generated using tests/uefi-test-tools source. Signed-off-by: Sunil V L --- .../bios-tables-test.riscv64.iso.qcow2 | Bin 0 -> 16896 bytes test

[PATCH v4 05/16] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them

Existing AARCH64 virt test functions do not have AARCH64 in their name. To add RISC-V virt related test cases, better to rename existing functions to indicate they are ARM only. Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test.c

Re: [RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

On 2024/6/20 12:29 PM, Richard Henderson wrote: On 6/13/24 10:51, Max Chou wrote: This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store instructions by following items: * Get the loose bound of activate elements * P

Re: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with x-pl011-rust in arm virt machine

Hi Manos, On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote: > Date: Wed, 19 Jun 2024 23:14:02 +0300 > From: Manos Pitsidianakis > Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with > x-pl011-rust in arm virt machine > X-Mailer: git-send-email 2.44.0 > > Conveni

Re: [PATCH 1/1] prealloc: add truncate mode for prealloc filter

On 30.04.24 20:05, Denis V. Lunev via wrote: Preallocate filter allows to implement really interesting setups. Assume that we have * shared block device, f.e. iSCSI LUN, implemented with some HW device * clustered LVM on top of it * QCOW2 image stored inside LVM volume This allows very cheap cl

Re: [PATCH 1/2] block: allow commit to unmap zero blocks

On 26.05.24 22:29, Vincent Vanlaer wrote: Non-active block commits do not discard blocks only containing zeros, causing images to lose sparseness after the commit. This commit fixes that by writing zero blocks using blk_co_pwrite_zeroes rather than writing them out as any oother arbitrary data.

[PATCH 2/2] hw/cxl/events: Mark cxl-add-dynamic-capacity and cxl-release-dynamic-capcity unstable

Markus suggested that we make the unstable. I don't expect these interfaces to change because of their tight coupling to the Compute Express Link (CXL) Specification, Revision 3.1 Fabric Management API definitions which can only be extended in backwards compatible way. However, there seems little d

[PATCH qemu 0/2] hw/cxl: DCD tweaks and improvements.

These came from review after Michael Tsirkin had queued the DCD stuff on his QEMU tree. For reasons unrelated to this series, the pull request was rejected but I'm assuming Michael will send a fresh pull request soon. Hence this is based on top of qemu/master with the DCD patches from gitlab.com/

[PATCH 0/4] hw/usb/u2f-passthru: U2F keepalive fixes

Hello, The u2f-passthru device is currently broken for (at least) the Yubikey 5. (gitlab: https://gitlab.com/qemu-project/qemu/-/issues/2293) This patchset aims to fix the issue by properly handling the U2F keepalive response in the u2f-passthru device. I initially suspected the hidraw chardev h

[PATCH 3/4] hw/usb/u2f-passthru: Clean up code

Prepare for implementing the FIDO-U2F keepalive feature: Represent all u2fhid frames using one coherent structure, and make casts explicit. Signed-off-by: David Bouman --- hw/usb/u2f-passthru.c | 73 ++- 1 file changed, 44 insertions(+), 29 deletions(-)

[PATCH 2/4] hw/usb/u2f-passthru: Do not needlessly retain handle to hidraw chardev

The Linux kernel presumes a hidraw device to be "active" as long as an open handle to its character device exists, and during that time will actively poll its bus for new messages. The u2f-passthru device keeps an open handle to the hidraw character device for its entire lifetime, wasting power an

[PATCH 4/4] hw/usb/u2f-passthru: Implement FIDO U2FHID keep-alive

FIDO U2FHID features a keep-alive response command (code 0xbb). A keep-alive response signifies that the request is being processed and the transaction should not be closed yet. u2f-passthru does not recognize this command, and hence closes the transaction prematurely upon receiving it. This preve

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote: > Hi Peter, Hi, Maciej, > > On 23.06.2024 22:27, Peter Xu wrote: > > On Tue, Jun 18, 2024 at 06:12:18PM +0200, Maciej S. Szmigiero wrote: > > > From: "Maciej S. Szmigiero" > > > > > > This is an updated v1 patch series of the

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On 25/06/2024 15:53, Peter Xu wrote: > On Tue, Jun 25, 2024 at 12:38:50PM +0100, Joao Martins wrote: >> On 24/06/2024 20:41, Peter Xu wrote: >>> On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote: @@ -2659,6 +2698,18 @@ qemu_loadvm_section_start_full(QEMUFile *f, MigrationIn

[PATCH v2 07/13] target/arm: Convert BFDOT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 20 +--- 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8a0251f83c

[PATCH v2 00/13] target/arm: AdvSIMD conversion, part 2

Convert another hand-full of instructions, plus fixes for two issues that are related. r~ Richard Henderson (13): target/arm: Fix VCMLA Dd, Dn, Dm[idx] target/arm: Fix SQDMULH (by element) with Q=0 target/arm: Fix FJCVTZS vs flush-to-zero target/arm: Convert SQRDMLAH, SQRDMLSH to decode

[PATCH v2 01/13] target/arm: Fix VCMLA Dd, Dn, Dm[idx]

The inner loop, bounded by eltspersegment, must not be larger than the outer loop, bounded by elements. Cc: qemu-sta...@nongnu.org Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add (indexed)") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376 Reviewed-by: Peter May

[PATCH v2 06/13] target/arm: Convert SUDOT, USDOT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 3 +++ target/arm/tcg/translate-a64.c | 35 -- 2 files changed, 11 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode

[PATCH 1/2] hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity.

New DCD command definitions updated in response to review comments from Markus. - Used Cxl instead of CXLX for newly added types. - Expanded some abreviations in type names to be easier to read. - Additional documentation for some fields. - Replace slightly vague cxl r3.1 references with

[PATCH v2 10/13] target/arm: Add data argument to do_fp3_vector

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 52 +- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2697c4b305..57cdde008e 100

Re: [PATCH] include: move typeof_strip_qual to compiler.h, use it in QAPI_LIST_LENGTH()

On 6/25/24 04:18, Paolo Bonzini wrote: The typeof_strip_qual() is most useful for the atomic fetch-and-modify operations in atomic.h, but it can be used elsewhere as well. For example, QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a requirement. Move the macro to compi

[PATCH v2 09/13] target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 target/arm/tcg/translate-a64.c | 36 -- 2 files changed, 12 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode

[PATCH 1/4] hw/usb/u2f: Add `start` and `stop` callbacks to U2F key class

Preparation for improved u2f-passthru hidraw handle lifetimes: These callbacks can be implemented by the backing implementation, i.e. u2f-passthru or u2f-emulated. The start callback is invoked when the device receives an INTR IN, and the stop callback is invoked when the endpoint has been unlink

Re: [PATCH RFC 1/2] migration: abort when switchover limit exceeded

On Fri, Jun 21, 2024 at 07:32:20AM -0700, Elena Ufimtseva wrote: > Introduce capability switchover_abort and migration parameter switchover_limit > to allow for live migration abort when the source downtime exceeded by > switchover_limit. > > Signed-off-by: Elena Ufimtseva > --- > hw/core/machin

[PATCH v2 08/13] target/arm: Convert BFMLALB, BFMLALT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 + target/arm/tcg/translate-a64.c | 77 +- 2 files changed, 31 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode in

[PATCH v2 12/13] target/arm: Convert FCMLA to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 + target/arm/tcg/translate-a64.c | 238 ++--- 2 files changed, 74 insertions(+), 170 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f330919851..223eac3cac

Re: [PATCH 3/3] ui/cocoa: Adds support for mouse cursors

On Tue, 11 Jun 2024 at 09:36, Akihiko Odaki wrote: > > […] I also > > definitely think host cursor integration is useful and valuable, at > > least in absolute pointing mode - for example, when the host system is > > itself being remote controlled, and also to avoid the cursor being > > cropped ne

Re: [RFC PATCH v3 2/5] rust: add bindgen step as a meson dependency

On Tue, 25 Jun 2024 19:00, Zhao Liu wrote: [snip] This is for future-proofing the Rust integration in general. I haven't been able to compile under macos yet because bindgen cannot find the system clang header. I also don't have a windows pc to test it on. But it should work theoretically unde

[PATCH v2 05/13] target/arm: Convert SDOT, UDOT to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 + target/arm/tcg/translate-a64.c | 54 ++ 2 files changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decod

[PATCH v2 11/13] target/arm: Convert FCADD to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/a64.decode | 3 +++ target/arm/tcg/translate-a64.c | 33 ++--- 2 files changed, 13 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode i

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On Tue, Jun 25, 2024 at 10:53:41AM -0400, Peter Xu wrote: > Then the question is how should we suggest the user to specify these two > parameters. > > The cover letter used: > > migrate_set_parameter downtime-limit 300 > migrate_set_parameter switchover-limit 10 What this means is that in pr

[PATCH v2 03/13] target/arm: Fix FJCVTZS vs flush-to-zero

Input denormals cause the Javascript inexact bit (output to Z) to be set. Cc: qemu-sta...@nongnu.org Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/ar

Re: [PATCH] include: move typeof_strip_qual to compiler.h, use it in QAPI_LIST_LENGTH()

On Tue, 25 Jun 2024 14:18, Paolo Bonzini wrote: The typeof_strip_qual() is most useful for the atomic fetch-and-modify operations in atomic.h, but it can be used elsewhere as well. For example, QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a requirement. Move the macr

[PATCH v2 13/13] target/arm: Delete dead code from disas_simd_indexed

MLA, MLS, SQDMULH, SQRDMULH, were converted with 8db93dcd3def and f80701cb44d, and this code should have been removed then. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 93 -- 1 file changed, 93 deletions(-) diff --git a/target/arm/tcg/tr

[PATCH v2 04/13] target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h| 10 ++ target/arm/tcg/a64.decode | 16 +++ target/arm/tcg/translate-a64.c | 206 + target/arm/tcg/vec_helper.c| 72 4 files changed, 180 inser

[PATCH v2 02/13] target/arm: Fix SQDMULH (by element) with Q=0

The inner loop, bounded by eltspersegment, must not be larger than the outer loop, bounded by elements. Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 24 1 file changed, 16 insertions(+), 8 delet

Re: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with x-pl011-rust in arm virt machine

On Tue, 25 Jun 2024 at 20:15, Daniel P. Berrangé wrote: > > On Wed, Jun 26, 2024 at 12:18:55AM +0800, Zhao Liu wrote: > > Hi Manos, > > > > On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote: > > > Date: Wed, 19 Jun 2024 23:14:02 +0300 > > > From: Manos Pitsidianakis > > > Subjec

Re: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with x-pl011-rust in arm virt machine

On Wed, Jun 26, 2024 at 12:18:55AM +0800, Zhao Liu wrote: > Hi Manos, > > On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote: > > Date: Wed, 19 Jun 2024 23:14:02 +0300 > > From: Manos Pitsidianakis > > Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with > > x-pl011

Re: [PULL 00/42] vfio queue

On 6/24/24 14:24, Cédric Le Goater wrote: The following changes since commit d89b64beea65f77c21a553cb54cb97b75c53dc21: Merge tag 'pull-request-2024-06-24' ofhttps://gitlab.com/thuth/qemu into staging (2024-06-24 11:57:11 -0700) are available in the Git repository at: https://github.com

Re: [PATCH 1/2] migration: Implement dirty ring

On Tue, Jun 25, 2024 at 08:10:23PM +0900, Shota Imamura wrote: > Dear Peter Xu, > > Thank you for your feedback. > > > It looks like this patch will introduce a ring but still it keeps the > > bitmaps around. > > > > Could you elaborate your motivation of this work? It’ll be interesting to > > kn

Re: [RFC PATCH v3 1/5] build-sys: Add rust feature option

On Mon, 24 Jun 2024 20:14, Paolo Bonzini wrote: Yes, I agree. However, considering we haven't even checked the situation with what language features are required by any idiomatic bindings vs the 1.63 version that we need to support for Debian, I think it's a bit premature to make it mandatory.

Re: [PATCH v2] target/riscv: Add support for machine specific pmu's events

On 6/25/24 07:46, Alexei Filippov wrote: Was added call backs for machine specific pmu events. Simplify monitor functions by adding new hash table, which going to map counter number and event index. Was added read/write callbacks which going to simplify support for events, which expected to have

Re: [PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext.

On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote: > > This series enables Control Transfer Records extension support on riscv > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > The Extension has been stable and the latest release can be found here [0] Can you be expli

Re: [PATCH v3 2/6] target/riscv: Introduce extension implied rule helpers

On Tue, Jun 25, 2024 at 9:47 PM wrote: > > From: Frank Chang > > Introduce helpers to enable the extensions based on the implied rules. > The implied extensions are enabled recursively, so we don't have to > expand all of them manually. This also eliminates the old-fashioned > ordering requiremen

Re: [PATCH V12 0/8] Add architecture agnostic code to support vCPU Hotplug

Hi Igor, On Wed, Jun 5, 2024 at 3:03 PM Igor Mammedov wrote: > On Sun, 2 Jun 2024 18:03:05 -0400 > "Michael S. Tsirkin" wrote: > > > On Thu, May 30, 2024 at 12:42:33AM +0100, Salil Mehta wrote: > > > Virtual CPU hotplug support is being added across various > architectures[1][3]. > > > This ser

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On Tue, Jun 25, 2024 at 05:31:19PM +0100, Joao Martins wrote: > The device-state multifd scaling is a take on improving switchover phase, > and we will keep improving it whenever we find things... but the That'll be helpful, thanks. Just a quick note that "reducing downtime" is a separate issue c

Re: [PATCH v3 1/6] target/riscv: Introduce extension implied rules definition

On Tue, Jun 25, 2024 at 9:47 PM wrote: > > From: Frank Chang > > RISCVCPUImpliedExtsRule is created to store the implied rules. > 'is_misa' flag is used to distinguish whether the rule is derived > from the MISA or other extensions. > 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it

Re: [PATCH v2 2/6] target/riscv: Add Control Transfer Records CSR definitions.

On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote: > > The Control Transfer Records (CTR) extension provides a method to > record a limited branch history in register-accessible internal chip > storage. > > This extension is similar to Arch LBR in x86 and BRBE in ARM. > The Extension has been s

[PATCH RFCv1 07/10] hw/arm/virt: Bypass iommu for default PCI bus

Now, all passthrough devices that should benefit from the nested SMMUv3 feature are assigned to dedicated pxb buses. So, the default PCI bus can be only used by emulated devices. In theory, these emualted devices can be still attached to an emualted SMMUv3 instance, yet there is no gain doing that

Re: [PATCH v3 0/6] Introduce extension implied rules

On Tue, Jun 25, 2024 at 9:48 PM wrote: > > From: Frank Chang > > Currently, the implied extensions are enabled and checked in > riscv_cpu_validate_set_extensions(). However, the order of enabling the > implied extensions must follow a strict sequence, which is error-prone. > > This patchset intro

[PATCH RFCv1 09/10] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes

There can be multiple PCI buses behind different SMMU nodes. And each pair should be associated in the IORT table too when building the ID mappings. Create multiple SMMU nodes if needed, store their offsets in an array. Signed-off-by: Nicolin Chen --- hw/arm/virt-acpi-build.c | 36 +

[PATCH RFCv1 06/10] hw/arm/virt: Assign vfio-pci devices to nested SMMUs

With iommu=nested-smmuv3, there could be multiple nested SMMU instances in the vms. A passthrough device must to look up for its iommu handler in its sysfs node, and then link to the nested SMMU instance created for the same iommu handler. This isn't easy to do. Add an auto-assign piece after all

[PATCH RFCv1 08/10] hw/arm/virt-acpi-build: Handle reserved bus number of pxb buses

Each pxb bus created for a nested SMMU has a reserved bus number, allowing a hotplug device to attach to the bus in a later stage. Read it out to apply to the id_count calculation. Signed-off-by: Nicolin Chen --- hw/arm/virt-acpi-build.c | 28 include/hw/arm/virt.h

Re: [PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes

On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > Extend memory transaction attributes with process identifier to allow > per-request address translation logic to use requester_id / process_id > to identify memory mapping (e.g. enabling IOMMU w/ PASID tra

Re: [PATCH v4 07/14] test/qtest: add riscv-iommu-pci tests

On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza wrote: > > To test the RISC-V IOMMU emulation we'll use its PCI representation. > Create a new 'riscv-iommu-pci' libqos device that will be present with > CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this > device will on

Re: [PATCH v4 14/14] docs/specs: add riscv-iommu

On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza wrote: > > Add a simple guideline to use the existing RISC-V IOMMU support we just > added. > > This doc will be updated once we add the riscv-iommu-sys device. > > Signed-off-by: Daniel Henrique Barboza > --- > docs/specs/index.rst |

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote: > During live migration, receive current downtime from source > and start a downtime timer. When the destination dowtime > and added source downtime exceeds downtime limit for more > than switchover limit, abort live migration on dest

Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote: > > Hi Alistair, > > IOPMP can applies all device. In this patch series, PCI devices on the bridge > can connect to IOPMP by pci_setup_iommu(), but other devices need change their > memory access address space from system memory to IOPMP by themse

[PATCH RFCv1 10/10] hw/arm/virt-acpi-build: Enable ATS for nested SMMUv3

For a nested SMMUv3, the ATS capaiblity is decided by the underlying HW, and then reflected in the IDR0 register of the vSMMU. The IORT on the other hand could allow it to be always enabled, relying on the guest-level SMMU kernel driver to disable ATS feature if the ATS bit isn't set in IDR0. Sig

[PATCH RFCv1 01/10] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding

From: Eric Auger To handle SMMUv3 nested stage support it is practical to expose the guest with reserved memory regions (RMRs) covering the IOVAs used by the host kernel to map physical MSI doorbells. Those IOVAs belong to [0x800, 0x810] matching MSI_IOVA_BASE and MSI_IOVA_LENGTH definit

Re: [PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h

On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > This header will be used by the RISC-V IOMMU emulation to be added > in the next patch. Due to its size it's being sent in separate for > an easier review. > > One thing to notice is that this header can b

[PATCH RFCv1 05/10] hw/arm/virt: Add VIRT_NESTED_SMMU

VIRT_SMMU can be used as an emulated SMMU, i.e. iommu=smmuv3. However, the MMIO space for VIRT_SMMU isn't large enough to accommodate multiple nested SMMUv3 instances. Add a new VIRT_NESTED_SMMU to separate MMIO space. Meanwhile, a nested SMMUv3 could only work with a vfio-pci device that is physi

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

On 25.06.2024 19:25, Peter Xu wrote: On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote: Hi Peter, Hi, Maciej, On 23.06.2024 22:27, Peter Xu wrote: On Tue, Jun 18, 2024 at 06:12:18PM +0200, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" This is an updated v1 pat

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