ASan detected a global-buffer-overflow error in the aspeed_gpio_read()
function. This issue occurred when reading beyond the bounds of the
reg_table.
To enhance the safety and maintainability of the Aspeed GPIO code, this commit
introduces a reg_table_size member to the AspeedGPIOClass structure.
Hi Philippe,
On Tue, Jun 18, 2024 at 10:34 PM Philippe Mathieu-Daudé
wrote:
> On 18/6/24 21:11, Zheyu Ma wrote:
> > Thanks for your useful advice!
> >
> > So how about report the issue and return:
>
> We might report the issue to the user, but there should
> be a way the hardware report the issu
On Tue, Jun 18, 2024 at 8:58 PM Sahil wrote:
>
> Hi,
>
> On Tuesday, June 18, 2024 11:48:34 PM GMT+5:30 Sahil Siddiq wrote:
> > [...]
> >
> > hw/virtio/vhost-shadow-virtqueue.c | 124 -
> > hw/virtio/vhost-shadow-virtqueue.h | 66 ++-
> > 2 files changed,
Signed-off-by: Guoyi Tu
---
docs/devel/multi-process.rst | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/docs/devel/multi-process.rst b/docs/devel/multi-process.rst
index 4ef539c0b0..223f878139 100644
--- a/docs/devel/multi-process.rst
+++ b/docs/devel/multi-process
On Wed, Jun 12, 2024 at 3:13 PM Philippe Mathieu-Daudé
wrote:
> Building qemu-system-mips configured with --without-default-devices:
>
> Undefined symbols for architecture arm64:
>"_qemu_semihosting_console_write", referenced from:
>_mips_semihosting in target_mips_tcg_sysemu_mips-semi
On Tue, Jun 18, 2024 at 04:05:36PM -0700, Richard Henderson wrote:
> On 6/18/24 15:46, Roman Kiryanov wrote:
> > @@ -2839,7 +2839,7 @@ static inline uint8_t
> > address_space_ldub_cached(MemoryRegionCache *cache,
> > {
> > assert(addr < cache->len);
> > if (likely(cache->ptr)) {
> >
Am 18.06.2024 um 23:24 hat Nir Soffer geschrieben:
> Set has_discard only when BDRV_O_UNMAP is not set. With this users that
> want to keep their images fully allocated can disable hole punching
> when writing zeros or discarding using:
>
>-drive file=thick.img,discard=off
>
> This change is
> -Original Message-
> From: qemu-devel-bounces+chen.zhang=intel@nongnu.org devel-bounces+chen.zhang=intel@nongnu.org> On Behalf Of Nabih
> Estefan
> Sent: Wednesday, June 19, 2024 1:25 AM
> To: peter.mayd...@linaro.org
> Cc: qemu-devel@nongnu.org; kft...@nuvoton.com; wuhao...@go
Hi Edgar,
From: Boddu, Sai Pavan
Sent: Friday, June 14, 2024 8:37 PM
To: Edgar E. Iglesias
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis
; Peter Maydell ; Iglesias,
Francisco
Subject: RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
Hi Edgar,
I examined -boot swi
Nabih Estefan writes:
> There is an extra `buf=` set that is not used by npcm-gmac. Remove it
> for coverity to be happy.
Have you go the coverity reference to include in the commit message?
>
> Signed-off-by: Nabih Estefan
> ---
> hw/net/npcm_gmac.c | 1 -
> 1 file changed, 1 deletion(-)
>
>
BootMode property sets user values into BOOT_MODE register, on hardware
these are derived from board switches.
Signed-off-by: Sai Pavan Boddu
---
hw/misc/zynq_slcr.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr
Added the supported device list and an example command.
Signed-off-by: Sai Pavan Boddu
---
docs/system/arm/xlnx-zynq.rst | 47 +++
docs/system/target-arm.rst| 1 +
2 files changed, 48 insertions(+)
create mode 100644 docs/system/arm/xlnx-zynq.rst
diff --git
Read boot-mode value as machine property and propagate that to
SLCR.BOOT_MODE register.
Signed-off-by: Sai Pavan Boddu
---
hw/arm/xilinx_zynq.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 7f7a3d23fbe..39f0
Add a way to update the boot-mode via machine properties.
Changes for V2:
Make boot-mode property work with string
Fixed few code style issues
Added zynq board doc.
Sai Pavan Boddu (3):
hw/misc/zynq_slcr: Add BootMode property
hw/arm/xilinx_zynq: Add boot-mode property
docs/syst
On Mon, 27 May 2024 20:46:29 +0530
Sunil V L wrote:
> On Mon, May 27, 2024 at 12:12:10PM +0200, Philippe Mathieu-Daudé wrote:
> > Hi Sunil,
> >
> > On 24/5/24 08:14, Sunil V L wrote:
> > > Since virt is a common machine name across architectures like ARM64 and
> > > RISC-V, move existing ARM64
On Fri, 24 May 2024 11:44:06 +0530
Sunil V L wrote:
> so that ACPI table test can be supported.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
> ---
> meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/meson.build
On Fri, 24 May 2024 11:44:04 +0530
Sunil V L wrote:
> Since virt machine is common for multiple architectures, add "arch" in
> the path to search expected AML files. Since the AML files are still
> under old path, support both by searching with and without arch in the
> path.
>
> Signed-off-by:
On Wed, Jun 19, 2024 at 11:17:43AM +0200, Igor Mammedov wrote:
> On Mon, 27 May 2024 20:46:29 +0530
> Sunil V L wrote:
>
> > On Mon, May 27, 2024 at 12:12:10PM +0200, Philippe Mathieu-Daudé wrote:
> > > Hi Sunil,
> > >
> > > On 24/5/24 08:14, Sunil V L wrote:
> > > > Since virt is a common mac
在 2024/6/19 7:35, Dave Jiang 写道:
On 6/18/24 9:53 AM, Shiyang Ruan wrote:
Background:
Since CXL device is a memory device, while CPU consumes a poison page of
CXL device, it always triggers a MCE by interrupt (INT18), no matter
which-First path is configured. This is the first report. Then
Fix coverity defect: DIVIDE_BY_ZERO.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index b6876b4862..d14a46df6f 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@
change from v1:
aspeed/soc: coverity defect: DIVIDE_BY_ZERO
aspeed/sdmc: coverity defect: Control flow issues (DEADCODE)
Jamin Lin (2):
aspeed/soc: fix coverity issue
aspeed/sdmc: fix coverity issue
hw/arm/aspeed_ast27x0.c | 6 ++
hw/misc/aspeed_sdmc.c | 1 -
2 files changed, 6 inserti
Fix coverity defect: Control flow issues (DEADCODE)
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 93e2e29ead..94eed9264d 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -
On Fri, 24 May 2024 11:44:07 +0530
Sunil V L wrote:
> Update list of images supported in unpack_edk2_blobs to enable RISC-V
> ACPI table testing.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
> ---
> pc-bios/meson.build | 2 ++
> tests/qtest/me
On Fri, 24 May 2024 11:44:08 +0530
Sunil V L wrote:
> Update the list of supported architectures to include RISC-V.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
> ---
> tests/data/acpi/rebuild-expected-aml.sh | 5 +++--
> 1 file changed, 3 inserti
On Fri, 24 May 2024 11:44:09 +0530
Sunil V L wrote:
> As per process documented (steps 1-3) in bios-tables-test.c, add empty
> AML data files for RISC-V ACPI tables and add the entries in
> bios-tables-test-allowed-diff.h.
>
> Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
> ---
> test
Pierrick Bouvier writes:
> On 6/18/24 02:53, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> On 6/17/24 13:56, Dr. David Alan Gilbert wrote:
* Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote:
> On 6/14/24 15:00, Dr. David Alan Gilbert wrote:
>> * Pierrick Bouvier (pierri
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/net/ftgmac100.c
Signed-off-by: Jamin Lin
---
hw/net/ftgmac100.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 74b6c3d
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Normal Priority Transmit Ring Base Address Register High(0x17C)",
"High Priority Transmit Ring Base Address Register High(0x184)" and
"Receive Ring Base Addr
change from v1:
- ftgmac100
- fix coding style
- support 64 bits dma dram address for AST2700
Jamin Lin (2):
hw/net:ftgmac100: fix coding style
hw/net:ftgmac100: support 64 bits dma dram address for AST2700
hw/net/ftgmac100.c | 83 ++
include/hw/
On 26/4/23 12:59, Paolo Bonzini wrote:
On 4/25/23 15:38, Thomas Huth wrote:
- CPU types have different suffixes between the -x86_64 and -i386
variant (see TYPE_X86_CPU in cpu-qom.h) ... do we need to care
about this in the new qemu-system-i386 symlink run mode?
- The code in target/i386/t
On 19/6/24 07:54, Thomas Huth wrote:
Beside migration-test.c, there is nowadays migration-helpers.[ch],
too, so update the entry in the migration section to also cover these
files now.
While we're at it, exclude these files in the common qtest section,
since the migration test is well covered by
On Fri, 24 May 2024 11:44:10 +0530
Sunil V L wrote:
> Add basic ACPI table test case for RISC-V.
>
> Signed-off-by: Sunil V L
> ---
> tests/qtest/bios-tables-test.c | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qte
On Tue, Jun 18, 2024 at 8:19 PM Sahil Siddiq wrote:
>
> This is the first patch in a series to add support for packed
> virtqueues in vhost_shadow_virtqueue. This patch implements the
> insertion of available buffers in the descriptor area. It takes
> into account descriptor chains, but does not c
On 19/6/24 00:45, Roman Kiryanov wrote:
to use the QEMU headers with a C++ compiler.
Google-Bug-Id: 331190993
Change-Id: Ic4e49b9c791616bb22c973922772b0494706092c
Signed-off-by: Roman Kiryanov
---
include/exec/memory.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/i
On 19/6/24 00:45, Roman Kiryanov wrote:
to use the QEMU headers with a C++ compiler.
Google-Bug-Id: 331190993
Change-Id: I785f2e65d192287f1f964d2840131b653755648c
Signed-off-by: Roman Kiryanov
---
include/exec/memop.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Phili
On 18/6/24 22:32, Richard Henderson wrote:
On 6/18/24 13:15, Philippe Mathieu-Daudé wrote:
On 18/6/24 22:06, Richard Henderson wrote:
On 6/18/24 08:59, Philippe Mathieu-Daudé wrote:
The following changes since commit
900536d3e97aed7fdd9cb4dadd3bf7023360e819:
Merge tag 'dirtylimit-dirtyrat
On 19/6/24 12:40, Philippe Mathieu-Daudé wrote:
On 19/6/24 00:45, Roman Kiryanov wrote:
to use the QEMU headers with a C++ compiler.
Google-Bug-Id: 331190993
I searched for this on
https://developers.google.com/issue-tracker/concepts/searches but no
hit, is this public information?
Chang
Thomas Huth writes:
> Beside migration-test.c, there is nowadays migration-helpers.[ch],
> too, so update the entry in the migration section to also cover these
> files now.
> While we're at it, exclude these files in the common qtest section,
> since the migration test is well covered by the mig
From: Roman Kiryanov
Make the MemOp enum cast explicit to use the QEMU
headers with a C++ compiler.
Signed-off-by: Roman Kiryanov
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240618224528.878425-1-r...@google.com>
Signed-off-by: Philippe Mathieu-Daudé
---
d/qemu.git tags/misc-20240619
for you to fetch changes up to fc0870c180872d0f40e63507cc6bf8565ffd8d98:
exec: Make the MemOp enum cast explicit (2024-06-19 12:52:21 +0200)
Spurious warning (3 times):
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
Deliberately ign
> On 19 Jun 2024, at 11:16, Kevin Wolf wrote:
>
> Am 18.06.2024 um 23:24 hat Nir Soffer geschrieben:
>> Set has_discard only when BDRV_O_UNMAP is not set. With this users that
>> want to keep their images fully allocated can disable hole punching
>> when writing zeros or discarding using:
>>
>
On Wed, Jun 19, 2024 at 11:16 AM Sai Pavan Boddu
wrote:
> Added the supported device list and an example command.
>
>
Thanks Sai!
You need to add an entry in the Xilinx Zynq section of the MAINTAINERS
file, e.g:
F: docs/system/arm/xlnx-zynq.rst
I would also list the supported boot-mode values i
On Fri, 24 May 2024 11:44:11 +0530
Sunil V L wrote:
> As per the step 5 in the process documented in bios-tables-test.c,
> generate the expected ACPI AML data files for RISC-V using the
> rebuild-expected-aml.sh script and update the
> bios-tables-test-allowed-diff.h.
>
> These are all new files
Treat it as a MIPS64 machine.
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index d0703ea279d..3669eec86e5 100755
--- a/configure
+++ b/configure
@@ -452,7 +452,7 @@ case "$cpu" in
linux_arch=loongarch
John Snow writes:
> Change get_doc_indented() to preserve indentation on all subsequent text
> lines, and create a compatibility dedent() function for qapidoc.py to
> remove that indentation. This is being done for the benefit of a new
Suggest "remove indentation the same way get_doc_indented()
John Snow writes:
> If a comment immediately follows a doc block, the parser doesn't ignore
> that token appropriately. Fix that.
>
> e.g.
>
>> ##
>> # = Hello World!
>> ##
>>
>> # I'm a comment!
>
> will break the parser, because it does not properly ignore the comment
> token if it immediately
John Snow writes:
> Sphinx does not like sections without titles, because it wants to
> convert every section into a reference. When there is no title, it
> struggles to do this and transforms the tree inproperly.
>
> Depending on the rST used, this may result in an assertion error deep in
> the
John Snow writes:
> The new QMP documentation generator wants to parse all examples as
> "QMP". We have an existing QMP lexer in docs/sphinx/qmp_lexer.py (Seen
> in-use here: https://qemu-project.gitlab.io/qemu/interop/bitmaps.html)
> that allows the use of "->", "<-" and "..." tokens to denote Q
John Snow writes:
> Transactions have the only instance of an Errors section that isn't a
> rST list; turn it into one.
>
> Signed-off-by: John Snow
Let;s explain the "why" a bit more clearly. Maybe
qapi: Nail down convention that Errors sections are lists
By unstated convention, Err
John Snow writes:
> Where I've noticed, rephrase the note to read more fluently.
>
> Signed-off-by: John Snow
> ---
> qapi/block-core.json | 4 ++--
> qga/qapi-schema.json | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/block-core.json b/qapi/block-core.json
> i
John Snow writes:
> Generally, surround command-line options with ``literal`` markup to help
> it stand out from prose in rendered HTML, and add cross-references to
> replace "see also" messages.
>
> References to types, values, and other QAPI definitions are not yet
> adjusted here; they will be
On Wed, Jun 19, 2024 at 11:16 AM Sai Pavan Boddu
wrote:
> BootMode property sets user values into BOOT_MODE register, on hardware
> these are derived from board switches.
>
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/misc/zynq_slcr.c | 22 ++
Merge gdbstub64.c in gdbstub.c and remove uses of
target specific TARGET_AARCH64 definition.
Small step toward single ARM/Aarch64 binary.
Philippe Mathieu-Daudé (2):
target/arm: Merge gdbstub64.c within gdbstub.c
target/arm: Always build Aarch64 gdbstub helpers
target/arm/cpu.h | 8 +
On 19/06/2024 13.46, Paolo Bonzini wrote:
Treat it as a MIPS64 machine.
Where did you encounter it?
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index d0703ea279d..3669eec86e5 100755
--- a/configure
++
In order to have a single binary for ARM and Aarch64,
always build Aarch64 gdbstub support.
Since arm_cpu_register_gdb_regs_for_features() checks
on arm_feature(env, ARM_FEATURE_AARCH64), the Aarch64
gdb registers won't be registered on 32-bit ARM.
There should be no functional changes.
Signed-of
John Snow writes:
> We do not need a dedicated section for notes. By eliminating a specially
> parsed section, these notes can be treated as normal rST paragraphs in
> the new QMP reference manual, and can be placed and styled much more
> flexibly.
>
> Convert all existing "Note" and "Notes" sect
Simple code movement adding #ifdef'ry on TARGET_AARCH64.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/gdbstub.c | 363 ++
target/arm/gdbstub64.c | 383 -
target/arm/meson.build | 1 -
3 files changed, 363 ins
John Snow writes:
> The double-colon synax is rST formatting that precedes a literal code
> block. We do not want to capture these as QAPI-specific sections.
>
> Coerce blocks that start with e.g. "Example::" to be parsed as untagged
> paragraphs instead of special tagged sections.
>
> Signed-off
On Wed, Jun 19, 2024 at 11:16 AM Sai Pavan Boddu
wrote:
> Read boot-mode value as machine property and propagate that to
> SLCR.BOOT_MODE register.
>
>
Hi Sai,
It seems a little odd to have -machine boot-mode and -boot. Perhaps someone
else has a better idea how this could be done?
Anyway, I'm
Hi Nicolin,
On 6/19/24 02:17, Nicolin Chen wrote:
> Both the other two callers of build_iort_id_mapping() just directly pass
> in the IORT_NODE_OFFSET macro. Keeping a "const uint32_t" local variable
> storing the same value doesn't have any gain.
>
> Simplify this by replacing the only place usi
In e820_add_entry() the e820_table is reallocated with g_renew() to make
space for a new entry. However, fw_cfg_arch_create() just uses the
existing e820_table pointer. This leads to a use-after-free if anything
adds a new entry after fw_cfg is set up.
Shift the addition of the etc/e820 file to th
John Snow writes:
> We do not need a dedicated section for notes. By eliminating a specially
> parsed section, these notes can be treated as normal rST paragraphs in
> the new QMP reference manual, and can be placed and styled much more
> flexibly.
>
> Convert all existing "Note" and "Notes" sect
John Snow writes:
> Eliminate the "Example" sections in QAPI doc blocks, converting them
> into QMP example code blocks. This is generally done in this patch by
> converting "Example:" or "Examples:" lines into ".. code-block:: QMP"
> lines.
>
> The old "Example:" or "Examples:" syntax is now cau
Signed-off-by: Hyeongtak Ji
---
docs/system/devices/cxl.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index 10a0e9bc9ff4..e2497e6a098b 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.r
Hi.
Pipewire feature is working great, but I haven't found a way to get Qemu
to re-connect after a user runs `systemctl --user restart pipewire` for
instance.
Qemu will simply continue, without sound output until restarted.
//Anton
On Wed, 19 Jun 2024 at 11:44, Philippe Mathieu-Daudé wrote:
>
> On 18/6/24 22:32, Richard Henderson wrote:
> > On 6/18/24 13:15, Philippe Mathieu-Daudé wrote:
> >> On 18/6/24 22:06, Richard Henderson wrote:
> >>> On 6/18/24 08:59, Philippe Mathieu-Daudé wrote:
> The following changes since co
On Wed, Jun 19, 2024 at 2:49 PM Thomas Huth wrote:
>
> On 19/06/2024 13.46, Paolo Bonzini wrote:
> > Treat it as a MIPS64 machine.
>
> Where did you encounter it?
It is handled by "config.sub" (the GNU script to canonicalize target
triples). and is also in the list produced by "rustc --print
targ
I was wondering why avocado tests passed with firmware which crashes
when anyone else is using it.
Turned out that amount of cores matters. Have to find out why still.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 2 --
1 file changed, 2 deletions(-)
diff --g
On Wed, Jun 19, 2024 at 07:54:47AM +0200, Thomas Huth wrote:
> Beside migration-test.c, there is nowadays migration-helpers.[ch],
> too, so update the entry in the migration section to also cover these
> files now.
> While we're at it, exclude these files in the common qtest section,
> since the mi
Hi Nicolin,
On 6/18/24 23:11, Nicolin Chen wrote:
> It's observed that Linux kernel booting with the VM reports a "conflicting
> mapping for input ID" FW_BUG.
>
> The IORT doc defines "Number of IDs" to be "the number of IDs in the range
> minus one", while virt-acpi-build.c simply stores the num
Hi,
This series is mainly to addresss Igor's comment about if one check in
host-cache-info could be removed [1], i.e., whether Guest's cache
topology should be self-consistent (able to correspond to Guest's CPU
topology level, as we currently do with the Guest cache topo).
I originally thought (i
The host-cache-info needs the check to ensure the valid maximum
addressable thread IDs.
We don't need to adjust the information in this one field for all cache
topology cases by default, even though Host's cache topology may not
correspond to Guest's CPU topology level.
For example, when a Geust
The CPUID[4].EAX[bits 25:14] encodes the "maximum number of addressable
IDs for logical processors", which value may be different with the
actual number of threads.
For example, there's a Guest with the topology like: 3 threads per core
and 3 cores per package. Its maximum ids for package level is
Hexadecimal mask is more intuitive comparing to decimal.
Therefore convert the mask of bits 00-04 to hexadecimal value.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 365852cb99e1..c4d
Hi maintainers,
Per my communication with Markus, it seems this renaming matches the
"local consistency" principle in (include/hw/boards.h). :-)
So do you think this change is acceptable?
Thanks,
Zhao
On Mon, May 27, 2024 at 09:18:37PM +0800, Zhao Liu wrote:
> Date: Mon, 27 May 2024 21:18:37 +0
Migration of a s390x guest with TCG was long known to be very unstable,
so the tests in tests/qtest/migration-test.c are disabled if running
with TCG instead of KVM.
Nicholas Piggin did a great analysis of the problem:
"The flic pending state is not migrated, so if the machine is migrated
while
On 19/06/2024 16.49, Zhao Liu wrote:
Hi maintainers,
Per my communication with Markus, it seems this renaming matches the
"local consistency" principle in (include/hw/boards.h). :-)
So do you think this change is acceptable?
I don't care too much, both ways of naming look acceptable to me...
On 6/19/24 02:49, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/18/24 02:53, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/17/24 13:56, Dr. David Alan Gilbert wrote:
* Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote:
On 6/14/24 15:00, Dr. David Alan Gilbert wrote:
* Pierrick
Dmitry Osipenko writes:
> From: Antonio Caggiano
>
> Support BLOB resources creation, mapping and unmapping by calling the
> new stable virglrenderer 0.10 interface. Only enabled when available and
> via the blob config. E.g. -device virtio-vga-gl,blob=true
>
>
> #if VIRGL_VERSION_MAJOR >= 1
The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.
This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here
https://github.com/ri
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.c.inc | 5 -
2 files changed, 6 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depends on couple of other extensions:
1. S[m|s]csrind : The ind
This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.
This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and counter overflow interrupts.
Signed-off-by: Rajnesh Kanwal
---
t
CTR entries are accessed using ctrsource, ctrtarget and ctrdata
registers using smcsrind/sscsrind extension. This commits extends
the csrind extension to support CTR registers.
ctrsource is accessible through xireg CSR, ctrtarget is accessible
through xireg1 and ctrdata is accessible through xireg
CTR extension adds a new instruction sctrclr to quickly
clear the recorded entries buffer.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 7
target/riscv/helper.h | 1 +
target
This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
sctrdepth CSRs handling.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_cfg.h | 2 +
target/riscv/csr.c | 128 +
3 files changed, 135 insertions(+)
19.06.2024 18:27, Alex Bennée пишет:
> Dmitry Osipenko writes:
>
>> From: Antonio Caggiano
>>
>> Support BLOB resources creation, mapping and unmapping by calling the
>> new stable virglrenderer 0.10 interface. Only enabled when available and
>> via the blob config. E.g. -device virtio-vga-gl,bl
16.06.2024 12:23, Akihiko Odaki пишет:
...
>> #endif
>> +#if VIRGL_VERSION_MAJOR >= 1
>> +typedef enum {
>> + HOSTMEM_MR_MAPPED,
>
> HOSTMEM_MR_MAPPED is no longer used.
Good catch
--
Best regards,
Dmitry
On 19/6/24 13:46, Paolo Bonzini wrote:
Treat it as a MIPS64 machine.
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 19/6/24 08:49, Zheyu Ma wrote:
Hi Andrew,
On Wed, Jun 19, 2024 at 1:58 AM Andrew Jeffery
mailto:and...@codeconstruct.com.au>> wrote:
Hello Zheyu Ma,
On Tue, 2024-06-18 at 15:09 +0200, Zheyu Ma wrote:
> Added bounds checking in the aspeed_gpio_read() and
aspeed_gpio_write(
Hello Cedric,
Thank You for reviewing this patch series.
Regards,
Chalapathi
On 18-06-2024 21:18, Cédric Le Goater wrote:
Hello Chalapathi,
On 6/17/24 6:54 PM, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeprom
On 6/19/24 07:34, Richard Henderson wrote:
First silly question: how much of this is boiler plate that gets moved
the moment that the second rust subdirectory is added?
If my suggestion at
https://lore.kernel.org/qemu-devel/CABgObfaP7DRD8dbSKNmUzhZNyxeHWO0MztaW3_EFYt=vf6s...@mail.gmail.com/
w
On 6/11/24 03:33, Manos Pitsidianakis wrote:
+++ b/scripts/cargo_wrapper.py
@@ -0,0 +1,211 @@
+#!/usr/bin/env python3
+# Copyright (c) 2020 Red Hat, Inc.
+# Copyright (c) 2023 Linaro Ltd.
+#
+# Authors:
+# Manos Pitsidianakis
+# Marc-André Lureau
+#
+# This work is licensed under the terms of t
On Wed, Jun 19, 2024 at 06:43:01PM +0200, Paolo Bonzini wrote:
> On 6/19/24 07:34, Richard Henderson wrote:
> > First silly question: how much of this is boiler plate that gets moved
> > the moment that the second rust subdirectory is added?
>
> If my suggestion at
> https://lore.kernel.org/qemu-
On Wed, Jun 19, 2024, 2:28 AM Markus Armbruster wrote:
> John Snow writes:
>
> > In a forthcoming series that adds a new QMP documentation generator, it
> > will be helpful to have a linting baseline. However, there's no need to
> > shuffle around the deck chairs too much, because most of this c
Il mer 19 giu 2024, 18:54 Daniel P. Berrangé ha
scritto:
> >build/
> > rust/
> >.cargo/
> > config.toml # generated by configure or meson.build
> >Cargo.toml # workspace generated by configure or meson.build
> >Cargo.lock # can be either linke
On Wed, Jun 19, 2024, 9:20 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Eliminate the "Example" sections in QAPI doc blocks, converting them
> > into QMP example code blocks. This is generally done in this patch by
> > converting "Example:" or "Examples:" lines into ".. code-block:: QMP
On Wed, 19 Jun 2024 19:52, Richard Henderson
wrote:
On 6/11/24 03:33, Manos Pitsidianakis wrote:
+++ b/scripts/cargo_wrapper.py
@@ -0,0 +1,211 @@
+#!/usr/bin/env python3
+# Copyright (c) 2020 Red Hat, Inc.
+# Copyright (c) 2023 Linaro Ltd.
+#
+# Authors:
+# Manos Pitsidianakis
+# Marc-André
Dmitry Osipenko writes:
> Hello,
>
> This series enables Vulkan Venus context support on virtio-gpu.
>
> All virglrender and almost all Linux kernel prerequisite changes
> needed by Venus are already in upstream. For kernel there is a pending
> KVM patchset that fixes mapping of compound pages ne
Hi,
On 3/7/23 15:24, Cédric Le Goater wrote:
The parameters mimick a real 4GB eMMC, but it can be set to various
sizes. Initially from Vincent Palatin
Signed-off-by: Cédric Le Goater
---
hw/sd/sdmmc-internal.h | 97
include/hw/sd/sd.h | 1 +
hw/
1 - 100 of 173 matches
Mail list logo