Re: [PATCH v3 2/4] usb/hub: mark as deprecated

2024-06-14 Thread Gerd Hoffmann
On Thu, Jun 13, 2024 at 03:49:23PM GMT, Alex Bennée wrote: > Daniel P. Berrangé writes: > > > I don't want to loose that clear & easily understood meaning, by overloading > > "deprecated" for scenarios like "it is sometimes better to use a different > > device instead of this one, depending on fa

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

2024-06-14 Thread Manos Pitsidianakis
On Thu, 13 Jun 2024 23:57, Paolo Bonzini wrote: On Thu, Jun 13, 2024 at 11:16 AM Daniel P. Berrangé wrote: I guess there's a balance to be had somewhere on the spectrum between doing everything against the raw C binding, vs everything against a perfectly idiomatic Rust API wrapping the C bnidi

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

2024-06-14 Thread Thomas Huth
On 14/06/2024 08.07, Christian Borntraeger wrote: Am 13.06.24 um 19:07 schrieb Thomas Huth: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Thus add a CONFIG switch that can be used to d

[PULL 00/19] aspeed queue

2024-06-14 Thread Cédric Le Goater
The following changes since commit 046a64b9801343e2e89eef10c7a48eec8d8c0d4f: Merge tag 'pull-request-2024-06-12' of https://gitlab.com/thuth/qemu into staging (2024-06-13 07:51:58 -0700) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspee

[PULL 06/19] aspeed/sdmc: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin The SDRAM memory controller(DRAMC) controls the access to external DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY. The DRAM memory controller of AST2700 is not backward compatible to previous chips such AST2600, AST2500 and AST2400. Max memory is now 8GiB on the AST2700.

[PULL 19/19] MAINTAINERS: Add reviewers for ASPEED BMCs

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be reviewers of ASPEED BMCs. Signed-off-by: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jeffery --- MAINTAIN

[PULL 02/19] aspeed/wdt: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 wdt controller is similiar to AST2600's wdt, but the AST2700 has 8 watchdogs, and they each have 0x80 of registers. Introduce ast2700 object class and increase the number of regs(offset) of ast2700 model. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Céd

[PULL 09/19] aspeed/smc: support 64 bits dma dram address

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed

[PULL 11/19] aspeed/smc: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad c

[PULL 14/19] aspeed/soc: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU). AST2700 SOC and its interrupt controller are too complex to handle in the common Aspeed SoC framework. We introduce a new ast2700 class with instance_init and realize handlers. AST2700 is a 64 bits q

[PULL 01/19] aspeed/smc: Reintroduce "dram-base" property for AST2700

2024-06-14 Thread Cédric Le Goater
The Aspeed SMC device model use to have a 'sdram_base' property. It was removed by commit d177892d4a48 ("aspeed/smc: Remove unused "sdram-base" property") because previous changes simplified the DMA transaction model to use an offset in RAM and not the physical address. The AST2700 SoC has larger

[PULL 18/19] docs:aspeed: Add AST2700 Evaluation board

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Add AST2700 Evaluation board and its boot command. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- docs/system/arm/aspeed.rst | 39 ++ 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/docs/sy

[PULL 05/19] aspeed/sdmc: fix coding style

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Fix coding style issues from checkpatch.pl Test command: scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/misc/aspeed_sdmc.c | 11 +++ 1 file changed, 7 insertions(+), 4 del

[PULL 03/19] aspeed/sli: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 SLI engine is designed to accelerate the throughput between cross-die connections. It have CPU_SLI at CPU die and IO_SLI at IO die. Introduce dummy AST2700 SLI and SLIIO models. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- includ

[PULL 04/19] aspeed/sdmc: remove redundant macros

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin These macros are no longer used for ASPEED SOCs, so removes them. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/misc/aspeed_sdmc.c | 15 --- 1 file changed, 15 deletions(-) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspee

[PULL 15/19] aspeed: Add an AST2700 eval board

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 CPU is ARM Cortex-A35 which is 64 bits. Add TARGET_AARCH64 to build this machine. According to the design of ast2700, it has a bootmcu(riscv-32) which is used for executing SPL. Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. Currently, qemu not support emulate t

[PULL 16/19] aspeed/soc: fix incorrect dram size for AST2700

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 dram size calculation is not back compatible AST2600. According to the DDR capacity hardware behavior, if users write the data to the address which is beyond the ram size, it would write the data to the "address % ram_size". For example: a. sdram base address "0x4

[PULL 07/19] aspeed/smc: correct device description

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 7075bc9d61b0..fe1cd96b803a 100644 --- a/hw/ssi/aspee

[PULL 13/19] aspeed/intc: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 interrupt controller(INTC) provides hardware interrupt interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of INT 128 to INT136 combines 32 interrupts. Introduce a new aspeed_intc class with instance_init and realize handlers. So far, this mod

[PULL 08/19] aspeed/smc: support dma start length and 1 byte length unit

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA length is from 4 bytes to 32MB for AST2500. In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte data for AST2600 and AST10x0 and 4 bytes data for AST2500. To support all ASPEED SOCs, adds dma_start_

[PULL 17/19] test/avocado/machine_aspeed.py: Add AST2700 test case

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board. It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os images to dram first which base address is 0x4. Then, boot and launch 4 cpu cores. ``` qemu-system-aarch64 -machine ast2700-evb -device loader,

[PULL 12/19] aspeed/scu: Add AST2700 support

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin AST2700 have two SCU controllers which are SCU and SCUIO. Both SCU and SCUIO registers are not compatible previous SOCs , introduces new registers and adds ast2700 scu, sucio class init handler. The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and the pclk divide

[PULL 10/19] aspeed/smc: support different memory region ops for SMC flash region

2024-06-14 Thread Cédric Le Goater
From: Jamin Lin It set "aspeed_smc_flash_ops" struct which containing read and write callbacks to be used when I/O is performed on the SMC flash region. And it set the valid max_access_size 4 by default for all ASPEED SMC models. However, the valid max_access_size 4 only support 32 bits CPUs. To

Re: [PATCH v3 2/7] virtio-iommu: Implement set|unset]_iommu_device() callbacks

2024-06-14 Thread Cédric Le Goater
On 6/13/24 11:57 AM, Duan, Zhenzhong wrote: -Original Message- From: Eric Auger Subject: [PATCH v3 2/7] virtio-iommu: Implement set|unset]_iommu_device() callbacks Implement PCIIOMMUOPs [set|unset]_iommu_device() callbacks. In set(), a VirtioHostIOMMUDevice is allocated which holds a

Re: [PATCH v3 2/7] virtio-iommu: Implement set|unset]_iommu_device() callbacks

2024-06-14 Thread Eric Auger
Hi Zhenzhong, On 6/13/24 11:57, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Eric Auger >> Subject: [PATCH v3 2/7] virtio-iommu: Implement >> set|unset]_iommu_device() callbacks >> >> Implement PCIIOMMUOPs [set|unset]_iommu_device() callbacks. >> In set(), a VirtioHostIOMMUDevi

Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for tdx-guest object

2024-06-14 Thread Daniel P . Berrangé
On Fri, Jun 14, 2024 at 09:04:33AM +0800, Xiaoyao Li wrote: > On 6/13/2024 4:35 PM, Duan, Zhenzhong wrote: > > > > > > > -Original Message- > > > From: Li, Xiaoyao > > > Subject: Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for > > > tdx-guest object > > > > > > On 6/6/20

Re: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions

2024-06-14 Thread Eric Auger
On 6/14/24 05:05, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Eric Auger >> Subject: Re: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions >> >> >> >> On 6/13/24 12:00, Duan, Zhenzhong wrote: >>> Hi Eric, >>> -Original Message- From: Eric Auger >>

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

2024-06-14 Thread Christian Borntraeger
Am 14.06.24 um 09:15 schrieb Thomas Huth: On 14/06/2024 08.07, Christian Borntraeger wrote: Am 13.06.24 um 19:07 schrieb Thomas Huth: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build.

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

2024-06-14 Thread Thomas Huth
On 14/06/2024 10.17, Christian Borntraeger wrote: Am 14.06.24 um 09:15 schrieb Thomas Huth: On 14/06/2024 08.07, Christian Borntraeger wrote: Am 13.06.24 um 19:07 schrieb Thomas Huth: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would li

Re: [PATCH v4 28/31] hw/i386: Add support for loading BIOS using guest_memfd

2024-06-14 Thread Xiaoyao Li
On 5/30/2024 7:16 PM, Pankaj Gupta wrote: From: Michael Roth When guest_memfd is enabled, the BIOS is generally part of the initial encrypted guest image and will be accessed as private guest memory. Add the necessary changes to set up the associated RAM region with a guest_memfd backend to all

Re: [PATCH v2 00/22] qga: clean up command source locations and conditionals

2024-06-14 Thread Marc-André Lureau
Hi On Thu, Jun 13, 2024 at 7:02 PM Daniel P. Berrangé wrote: > This series is a side effect of other work I started, to attempt to > make the QGA safe to use in confidential VMs by automatically > restricting the permitted commands. Since this cleanup stands on > its own, I'm sending it now. > >

Re: [PATCH v3 2/4] usb/hub: mark as deprecated

2024-06-14 Thread Gerd Hoffmann
Hi, > > This does seem quite aggressive because there may be cases when users > > explicitly want to use old devices. Maybe there is need for a third > > state (better_alternatives?) so we can steer users away from old command > > lines they may have picked up from the web to the modern alternat

Re: [RFC PATCH v2 0/2] ui/gtk: Introduce new param - Connectors

2024-06-14 Thread Marc-André Lureau
Hi On Thu, Jun 13, 2024 at 9:08 PM Kim, Dongwon wrote: > > "hotplug" functionality where a Guest display/window is deeply tied > to a > > physical monitor to make it appear to the guest that it is dealing > with > > a real physical monitor. > > > > In other words, when the physic

Re: [PATCH 09/20] qapi/parser: add undocumented stub members to all_sections

2024-06-14 Thread Markus Armbruster
John Snow writes: > This helps simplify the doc generator if it doesn't have to check for > undocumented members. > > Signed-off-by: John Snow > --- > scripts/qapi/parser.py | 20 ++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/scripts/qapi/parser.py b/s

Re: [PATCH v4 28/31] hw/i386: Add support for loading BIOS using guest_memfd

2024-06-14 Thread Gupta, Pankaj
On 6/14/2024 10:34 AM, Xiaoyao Li wrote: On 5/30/2024 7:16 PM, Pankaj Gupta wrote: From: Michael Roth When guest_memfd is enabled, the BIOS is generally part of the initial encrypted guest image and will be accessed as private guest memory. Add the necessary changes to set up the associated RA

Re: [PATCH v4 27/31] hw/i386/sev: Use guest_memfd for legacy ROMs

2024-06-14 Thread Xiaoyao Li
On 5/30/2024 7:16 PM, Pankaj Gupta wrote: From: Michael Roth Current SNP guest kernels will attempt to access these regions with with C-bit set, so guest_memfd is needed to handle that. Otherwise, kvm_convert_memory() will fail when the guest kernel tries to access it and QEMU attempts to call

Re: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions

2024-06-14 Thread Eric Auger
Hi Zhenzhong, On 6/14/24 05:05, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Eric Auger >> Subject: Re: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions >> >> >> >> On 6/13/24 12:00, Duan, Zhenzhong wrote: >>> Hi Eric, >>> -Original Message- From: Er

Re: [PATCH v2 6/9] target/arm: Factor out code for setting MTE TCF0 field

2024-06-14 Thread Philippe Mathieu-Daudé
On 13/6/24 20:15, Gustavo Romero wrote: Hi Phil, On 6/13/24 2:35 PM, Philippe Mathieu-Daudé wrote: On 13/6/24 19:21, Gustavo Romero wrote: Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this fi

Re: [PATCH v4 28/31] hw/i386: Add support for loading BIOS using guest_memfd

2024-06-14 Thread Xiaoyao Li
On 6/14/2024 4:48 PM, Gupta, Pankaj wrote: On 6/14/2024 10:34 AM, Xiaoyao Li wrote: On 5/30/2024 7:16 PM, Pankaj Gupta wrote: From: Michael Roth When guest_memfd is enabled, the BIOS is generally part of the initial encrypted guest image and will be accessed as private guest memory. Add the n

Re: [PATCH v2 0/2] AWS Nitro Enclave emulation

2024-06-14 Thread Alexander Graf
On 01.06.24 18:26, Dorjoy Chowdhury wrote: This is v2 submission for AWS Nitro Enclave emulation in QEMU. v1 is at: https://mail.gnu.org/archive/html/qemu-devel/2024-05/msg03524.html Changes in v2: - moved eif.c and eif.h files from hw/i386 to hw/core Hi, Hope everyone is doing well. I a

Re: [PATCH v3 1/7] HostIOMMUDevice: Store the VFIO/VDPA agent

2024-06-14 Thread Cédric Le Goater
On 6/13/24 11:20 AM, Eric Auger wrote: Store the agent device (VFIO or VDPA) in the host IOMMU device. This will allow easy access to some of its resources. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan --- include/sysemu/host_iommu_device.h | 1 + hw/vfio/container.c

Re: [PATCH v2 00/22] qga: clean up command source locations and conditionals

2024-06-14 Thread Daniel P . Berrangé
On Fri, Jun 14, 2024 at 12:34:52PM +0400, Marc-André Lureau wrote: > Hi > > On Thu, Jun 13, 2024 at 7:02 PM Daniel P. Berrangé > wrote: > > > This series is a side effect of other work I started, to attempt to > > make the QGA safe to use in confidential VMs by automatically > > restricting the

Re: [PATCH] ui/gtk: Wait until the current guest frame is rendered before switching to RUN_STATE_SAVE_VM

2024-06-14 Thread Marc-André Lureau
Hi On Thu, Jun 13, 2024 at 9:27 PM Kim, Dongwon wrote: > Hi Marc-André, > > On 6/13/2024 6:16 AM, Marc-André Lureau wrote: > > Hi > > > > On Wed, Jun 12, 2024 at 10:50 PM Kim, Dongwon > > wrote: > > > > On 6/11/2024 10:44 PM, Marc-André Lureau wrote: > > >

Re: [RFC PATCH] migration/savevm: do not schedule snapshot_save_job_bh in qemu_aio_context

2024-06-14 Thread Fiona Ebner
Am 12.06.24 um 17:34 schrieb Stefan Hajnoczi: > > Thank you for investigating! It looks like we would be trading one > issue (the assertion failures you mentioned) for another (a rare, but > possible, hang). > > I'm not sure what the best solution is. It seems like vm_stop() is the > first place

[PATCH RFC 0/3] Add DCC uart console support

2024-06-14 Thread Sai Pavan Boddu
This patch series attaches a chardev to arm Debug Communication channel registers, As each cpu has it own DBGDTRTX/RX register just tried to hook each cpu with chardev iff we find a chardev with id "dcc". ex: Below chardev switch would be connected to A53-0. ./qemu-system-aarch64 -M xln

[PATCH RFC 2/3] target/arm: Enable dcc console for a53 and R5

2024-06-14 Thread Sai Pavan Boddu
This enabled DCC support. Signed-off-by: Sai Pavan Boddu --- target/arm/cpu64.c | 1 + target/arm/tcg/cpu32.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 262a1d6c0b..e39740303b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@

[PATCH RFC 3/3] target/arm/debug_helper: Add fieldoffset for MDCCSR_EL0 reg

2024-06-14 Thread Sai Pavan Boddu
MDCCSR_EL0 is aarch64 varient of DBGDSCRint, so utilize the same cpreg offset. Signed-off-by: Sai Pavan Boddu --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..5deafa4d1f 10064

[PATCH RFC 1/3] target/arm: Add dcc uart support

2024-06-14 Thread Sai Pavan Boddu
DCC is a debug port to transfer some data between debugger and processor, we are using this feature to connect a chardev device. Chardev frontends should be named as "dcc" inorder to connect to this interface. Signed-off-by: Sai Pavan Boddu --- target/arm/cpu.h | 11 + target/arm/inter

Re: *** MAY_BE_SPAM !!! *** Re: [PATCH] tests/qtest/fuzz/virtio_net_fuzz.c: fix virtio_net_fuzz_multi

2024-06-14 Thread Дмитрий Фролов
On 13.06.2024 18:54, Alexander Bulekov wrote: This fixes the almost-immediate timeout issue for me on the virtio_net_fuzz target, but I'm not sure why this works or if it is fixing the right problem: qtest_probe_child is designed to run from a libqtest process which uses waitpid on the PID of th

Re: [PATCH v3] target/loongarch/kvm: Add software breakpoint support

2024-06-14 Thread gaosong
在 2024/6/7 上午11:50, Bibo Mao 写道: With KVM virtualization, debug exception is injected to guest kernel rather than host for normal break intruction. Here hypercall instruction with special code is used for sw breakpoint usage, and detailed instruction comes from kvm kernel with user API KVM_REG_LO

Re: [PATCH 11/20] qapi/schema: add doc_visible property to QAPISchemaDefinition

2024-06-14 Thread Markus Armbruster
John Snow writes: > The intent here is to mark only certain definitions as visible in the > end-user docs. > > All commands and events are inherently visible. Everything else is > visible only if it is a member (or a branch member) of a type that is > visible, or if it is named as a return type f

Re: [PATCH] tests/qtest/fuzz/virtio_net_fuzz.c: fix virtio_net_fuzz_multi

2024-06-14 Thread Дмитрий Фролов
On 13.06.2024 19:50, Thomas Huth wrote: On 13/06/2024 13.59, Дмитрий Фролов wrote: On 13.06.2024 13:08, Thomas Huth wrote: On 23/05/2024 12.28, Dmitry Frolov wrote: If QTestState was already CLOSED due to error, calling qtest_clock_step() afterwards makes no sense and only raises false-cras

Re: [PATCH 13/20] docs/qapidoc: fix nested parsing under untagged sections

2024-06-14 Thread Markus Armbruster
John Snow writes: > Sphinx does not like sections without titles, because it wants to > convert every section into a reference. When there is no title, it > struggles to do this and transforms the tree inproperly. > > Depending on the rST used, this may result in an assertion error deep in > the

[PATCH v4 1/8] HostIOMMUDevice: Store the VFIO/VDPA agent

2024-06-14 Thread Eric Auger
Store the agent device (VFIO or VDPA) in the host IOMMU device. This will allow easy access to some of its resources. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan --- include/sysemu/host_iommu_device.h | 1 + hw/vfio/container.c| 1 + hw/vfio/iommufd.c

[PATCH v4 4/8] HostIOMMUDevice: Store the aliased bus and devfn

2024-06-14 Thread Eric Auger
Store the aliased bus and devfn in the HostIOMMUDevice. This will be useful to handle info that are iommu group specific and not device specific (such as reserved iova ranges). Signed-off-by: Eric Auger --- include/sysemu/host_iommu_device.h | 2 ++ hw/pci/pci.c | 8 ++-

[PATCH v4 8/8] memory: Remove IOMMU MR iommu_set_iova_range API

2024-06-14 Thread Eric Auger
Since the host IOVA ranges are now passed through the PCIIOMMUOps set_host_resv_regions and we have removed the only implementation of iommu_set_iova_range() in the virtio-iommu and the only call site in vfio/common, let's retire the IOMMU MR API and its memory wrapper. Signed-off-by: Eric Auger

[PATCH v4 6/8] virtio-iommu: Remove the implementation of iommu_set_iova_range

2024-06-14 Thread Eric Auger
Now that we use PCIIOMMUOps to convey information about usable IOVA ranges we do not to implement the iommu_set_iova_ranges IOMMU MR callback. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan --- hw/virtio/virtio-iommu.c | 67 1 file changed, 67 del

[PATCH v4 2/8] virtio-iommu: Implement set|unset]_iommu_device() callbacks

2024-06-14 Thread Eric Auger
Implement PCIIOMMUOPs [set|unset]_iommu_device() callbacks. In set(), the HostIOMMUDevice handle is stored in a hash table indexed by PCI BDF. The object will allow to retrieve information related to the physical IOMMU. Signed-off-by: Eric Auger --- v3 -> v4: - Simply use native HostIOMMUDevice

[PATCH v4 7/8] hw/vfio: Remove memory_region_iommu_set_iova_ranges() call

2024-06-14 Thread Eric Auger
As we have just removed the only implementation of iommu_set_iova_ranges IOMMU MR callback in the virtio-iommu, let's remove the call to the memory wrapper. Usable IOVA ranges are now conveyed through the PCIIOMMUOps in VFIO-PCI. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan --- hw/vfio

[PATCH v4 0/8] VIRTIO-IOMMU/VFIO: Fix host iommu geometry handling for hotplugged devices

2024-06-14 Thread Eric Auger
This series is based on Zhenzhong HostIOMMUDevice: [PATCH v7 00/17] Add a host IOMMU device abstraction to check with vIOMMU https://lore.kernel.org/all/20240605083043.317831-1-zhenzhong.d...@intel.com/ It allows to convey host IOVA reserved regions to the virtio-iommu and uses the HostIOMMUDevi

[PATCH v4 3/8] HostIOMMUDevice: Introduce get_iova_ranges callback

2024-06-14 Thread Eric Auger
Introduce a new HostIOMMUDevice callback that allows to retrieve the usable IOVA ranges. Implement this callback in the legacy VFIO and IOMMUFD VFIO host iommu devices. This relies on the VFIODevice agent's base container iova_ranges resource. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Dua

[PATCH v4 5/8] virtio-iommu: Compute host reserved regions

2024-06-14 Thread Eric Auger
Compute the host reserved regions in virtio_iommu_set_iommu_device(). The usable IOVA regions are retrieved from the HostIOMMUDevice. The virtio_iommu_set_host_iova_ranges() helper turns usable regions into complementary reserved regions while testing the inclusion into existing ones. virtio_iommu_

Re: [PATCH v3 1/7] HostIOMMUDevice: Store the VFIO/VDPA agent

2024-06-14 Thread Eric Auger
Hi Cédric, On 6/14/24 11:13, Cédric Le Goater wrote: > On 6/13/24 11:20 AM, Eric Auger wrote: >> Store the agent device (VFIO or VDPA) in the host IOMMU device. >> This will allow easy access to some of its resources. >> >> Signed-off-by: Eric Auger >> Reviewed-by: Zhenzhong Duan >> --- >>   inc

Re: [PATCH v4 27/31] hw/i386/sev: Use guest_memfd for legacy ROMs

2024-06-14 Thread Gupta, Pankaj
On 6/14/2024 10:58 AM, Xiaoyao Li wrote: On 5/30/2024 7:16 PM, Pankaj Gupta wrote: From: Michael Roth Current SNP guest kernels will attempt to access these regions with with C-bit set, so guest_memfd is needed to handle that. Otherwise, kvm_convert_memory() will fail when the guest kernel tri

Re: [PATCH v3 1/7] HostIOMMUDevice: Store the VFIO/VDPA agent

2024-06-14 Thread Cédric Le Goater
Talking of which, why are we passing a 'VFIODevice *' parameter to HostIOMMUDeviceClass::realize ? I don't see a good reason I think a 'VFIOContainerBase *' would be more appropriate since 'HostIOMMUDevice' represents a device on the host which is common to all VFIO devices. In that case, H

[PATCH] i386: revert defaults to 'legacy-vm-type=true' for SEV(-ES) guests

2024-06-14 Thread Daniel P . Berrangé
The KVM_SEV_INIT2 ioctl was only introduced in Linux 6.10, which will only have been released for a bit over a month when QEMU 9.1 is released. The SEV(-ES) support in QEMU has been present since 2.12 dating back to 2018. With this in mind, the overwhealming majority of users of SEV(-ES) are unlik

Re: [PATCH v5 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine

2024-06-14 Thread Marcin Juszkiewicz
W dniu 7.06.2024 o 12:38, Xiong Yining pisze: Enable CPU cluster support on SbsaQemu platform, so that users can specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this topology can be passed to the firmware through /cpus/topology Device Tree. Signed-off-by: Xiong Yining tested

Re: [PATCH v2 8/9] gdbstub: Add support for MTE in user mode

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > This commit implements the stubs to handle the qIsAddressTagged, > qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' > subcommands to work with QEMU gdbstub on aarch64 user mode. It also > implements the get/set functions for the special GDB MTE register > '

Re: [PATCH 14/20] qapi: fix non-compliant JSON examples

2024-06-14 Thread Markus Armbruster
John Snow writes: > If we parse all examples as QMP, we need them to conform to a standard > so that they render correctly. Once the QMP lexer is active for > examples, these will produce warning messages and fail the build. > > The QMP lexer still supports elisions, but they must be represented

Re: [PATCH qemu ] hw/acpi: Fix big endian host creation of Generic Port Affinity Structures

2024-06-14 Thread Igor Mammedov
On Thu, 6 Jun 2024 18:47:16 +0100 Jonathan Cameron wrote: > On Thu, 6 Jun 2024 16:06:53 +0200 > Igor Mammedov wrote: > > > On Wed, 5 Jun 2024 19:04:55 +0100 > > Jonathan Cameron wrote: > > > > > Treating the HID as an integer caused it to get bit reversed > > > on big endian hosts running lit

Re: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property

2024-06-14 Thread Edgar E. Iglesias
On Thu, Jun 13, 2024 at 5:36 PM Sai Pavan Boddu wrote: > Read boot-mode value as machine property and propagate that to > SLCR.BOOT_MODE register. > > Hi Sai, Directly exposing the register field to the user to set on the command-line probably makes usability a little too rough (user has to chec

Re: [PATCH v2 6/9] target/arm: Factor out code for setting MTE TCF0 field

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Factor out the code used for setting the MTE TCF0 field from the prctl > code into a convenient function. Other subsystems, like gdbstub, need to > set this field as well, so keep it as a separate function to avoid > duplication and ensure consistency in how this field is

Re: [PATCH v2 1/9] gdbstub: Clean up process_string_cmd

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Change 'process_string_cmd' to return true on success and false on > failure, instead of 0 and -1. > > Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH 18/20] qapi: ensure all errors sections are uniformly typset

2024-06-14 Thread Markus Armbruster
John Snow writes: > Transactions have the only instance of an Errors section that isn't a > rST list; turn it into one. Just for consistency? Or do you have other shenanigans up your sleeve? If we want the Errors sections to remain all rST lists, we should update docs/devel/qapi-code-gen.rst t

Re: [PATCH v2 2/9] gdbstub: Move GdbCmdParseEntry into a new header file

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Move GdbCmdParseEntry and its associated types into a separate header > file to allow the use of GdbCmdParseEntry and other gdbstub command > functions outside of gdbstub.c. > > Since GdbCmdParseEntry and get_param are now public, kdoc > GdbCmdParseEntry and rename get_pa

Re: [PATCH v2 3/9] gdbstub: Add support for target-specific stubs

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Currently, it's not possible to have stubs specific to a given target, > even though there are GDB features which are target-specific, like, for > instance, memory tagging. > > This commit introduces gdb_extend_qsupported_features, > gdb_extend_query_table, and gdb_extend

Re: [PATCH v3 1/5] ppc/pnv: Add SPI controller model

2024-06-14 Thread Cédric Le Goater
On 6/13/24 3:45 PM, Chalapathi V wrote: On 20-05-2024 11:19, Cédric Le Goater wrote: On 5/15/24 19:41, Chalapathi V wrote: SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller. All SPI functio

Re: [PATCH v2 4/9] target/arm: Fix exception case in allocation_tag_mem_probe

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > If page in 'ptr_access' is inaccessible and probe is 'true' > allocation_tag_mem_probe should not throw an exception, but currently it > does, so fix it. > > Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH v2 7/9] gdbstub: Make get cpu and hex conversion functions non-internal

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they > are not confined to use only in gdbstub.c. so they can be used by architecture extensions to the gdbstub? we don't want everyone using these functions, or if we do maybe we should consider moving th

Re: [PATCH v2 9/9] tests/tcg/aarch64: Add MTE gdbstub tests

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > Add tests to exercise the MTE stubs. > > Signed-off-by: Gustavo Romero > --- > tests/tcg/aarch64/Makefile.target | 11 ++- > tests/tcg/aarch64/gdbstub/test-mte.py | 86 ++ > tests/tcg/aarch64/mte-8.c | 102 ++

Re: [PATCH v3 1/5] ppc/pnv: Add SPI controller model

2024-06-14 Thread Chalapathi V
On 14-06-2024 16:57, Cédric Le Goater wrote: On 6/13/24 3:45 PM, Chalapathi V wrote: On 20-05-2024 11:19, Cédric Le Goater wrote: On 5/15/24 19:41, Chalapathi V wrote: SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flas

Re: [PATCH v2 5/9] target/arm: Make some MTE helpers widely available

2024-06-14 Thread Philippe Mathieu-Daudé
On 13/6/24 20:13, Gustavo Romero wrote: Hi Phil! On 6/13/24 2:32 PM, Philippe Mathieu-Daudé wrote: Hi Gustavo, On 13/6/24 19:20, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems by moving them from mte_helper.c to a n

[PATCH v2] target/s390x: Add a CONFIG switch to disable legacy CPUs

2024-06-14 Thread Thomas Huth
The oldest model that IBM still supports is the z13. Considering that each generation can "emulate" the previous two generations in hardware (via the "IBC" feature of the CPUs), this means that everything that is older than z114/196 is not an officially supported CPU model anymore. The Linux kernel

[PATCH] os-posix: Expand setrlimit() syscall compatibility

2024-06-14 Thread Trent Huber
Darwin (I'm running version 19.6.0) uses a subtly different version of the setrlimit() syscall as described in the COMPATIBILITY section of the macOS man page. I adjusted the way the rlim_cur member is set to accommodate and which shouldn't affect any non-Darwin systems. Signed-off-by: Trent Huber

Re: [PATCH v8 0/7] Live Migration With IAA

2024-06-14 Thread Fabiano Rosas
On Mon, 10 Jun 2024 18:21:03 +0800, Yuan Liu wrote: > I am writing to submit a code change aimed at enhancing live migration > acceleration by leveraging the compression capability of the Intel > In-Memory Analytics Accelerator (IAA). > > The implementation of the IAA (de)compression code is based

Re: [PATCH v2 0/7] Live migration acceleration with UADK

2024-06-14 Thread Fabiano Rosas
On Fri, 07 Jun 2024 14:53:03 +0100, Shameer Kolothum via wrote: > v1 --> v2 > (v1: > https://lore.kernel.org/qemu-devel/20240529094435.11140-1-shameerali.kolothum.th...@huawei.com/) > > -Rebased on top of Intel IAA v7 series[0]. > -Addressed comments from Fabiano. Thanks. > -Gathered tags receive

Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

2024-06-14 Thread LIU Zhiwei
On 2024/6/14 9:46, Ethan Chen wrote: On Thu, Jun 13, 2024 at 05:26:03PM +0800, LIU Zhiwei wrote: Hi Ethan, On 2024/6/12 11:17, Ethan Chen wrote: Support basic functions of IOPMP specification v0.9.1 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/ta

Re: [PATCH] os-posix: Expand setrlimit() syscall compatibility

2024-06-14 Thread Daniel P . Berrangé
On Fri, Jun 14, 2024 at 01:14:22AM -0400, Trent Huber wrote: > Darwin (I'm running version 19.6.0) uses a subtly different version > of the setrlimit() syscall as described in the COMPATIBILITY section > of the macOS man page. I adjusted the way the rlim_cur member is set > to accommodate and which

Re: [PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support

2024-06-14 Thread LIU Zhiwei
On 2024/6/12 20:10, Daniel Henrique Barboza wrote: On 6/12/24 4:50 AM, LIU Zhiwei wrote: On 2024/6/11 18:13, Daniel Henrique Barboza wrote: Hi Zhiwei, On 6/10/24 10:51 PM, LIU Zhiwei wrote: Hi Daniel, I want to know if we can use the IOMMU and IOPMP at the same time. AFAIK we can. The

Re: [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull

2024-06-14 Thread LIU Zhiwei
On 2024/6/13 18:37, Jim Shu wrote: Hi Zhiwei, Common IOMMU devices will not have IOMMUMemoryRegion in the path of CPU access since It only affects DMA access. In QEMU, it usually places this IOMMU MR as the parent of "system_memory", and changes the target_mr of DMA from "system_memory" to IOM

Re: [PATCH 19/20] qapi: convert "Note" sections to plain rST

2024-06-14 Thread Markus Armbruster
John Snow writes: > We do not need a dedicated section for notes. By eliminating a specially > parsed section, these notes can be treated as normal rST paragraphs in > the new QMP reference manual, and can be placed and styled much more > flexibly. > > Update the QAPI parser to now prohibit speci

Re: [PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

2024-06-14 Thread Jiaxun Yang
在2024年6月14日六月 上午6:17,maobibo写道: > On 2024/6/14 下午12:27, Jiaxun Yang wrote: >> >> >> 在2024年6月14日六月 上午4:32,maobibo写道: >>> It is interesting. >>> >>> How to wakeup VM if it sleeps in S3/S4, from emulated keyboard or >>> ethernet magic packet or qemu monitor command in background? >> >> Hi Bibo,

Re: [PATCH qemu ] hw/acpi: Fix big endian host creation of Generic Port Affinity Structures

2024-06-14 Thread Jonathan Cameron via
On Fri, 14 Jun 2024 12:57:25 +0200 Igor Mammedov wrote: > On Thu, 6 Jun 2024 18:47:16 +0100 > Jonathan Cameron wrote: > > > On Thu, 6 Jun 2024 16:06:53 +0200 > > Igor Mammedov wrote: > > > > > On Wed, 5 Jun 2024 19:04:55 +0100 > > > Jonathan Cameron wrote: > > > > > > > Treating the HID

Re: [PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

2024-06-14 Thread Daniel P . Berrangé
On Fri, Jun 14, 2024 at 01:17:39PM +0800, maobibo wrote: > > > On 2024/6/14 下午12:27, Jiaxun Yang wrote: > > > > > > 在2024年6月14日六月 上午4:32,maobibo写道: > > > It is interesting. > > > > > > How to wakeup VM if it sleeps in S3/S4, from emulated keyboard or > > > ethernet magic packet or qemu monitor

Re: [PATCH 20/20] qapi: convert "Example" sections to rST

2024-06-14 Thread Markus Armbruster
John Snow writes: > Eliminate the "Example" sections in QAPI doc blocks, converting them > into QMP example code blocks. This is generally done by converting > "Example:" or "Examples:" lines into ".. code-block:: QMP" lines. > > This patch does also allow for the use of the rST syntax "Example::

RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property

2024-06-14 Thread Boddu, Sai Pavan
Hi Edgar, From: Edgar E. Iglesias Sent: Friday, June 14, 2024 4:38 PM To: Boddu, Sai Pavan Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis ; Peter Maydell ; Iglesias, Francisco Subject: Re: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property On Thu, Jun 13, 2024 at 5:36 P

[PATCH v2] linux-user: Make TARGET_NR_setgroups affect only the current thread

2024-06-14 Thread Ilya Leoshkevich
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the calling thread, and not the entire process. Therefore, implement it using a syscall, and not a libc call. Cc: qemu-sta...@nongnu.org Fixes: 19b84f3c35d7 ("added setgroups and getgroups syscalls") Signed-off-by: Ilya Leoshkevich Rev

Re: [PATCH v2 0/9] Add MTE stubs for aarch64 user mode

2024-06-14 Thread Alex Bennée
Gustavo Romero writes: > This patchset adds the stubs necessary to support GDB memory tagging > commands on QEMU aarch64 user mode. > > These new stubs handle the qIsAddressTagged, qMemTag, and QMemTag > packets, which allow GDB memory tagging subcommands 'check', > 'print-allocation-tag', and 's

Re: [PATCH v2 9/9] tests/tcg/aarch64: Add MTE gdbstub tests

2024-06-14 Thread Gustavo Romero
Hi Alex! On 6/14/24 8:42 AM, Alex Bennée wrote: Gustavo Romero writes: Add tests to exercise the MTE stubs. Signed-off-by: Gustavo Romero --- tests/tcg/aarch64/Makefile.target | 11 ++- tests/tcg/aarch64/gdbstub/test-mte.py | 86 ++ tests/tcg/aarch64/mte-8.c

Re: [PATCH v2 0/9] Add MTE stubs for aarch64 user mode

2024-06-14 Thread Gustavo Romero
On 6/14/24 12:49 PM, Alex Bennée wrote: Gustavo Romero writes: This patchset adds the stubs necessary to support GDB memory tagging commands on QEMU aarch64 user mode. These new stubs handle the qIsAddressTagged, qMemTag, and QMemTag packets, which allow GDB memory tagging subcommands 'che

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