+static void aspeed_2700_intc_class_init(ObjectClass *klass, void
+*data) {
+DeviceClass *dc = DEVICE_CLASS(klass);
+AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+dc->desc = "ASPEED 2700 INTC Controller";
+aic->num_lines = 32;
+aic->num_ints = 9;
Use ASPEED_INTC_NR_INTS
Queued, thanks.
Paolo
@@ -670,7 +670,7 @@ static const MemoryRegionOps
aspeed_smc_flash_ops
= {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
- .max_access_size = 4,
+ .max_access_size = 8,
Is this a bugfix? If so, please use a separate patch. Otherwise
We can remove Xen from default build too. Though, I think, regardless
of Xen being in our out of default build, the "depends on" change in
`hw/i386/Kconfig` is essential in itself to cover the case when a user
builds with Xen only. In case of a Xen only build by user, without the
proposed Kconfig c
On 6/2/24 12:05, lixinyu...@ict.ac.cn wrote:
From: Xinyu Li
This commit fixes an issue with MOV instructions (0x8C and 0x8E)
involving segment registers by explicitly setting the memory operand
size to 16 bits. It introduces a new flag X86_SPECIAL_MovSeg to handle
this specification correctly.
03.06.2024 10:31, Vilhelm Gyda wrote:
We can remove Xen from default build too. Though, I think, regardless
of Xen being in our out of default build, the "depends on" change in
`hw/i386/Kconfig` is essential in itself to cover the case when a user
builds with Xen only. In case of a Xen only build
On Mon, Jun 3, 2024 at 1:10 PM Michael Tokarev wrote:
>
> 03.06.2024 10:31, Vilhelm Gyda wrote:
> > We can remove Xen from default build too. Though, I think, regardless
> > of Xen being in our out of default build, the "depends on" change in
> > `hw/i386/Kconfig` is essential in itself to cover t
On 5/31/24 17:46, Philippe Mathieu-Daudé wrote:
> On 31/5/24 17:10, Michal Privoznik wrote:
>> The unspoken premise of qemu_madvise() is that errno is set on
>> error. And it is mostly the case except for posix_madvise() which
>> is documented to return either zero (on success) or a positive
>> err
DisasContext.cpuid_ext_features indicates CPUID.01H.ECX.
Use DisasContext.cpuid_7_0_ecx_features field to check RDPID feature bit
(CPUID_7_0_ECX_RDPID).
Fixes: 6750485bf42a ("target/i386: implement RDPID in TCG")
Inspired-by: Xinyu Li
Signed-off-by: Zhao Liu
---
target/i386/tcg/translate.c | 2
On 6/2/24 08:26, Akihiko Odaki wrote:
> On 2024/06/01 0:46, Philippe Mathieu-Daudé wrote:
>> On 31/5/24 17:10, Michal Privoznik wrote:
>>> The unspoken premise of qemu_madvise() is that errno is set on
>>> error. And it is mostly the case except for posix_madvise() which
>>> is documented to return
Queued, thanks.
Paolo
Hi Gavin,
On Sat, Jun 01, 2024 at 08:14:46PM +1000, Gavin Shan wrote:
> ---> guest edk2
>
> # git clone https://git.codelinaro.org/linaro/dcap/edk2.git edk2-guest
> # cd edk2-guest; git checkout origin/cca/v2 -b cca/v2
> # git submodule update --init --recursive; \
> source edksetup.sh; make -
On 30/5/24 16:53, Philippe Mathieu-Daudé wrote:
v2: Address Paolo's comment
Missing review: 1 & 2
Semihosting currently uses the TCG probe_access API,
so it is pointless to have it in the binary when TCG
isn't.
It could be implemented for other accelerators, but
work need to be done. Meanwhi
From: Minwoo Im
This patch is a prep patch for the following MCQ support patch for
hw/ufs. This patch updated minimal mandatory fields to support MCQ
based on UFSHCI 4.0.
Signed-off-by: Minwoo Im
Reviewed-by: Jeuk Kim
Message-Id: <20240528023106.856777-2-minwoo...@samsung.com>
Signed-off-by:
com/jeuk20.kim/qemu.git tags/pull-ufs-20240603
for you to fetch changes up to 5c079578d2e46df626d13eeb629c7d761a5c4e44:
hw/ufs: Add support MCQ of UFSHCI 4.0 (2024-06-03 16:20:42 +0900)
hw/ufs patches
- Add support MCQ of
From: Minwoo Im
This patch adds support for MCQ defined in UFSHCI 4.0. This patch
utilized the legacy I/O codes as much as possible to support MCQ.
MCQ operation & runtime register is placed at 0x1000 offset of UFSHCI
register statically with no spare space among four registers (48B):
When QEMU is started with:
-cpu host,host-cache-info=on,l3-cache=off \
-smp 2,sockets=1,dies=1,cores=1,threads=2
Guest can't acquire maximum number of addressable IDs for processor cores in
the physical package from CPUID[04H].
When testing Intel TDX, guest attempts to acquire extended topology fr
Thomas Huth writes:
> On 30/05/2024 16.01, Zhao Liu wrote:
>> Hi Thomas,
>> BTW, do you think it's a good idea to define the overcommit via QAPI way
>> (defined in a json file)? ;-)
>> My rough understanding is that all APIs are better to be defined via
>> QAPI to go JSON compatible.
>
> Sorry, n
On 31/5/24 16:11, Dr. David Alan Gilbert wrote:
* Don Porter (por...@cs.unc.edu) wrote:
The new "info pg" monitor command prints the current page table,
including virtual address ranges, flag bits, and snippets of physical
page numbers. Completely filled regions of the page table with
compatibl
On 2024/06/03 16:56, Michal Prívozník wrote:
On 6/2/24 08:26, Akihiko Odaki wrote:
On 2024/06/01 0:46, Philippe Mathieu-Daudé wrote:
On 31/5/24 17:10, Michal Privoznik wrote:
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case except for posix_madvis
On Sun, Jun 02, 2024 at 09:26:09AM GMT, Michael S. Tsirkin wrote:
> On Thu, Apr 11, 2024 at 11:48:28AM +0200, Gerd Hoffmann wrote:
> > Add a new "etc/boot/kernel" fw_cfg file, containing the kernel without
> > the setup header patches. Intended use is booting in UEFI with secure
> > boot enabled,
On 5/13/24 9:31 AM, Andrey Drobyshev wrote:
> v1: https://lists.nongnu.org/archive/html/qemu-devel/2023-10/msg07223.html
>
> Andrey Drobyshev (11):
> qcow2: make function update_refcount_discard() global
> qcow2: simplify L2 entries accounting for discard-no-unref
> qcow2: put discard reques
On Sat, 1 Jun 2024 23:26:55 +0800
Zhao Liu wrote:
> On Fri, May 31, 2024 at 10:13:47AM -0700, Chen, Zide wrote:
> > Date: Fri, 31 May 2024 10:13:47 -0700
> > From: "Chen, Zide"
> > Subject: Re: [PATCH V2 2/3] target/i386: call cpu_exec_realizefn before
> > x86_cpu_filter_features
> >
> > On 5/
On Fri, May 31, 2024 at 10:51:53AM -0700, Octavian Purdila wrote:
> Add path option to the pty char backend which will create a symbolic
> link to the given path that points to the allocated PTY.
>
> Based on patch from Paulo Neves:
>
> https://patchew.org/QEMU/1548509635-15776-1-git-send-email-p
On Sat, Jun 01, 2024 at 09:05:39AM +0200, Thomas Huth wrote:
> We've missed to delete this file when removing support for CentOS 8.
> Since the current upstream version of the lcitool removed support
> for CentOS 8 now, too, we have to remove the file before updating.
>
> Signed-off-by: Thomas Hut
On Sat, Jun 01, 2024 at 09:05:40AM +0200, Thomas Huth wrote:
> Update to the latest version of lcitool. It dropped support for Fedora 38
> and Alpine 3.18, so we have to update these to newer versions here, too.
>
> Python 3.12 dropped the "imp" module which we still need for running
> Avocado. Fo
Stefano Garzarella writes:
> The default value of the @share option of the @MemoryBackendProperties
> eally depends on the backend type, so let's document it explicitly and
> add the default value where it was missing.
>
> Cc: David Hildenbrand
> Suggested-by: Markus Armbruster
> Signed-off-by:
On Mon, 3 Jun 2024 at 09:46, Philippe Mathieu-Daudé wrote:
>
> On 31/5/24 16:11, Dr. David Alan Gilbert wrote:
> > * Don Porter (por...@cs.unc.edu) wrote:
> >> The new "info pg" monitor command prints the current page table,
> >> including virtual address ranges, flag bits, and snippets of physica
On Sat, Jun 01, 2024 at 09:05:41AM +0200, Thomas Huth wrote:
> The latest version of Clang (version 18 from Fedora 40) now reports
> bad function pointer casts as undefined behavior. Unfortunately, we are
> still doing this in quite a lot of places in the QEMU code and some of
> them are not easy t
On Sat, Jun 01, 2024 at 09:05:42AM +0200, Thomas Huth wrote:
> Beside g++ we also need the mingw-w64-tools for properly building
> the code in qga/vss-win32/ , so let's install that package now, too.
>
> Signed-off-by: Thomas Huth
> ---
> tests/lcitool/projects/qemu-win-installer.yml | 1 +
> 1
On Sat, Jun 01, 2024 at 09:05:43AM +0200, Thomas Huth wrote:
> Run "make lcitool-refresh" to update the dockerfiles with the recent
> changes to the lcitool.
>
> Signed-off-by: Thomas Huth
> ---
> tests/docker/dockerfiles/alpine.docker | 4 ++--
> tests/docker/dockerfiles/fedora-win6
The Intel manual states, "Move lower 16 bits of r/m64 to segment register,"
which is somewhat ambiguous. Therefore, I have written the following test to
verify this.
#include
#include
#include
#include
#include
int main (int argc, char** argv) {
uint16_t gs;
int ps = getpagesize();
Stefano Garzarella writes:
> On Wed, May 29, 2024 at 04:50:20PM GMT, Markus Armbruster wrote:
>>Stefano Garzarella writes:
>>
>>> shm_open() creates and opens a new POSIX shared memory object.
>>> A POSIX shared memory object allows creating memory backend with an
>>> associated file descriptor
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700 support
>
> @@ -670,7 +670,7 @@ static const MemoryRegionOps
> >> aspeed_smc_flash_ops
> = {
> .endianness = DEVICE_LITTLE_ENDIAN,
> .valid = {
>
On 6/3/24 11:49, Jamin Lin wrote:
Hi Cedric,
From: Cédric Le Goater
Subject: Re: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700 support
@@ -670,7 +670,7 @@ static const MemoryRegionOps
aspeed_smc_flash_ops
= {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
xsave.flat checks that "executing the XSETBV instruction causes a general-
protection fault (#GP) if ECX = 0 and EAX[2:1] has the value 10b". QEMU allows
that option, so the test fails. Add the condition.
Cc: qemu-sta...@nongnu.org
Fixes: 892544317fe ("target/i386: implement XSAVE and XRSTOR of
On 6/3/24 10:50, Akihiko Odaki wrote:
> On 2024/06/03 16:56, Michal Prívozník wrote:
>> On 6/2/24 08:26, Akihiko Odaki wrote:
>>> On 2024/06/01 0:46, Philippe Mathieu-Daudé wrote:
On 31/5/24 17:10, Michal Privoznik wrote:
> The unspoken premise of qemu_madvise() is that errno is set on
>>>
On 03/06/2024 08:10, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> From: Yi Liu
>
> Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU.
> In set call, a ne
On Wed, May 29, 2024 at 01:31:38PM -0400, Steven Sistare wrote:
> On 5/28/2024 5:12 PM, Peter Xu wrote:
> > On Mon, Apr 29, 2024 at 08:55:26AM -0700, Steve Sistare wrote:
> > > Allocate anonymous memory using memfd_create if the memfd-alloc machine
> > > option is set.
> > >
> > > Signed-off-by: S
On Mon, Jun 3, 2024 at 7:47 AM Fea.Wang wrote:
> Loading a description from memory may cause a bus-error. In this
> case, the DMA should stop working, set the error flag, and return
> the error value.
>
> Signed-off-by: Fea.Wang
>
Hi Fea,
I've got a couple of small comments:
---
> hw/dma/x
On Thu, May 23, 2024 at 04:05:31PM -0300, Fabiano Rosas wrote:
> When the "file:" migration support was added we missed the special
> case in the qemu_open_old implementation that allows for a particular
> file name format to be used to refer to a set of file descriptors that
> have been previously
On Mon, Jun 3, 2024 at 7:48 AM Fea.Wang wrote:
> When calling the loading a description function, it should be noticed
> that the function may return a failure value. Breaking the loop is one
> of the possible ways to handle it.
>
> Signed-off-by: Fea.Wang
>
Looks good, a nitpick comment, I wo
On Thu, May 23, 2024 at 04:05:32PM -0300, Fabiano Rosas wrote:
> When doing file migration, QEMU accepts an offset that should be
> skipped when writing the migration stream to the file. The purpose of
> the offset is to allow the management layer to put its own metadata at
> the start of the file.
On Mon, Jun 3, 2024 at 7:48 AM Fea.Wang wrote:
> Due to a description loading failure, adding a trace log makes observing
> the DMA behavior easy.
>
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Fea.Wang
> ---
> hw/dma/trace-events| 3 +++
> hw/dma/xilinx_axidma.c | 3 +++
> 2 files
Hi
On Thu, May 30, 2024 at 3:05 PM Gerd Hoffmann wrote:
> In case the display surface uses a shared buffer (i.e. uses vga vram
> directly instead of a shadow) go unshare the buffer before clearing it.
>
> This avoids vga memory corruption, which in turn fixes unblanking not
> working properly wi
Incorrect $SUBJECT - it claims to be removing monitor_fdset_dup_fd_add
but actually removes monitor_fdset_dup_fd_find.
On Thu, May 23, 2024 at 04:05:34PM -0300, Fabiano Rosas wrote:
> From: Peter Xu
>
> This function is not needed, one remove function should already work.
> Clean it up.
>
> Her
On Mon, Jun 3, 2024 at 7:48 AM Fea.Wang wrote:
> Fix the transmission return size because not all bytes could be
> transmitted successfully. So, return a successful length instead of a
> constant value.
>
>
How did you test this patch, on Linux or something else? I have some
memory that we had so
On Thu, May 23, 2024 at 04:05:46PM -0300, Fabiano Rosas wrote:
> Add support for setting/clearing the O_DIRECT flag on a file
> descriptor. This will be used for enabling O_DIRECT in the main
> migration channel when multifd is not in use.
>
> Signed-off-by: Fabiano Rosas
> ---
> include/io/chan
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700 support
>
> On 6/3/24 11:49, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> From: Cédric Le Goater
> >> Subject: Re: [SPAM] Re: [PATCH v4 09/16] aspeed/smc: Add AST2700
> >> support
> >>
> >> @@
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v6 18/19] intel_iommu: Implement
>[set|unset]_iommu_device() callbacks
>
>
>On 03/06/2024 08:10, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this
>email comes from a
On Tue, May 28, 2024 at 11:54:56AM +0200, Gerd Hoffmann wrote:
> Add deprecation_note field (string) to ObjectClass.
> Add deprecated bool to ObjectTypeInfo, report in 'qom-list-types'.
> Print the note when listing devices via '-device help'.
>
> Signed-off-by: Gerd Hoffmann
> ---
> include/qom
Fiona Ebner writes:
> In the context of backup fleecing, discarding the source will not work
> when the fleecing image has a larger granularity than the one used for
> block-copy operations (can happen if the backup target has smaller
> cluster size), because cbw_co_pdiscard_snapshot() will align
From: Clément Léger
The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number t
From: Cheng Yang
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.
Signed-off-by: Cheng Yang
Reviewed-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
hw/riscv/boot.c | 4 ++--
1 file changed, 2 i
From: "yang.zhang"
Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: yang.zhang
Cc: qemu-stable
Message-ID: <20240409014445.278-1-gao
u.git tags/pull-riscv-to-apply-20240603
for you to fetch changes up to 915758c537b5fe09575291f4acd87e2d377a93de:
disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (2024-06-03 11:12:12
+1000)
RISC-V PR for 9.1
* APLICs
On 2024/06/03 19:07, Michal Prívozník wrote:
On 6/3/24 10:50, Akihiko Odaki wrote:
On 2024/06/03 16:56, Michal Prívozník wrote:
On 6/2/24 08:26, Akihiko Odaki wrote:
On 2024/06/01 0:46, Philippe Mathieu-Daudé wrote:
On 31/5/24 17:10, Michal Privoznik wrote:
The unspoken premise of qemu_madvi
From: Jason Chien
Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240328022343.6871-2-jason.ch...@sif
From: Daniel Henrique Barboza
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stor
From: Andrew Jones
The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.
Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (
From: Huang Tao
In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
From: Daniel Henrique Barboza
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fau
From: Daniel Henrique Barboza
raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.
There's no mention in the spec about guest page fault being a higher
priority that PMP f
From: Alistair Francis
Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.
Reported-by: Eric DeVolder
Signed-off-by: Alistair Francis
Fixes: ea10325917 ("RISC-V Disassemble
From: Jason Chien
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
Reviewed-
From: Jason Chien
In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-
From: Christoph Müllner
The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
An important property of this patch is, that the th.sxstatus MAEE fiel
From: Yong-Xuan Wang
In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number a
From: Daniel Henrique Barboza
SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.
The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.
As far as K
From: Max Chou
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-
From: Max Chou
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Messag
From: Daniel Henrique Barboza
Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.
Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting '
On 1/6/24 09:05, Thomas Huth wrote:
Beside g++ we also need the mingw-w64-tools for properly building
the code in qga/vss-win32/ , so let's install that package now, too.
Signed-off-by: Thomas Huth
---
tests/lcitool/projects/qemu-win-installer.yml | 1 +
1 file changed, 1 insertion(+)
Revi
From: Andrew Jones
Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of th
From: Max Chou
The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.
The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
in
From: Alexei Filippov
Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation
but
failed pmp check.
In this case w
From: Alistair Francis
When running the instruction
```
cbo.flush 0(x0)
```
QEMU would segfault.
The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.
In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer m
Fiona Ebner writes:
> In the context of backup fleecing, discarding the source will not work
> when the fleecing image has a larger granularity than the one used for
> block-copy operations (can happen if the backup target has smaller
> cluster size), because cbw_co_pdiscard_snapshot() will align
From: Yangyu Chen
This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.
Signed-off-by: Yangyu Chen
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to
riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei
Revie
From: Max Chou
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Cc: qemu-stable
Message-ID: <20240322092600.1198921-4-max.c...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_t
From: Daniel Henrique Barboza
Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if
From: Rob Bradford
This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.
Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.
Signed-off-by: Rob Bradford
Reviewed-by: Andrew Jones
R
From: Huang Tao
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling o
Hi Zhenzhong,
On 6/3/24 08:10, Zhenzhong Duan wrote:
> Utilize range_get_last_bit() to get host IOMMU address width and
> package it in HostIOMMUDeviceCaps for query with .get_cap().
>
> Signed-off-by: Zhenzhong Duan
> ---
> hw/vfio/container.c | 26 ++
> 1 file changed,
Philippe Mathieu-Daudé writes:
> Remove MEM_UNPLUG_ERROR and 'vcpu' field in TRACE events,
> all deprecated since long enough.
Thank you!
Reviewed-by: Markus Armbruster
On 30/5/24 09:04, Philippe Mathieu-Daudé wrote:
The 'blacklist' argument / config key are deprecated since commi
Typo "commit".
582a098e6c ("qga: Replace 'blacklist' command line and config file
options by 'block-rpcs'"), time to remove them.
Signed-off-by: Philippe Mathieu-Daudé
---
docs
On Mon, May 27, 2024 at 01:49:41PM +0300, Michael Tokarev wrote:
> Hi!
>
> Noticed today that a rebuild of basically the same tree (a few commits apart)
> in CI result in just 11% hit rate of ccache:
>
> https://gitlab.com/mjt0k/qemu/-/jobs/6947445337#L5054
>
> while it should be near 100%. Wha
On 30/5/24 21:42, Alex Bennée wrote:
Aside from the round robin threads this is all common code. By
moving the halt_cond setup we also no longer need hacks to work around
the race between QOM object creation and thread creation.
It is a little ugly to free stuff up for the round robin thread but
On Mon, Jun 3, 2024 at 11:53 AM Paolo Bonzini wrote:
>
> On 6/2/24 12:38, Will Gyda wrote:
> > i386: removes microvm from default build since microvm doesn't support Xen
> > accel.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2294
>
> This is already done in (what will be) QEMU
On Mon, May 27, 2024 at 02:38:08PM +0300, Michael Tokarev wrote:
> 27.05.2024 14:19, Thomas Huth wrote:
> > On 27/05/2024 12.49, Michael Tokarev wrote:
> > > Hi!
> > >
> > > Noticed today that a rebuild of basically the same tree (a few commits
> > > apart)
> > > in CI result in just 11% hit rate
On 30/5/24 21:42, Alex Bennée wrote:
The thread_id isn't valid until the threads are created. There is no
point setting it here. The only thing that cares about the thread_id
is qmp_query_cpus_fast.
Signed-off-by: Alex Bennée
---
cpu-target.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-b
On 30/5/24 21:42, Alex Bennée wrote:
Now the condition variable is initialised early on we don't need to go
through hoops to avoid calling async_run_on_cpu.
Signed-off-by: Alex Bennée
---
plugins/core.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/plugins/core.c b
Hi Zhenzhong,
On 6/3/24 08:10, Zhenzhong Duan wrote:
> It calls iommufd_backend_get_device_info() to get host IOMMU
> related information and translate it into HostIOMMUDeviceCaps
> for query with .get_cap().
>
> Introduce macro VTD_MGAW_FROM_CAP to get MGAW which equals to
> (aw_bits - 1).
>
> Si
On 30/5/24 21:42, Alex Bennée wrote:
Make the relationship between CPUState, ArchCPU and cpu_env a bit
clearer in the kdoc comments.
Signed-off-by: Alex Bennée
---
include/hw/core/cpu.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daud
On 6/3/24 08:10, Zhenzhong Duan wrote:
> Suggested-by: Cédric Le Goater
> Signed-off-by: Zhenzhong Duan
> ---
> backends/iommufd.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/backends/iommufd.c b/backends/iommufd.c
> index c7e969d6f7..f2f7a762a0 100644
>
On Wed, May 29, 2024 at 07:15:37AM +0200, Philippe Mathieu-Daudé wrote:
> Last commit removed the last non-NULL use of DEFINE_I440FX_MACHINE
> 3rd parameter. 'compatfn' is now obsolete, remove it.
>
> Suggested-by: Daniel P. Berrangé
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/pc_pi
On Thu, May 30, 2024 at 01:22:11PM +0100, Mark Cave-Ayland wrote:
> On 30/05/2024 12:40, BALATON Zoltan wrote:
>
> > On Thu, 30 May 2024, Gerd Hoffmann wrote:
> > > stdvga is the much better option.
> > >
> > > Signed-off-by: Gerd Hoffmann
> > > ---
> > > hw/display/cirrus_vga.c | 1 +
> > >
On Thu, May 30, 2024 at 01:27:14PM +0200, Gerd Hoffmann wrote:
> Add deprecation_note field (string) to ObjectClass.
> Add deprecated bool to ObjectTypeInfo, report in 'qom-list-types'.
> Print the note when listing devices via '-device help'.
>
> Signed-off-by: Gerd Hoffmann
> ---
> include/qom
On Thu, 30 May 2024 10:34:55 +0800
Jason Wang wrote:
> >
> > IMHO changing the semantic of the VHOST_GET_FEATURES ioctl is not viable,
> > but also not necessary. What I am proposing is changing the (in QEMU)
> > logic of processing the features returned by VHOST_GET_FEATURES, while
> > preservin
On Fri, May 31, 2024 at 01:04:59PM -0500, Eric Blake wrote:
> Prevent regressions when using NBD with TLS in the presence of
> iothreads, adding coverage the fix to qio channels made in the
> previous patch.
>
> The shell function pick_unused_port() was copied from
> nbdkit.git/tests/functions.sh.
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