On Thu, 30 May 2024 at 15:25, Nicholas Piggin wrote:
> There is no need to use /dev/shm for file-backed memory devices, and
> on Gitlab CI the tmpfs mount is too small to be usable for migration
> tests. Switch to using a regular file in /tmp/ which will usually have
> more space available.
...
>
On 30/5/24 21:42, Alex Bennée wrote:
Originally I tried to move where vCPU thread initialisation to later
in realize. However pulling that thread (sic) got gnarly really
quickly. It turns out some steps of CPU realization need values that
can only be determined from the running vCPU thread.
FYI
On Thu, 30 May 2024 at 13:17, Nicholas Piggin wrote:
> diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> /*
> - * On ppc64, the test only works with kvm-hv, but not with kvm-pr and TCG
> - * is touchy due to race conditions on dirty bits (especially on PPC for
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case except for posix_madvise() which
is documented to return either zero (on success) or a positive
error number. This means, we must set errno ourselves. And while
at it, make the function return a negative
If user sets .merge or .dump attributes qemu_madvise() is called
with corresponding advice. But it is never checked for failure
which may mislead users into thinking the attribute is set
correctly. Report an appropriate error.
Signed-off-by: Michal Privoznik
---
backends/hostmem.c | 36 +
If memory-backend-{file,ram} has a size that's not aligned to
underlying page size it is not only wasteful, but also may lead
to hard to debug behaviour. For instance, in case
memory-backend-file and hugepages, madvise() and mbind() fail.
Rightfully so, page is the smallest unit they can work with.
v2 of:
https://lists.gnu.org/archive/html/qemu-devel/2024-05/msg05659.html
diff to v1:
- patch 2/4 is new
- Errors are reported instead of warnings on failed qemu_madvise()
- Instead of rounding up value passed to qemu_madvise()/mbind() an error
is reported
Michal Privoznik (4):
osdep: Make
Not every OS is capable of madvise() or posix_madvise() even. In
that case, errno should be set to ENOSYS as it reflects the cause
better. This also mimic what madvise()/posix_madvise() would
return if kernel lacks corresponding syscall (e.g. due to
configuration).
Signed-off-by: Michal Privoznik
On Thu, 30 May 2024 at 13:17, Nicholas Piggin wrote:
>
> Reviewed-by: Thomas Huth
> Signed-off-by: Nicholas Piggin
> ---
* No commit log message?
---
- Prasad
Pointer, returned from function 'spapr_vio_find_by_reg', may be NULL and is
dereferenced immediately after.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Oleg Sviridov
---
v2: Debug message added
hw/net/spapr_llan.c | 6 ++
1 file changed, 6 insertions(+)
On 31/5/24 00:06, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/sysemu/qtest.h | 3 ---
accel/qtest/qtest.c| 12
system/qtest.c | 12
3 files changed, 12 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hello Jamin,
I refer to versal_create_apu_gic function,
https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
and updated aspeed_soc_ast2700_gic as following.
If you have any concerned about the new changes, please let me know.
Thanks-Jamin
static bool aspeed_soc_ast2700_gic(Devic
On 31/5/24 09:28, Michal Privoznik wrote:
Not every OS is capable of madvise() or posix_madvise() even. In
that case, errno should be set to ENOSYS as it reflects the cause
better. This also mimic what madvise()/posix_madvise() would
return if kernel lacks corresponding syscall (e.g. due to
confi
On 31/5/24 09:28, Michal Privoznik wrote:
If user sets .merge or .dump attributes qemu_madvise() is called
with corresponding advice. But it is never checked for failure
which may mislead users into thinking the attribute is set
correctly. Report an appropriate error.
Signed-off-by: Michal Privo
On 31.05.24 09:28, Michal Privoznik wrote:
Not every OS is capable of madvise() or posix_madvise() even. In
that case, errno should be set to ENOSYS as it reflects the cause
better. This also mimic what madvise()/posix_madvise() would
return if kernel lacks corresponding syscall (e.g. due to
conf
Hi Michal,
On 31/5/24 09:29, Michal Privoznik wrote:
If memory-backend-{file,ram} has a size that's not aligned to
underlying page size it is not only wasteful, but also may lead
to hard to debug behaviour. For instance, in case
memory-backend-file and hugepages, madvise() and mbind() fail.
Righ
On 22.05.24 19:23, Dorjoy Chowdhury wrote:
Hi Daniel,
Thanks for reviewing.
On Wed, May 22, 2024 at 9:32 PM Daniel P. Berrangé wrote:
On Sat, May 18, 2024 at 02:07:52PM +0600, Dorjoy Chowdhury wrote:
An EIF (Enclave Image Format)[1] image is used to boot an AWS nitro
enclave[2] virtual machi
Hi Michal,
On 31/5/24 09:28, Michal Privoznik wrote:
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case except for posix_madvise() which
is documented to return either zero (on success) or a positive
error number.
Watch out, Linux:
RETURN VALUE
On 31/5/24 09:53, David Hildenbrand wrote:
On 31.05.24 09:28, Michal Privoznik wrote:
Not every OS is capable of madvise() or posix_madvise() even. In
that case, errno should be set to ENOSYS as it reflects the cause
better. This also mimic what madvise()/posix_madvise() would
return if kernel l
On 31.05.24 09:57, Philippe Mathieu-Daudé wrote:
Hi Michal,
On 31/5/24 09:28, Michal Privoznik wrote:
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case except for posix_madvise() which
is documented to return either zero (on success) or a positive
e
On 31/5/24 10:01, David Hildenbrand wrote:
On 31.05.24 09:57, Philippe Mathieu-Daudé wrote:
Hi Michal,
On 31/5/24 09:28, Michal Privoznik wrote:
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case except for posix_madvise() which
is documented to ret
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
>
>
> Hello Jamin,
> > I refer to versal_create_apu_gic function,
> https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
> > and updated aspeed_soc_ast2700_gic as following.
> > If y
Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to
become wrongly sorted when executing g_slist_sort. Fix this by always
returning -1 or 1 from g_cmp_ids based on the ID comparison instead.
Also, if two message IDs are the same, sort them by using their index and
transmit
在 2024/5/31 下午1:34, Jiaxun Yang 写道:
在2024年5月31日五月 上午2:52，gaosong写道：
在 2024/5/30 下午9:16, Jiaxun Yang 写道:
在2024年5月30日五月 下午2:00，gaosong写道：
[...]
FYI, the test does not seem to work anymore - apparently the binaries
have changed and now the hashes do not match anymore. Could you please
update it?
Philippe Mathieu-Daudé writes:
> On 30/5/24 21:42, Alex Bennée wrote:
>> Originally I tried to move where vCPU thread initialisation to later
>> in realize. However pulling that thread (sic) got gnarly really
>> quickly. It turns out some steps of CPU realization need values that
>> can only be d
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
According to Chapter "CPUID Virtualization" in TDX module spec, CPUID
bits of TD can be classified into 6 types:
1 | As configured | configurable by VMM, independent of native value
Brian Cain writes:
> On 5/30/2024 6:23 AM, Alex Bennée wrote:
>> It's a pain when you come back to a code base you haven't touched in a
>> while and realise whatever indent settings you were using having
>> carried over. Add an editorconfig and be done with it.
>>
>> Signed-off-by: Alex Bennée
>
Hi Cedric,
> From: Cédric Le Goater
> On 5/27/24 10:02, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2
Pierrick Bouvier writes:
> On 5/30/24 12:42, Alex Bennée wrote:
>> Originally I tried to move where vCPU thread initialisation to later
>> in realize. However pulling that thread (sic) got gnarly really
>> quickly. It turns out some steps of CPU realization need values that
>> can only be determi
On 31.05.24 10:12, Philippe Mathieu-Daudé wrote:
On 31/5/24 10:01, David Hildenbrand wrote:
On 31.05.24 09:57, Philippe Mathieu-Daudé wrote:
Hi Michal,
On 31/5/24 09:28, Michal Privoznik wrote:
The unspoken premise of qemu_madvise() is that errno is set on
error. And it is mostly the case exc
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
'xen_blkdev_ops' was removed in commit 19f87870ba ("xen: remove
the legacy 'xen_disk' backend"), 'xen_netdev_ops' in commit
25967ff69f ("hw/xen: update Xen PV NIC to XenDevice model") and
'xen_console_ops' in commit 9b77374690 ("hw/xen: update Xe
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
XenDevOps @ops is not updated, mark it const.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/xen/xen_pvdev.h | 2 +-
hw/xen/xen-legacy-backend.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Paul Durrant
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
XenDevOps @ops is not updated, mark it const.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/xen/xen-legacy-backend.h | 2 +-
hw/xen/xen-legacy-backend.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed
On 31.05.24 09:28, Michal Privoznik wrote:
If user sets .merge or .dump attributes qemu_madvise() is called
with corresponding advice. But it is never checked for failure
which may mislead users into thinking the attribute is set
correctly. Report an appropriate error.
Signed-off-by: Michal Priv
QEMU now requires an x86-64-v2 host, which has SSE2.
Use it freely in buffer_is_zero.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 -
util/bufferiszero.c | 2 +-
util/cpuinfo-i386.c | 1 -
3 files changed, 1 insertion(+), 3 deletions(-)
diff --
The only user was the SSE4.1 variant of buffer_is_zero, which has
been removed; code to compute CPUINFO_SSE4 is dead.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 -
util/cpuinfo-i386.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/host/include/i386/h
x86-64-v2 processors were released in 2008, assume that we have one.
This provides CMOV on 32-bit processors, and also POPCNT and various
vector ISA extensions.
Paolo
Paolo Bonzini (6):
host/i386: nothing looks at CPUINFO_SSE4
meson: assume x86-64-v2 baseline ISA
host/i386: assume presence
QEMU now requires an x86-64-v2 host, which has SSSE3 instructions
(notably, PSHUFB which is used by QEMU's AES implementation).
Do not bother checking it.
Signed-off-by: Paolo Bonzini
---
util/cpuinfo-i386.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/cpuinfo-i38
x86-64-v2 processors were released in 2008, assume that we have one.
Unfortunately there is no GCC flag to enable all the features
without disabling what came after; so enable them one by one.
Signed-off-by: Paolo Bonzini
---
meson.build | 10 +++---
1 file changed, 7 insertions(+), 3 deleti
QEMU now requires an x86-64-v2 host, which always has CMOV.
Use it freely in TCG generated code.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 -
util/cpuinfo-i386.c | 1 -
tcg/i386/tcg-target.c.inc| 15 +--
3 files changed, 1 insertion(
QEMU now requires an x86-64-v2 host, which has the POPCNT instruction.
Use it freely in TCG-generated code.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 -
tcg/i386/tcg-target.h| 5 ++---
util/cpuinfo-i386.c | 1 -
3 files changed, 2 insertions(+
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
tdx_cpuid_lookup[].tdx_fixed0/1 is QEMU maintained data which reflects
TDX restrictions regrading what bits are fixed by TDX module.
It's retrieved from TDX spec and static. However, TDX may evolve and
change some fixed fields to configurable in the futu
On 2/29/2024 2:36 PM, Xiaoyao Li wrote:
Due to the fact that Intel-PT virtualization support has been broken in
QEMU since Sapphire Rapids generation[1], below warning is triggered when
luanching TD guest:
warning: host doesn't support requested feature: CPUID.07H:EBX.intel-pt [bit
25]
Be
Trusted Firmware 2.11 got released, EDK2 202405 got released as well.
Both were built for QEMU CI and proper patch is now in arm.next queue.
So all requirements to move from legacy 62.5MHz to armv8.6-ready 1GHz
frequency are fulfiled.
Marcin Juszkiewicz (1):
hw/arm/sbsa-ref: switch to 1GHz time
Updated firmware for QEMU CI is already in merge queue so we can move
platform to be future proof.
All supported cpus work fine with 1GHz timer frequency when firmware is
fresh enough.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 12
1 file changed, 4 insertions(+), 8
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
Keep XenDevOps structures in .rodata.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/xen/xen-legacy-backend.h | 8
hw/9pfs/xen-9p-backend.c| 2 +-
hw/display/xenfb.c | 4 ++--
hw/usb/xen-usb.c
Hi Shiva,
>-Original Message-
>From: Shiva sagar Myana
>Sent: Friday, May 31, 2024 1:56 PM
>To: Iglesias, Francisco ; jasow...@redhat.com;
>qemu-devel@nongnu.org; p...@cmp.felk.cvut.cz
>Cc: peter.mayd...@linaro.org; Boddu, Sai Pavan ;
>Myana, Shivasagar
>Subject: [QEMU][master][PATCH v2
On Thu, 30 May 2024 at 18:37, Richard Henderson
wrote:
>
> On 5/30/24 05:51, Peter Maydell wrote:
> >> @@ -87,13 +87,13 @@ sub progress_update($)
> >> my $barlen = int($proglen * $done / $progmax);
> >> if ($barlen != $lastprog) {
> >> $lastprog = $barlen;
> >> -print
在 2024/5/30 上午10:15, Bibo Mao 写道:
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configure GPEX pci host controller
information
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
From: Paolo Bonzini
Prepare for moving the calls to xen_be_register() under the
control of xen_bus_init(), using the normal xen_backend_init()
method that is used by the "modern" backends.
This requires the xenstore global variable to be initi
On Fri, 31 May 2024 at 05:20, Itaru Kitayama wrote:
>
>
>
> > On May 30, 2024, at 22:30, Philippe Mathieu-Daudé wrote:
> >
> > Cc'ing more developers
> >
> > On 30/5/24 06:30, Itaru Kitayama wrote:
> >> Hi,
> >> When I see a Realm VM creation fails with:
> >> Unexpected error in rme_configure_one
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
From: Paolo Bonzini
It is okay to register legacy backends in the middle of xen_bus_init().
All that the registration does is record the existence of the backend
in xenstore.
This makes it possible to remove them from the build without introdu
在 2024/5/28 下午4:21, Bibo Mao 写道:
Add numa test case for loongarch system, it passes to run
with command "make check-qtest".
Signed-off-by: Bibo Mao
---
tests/qtest/meson.build | 2 +-
tests/qtest/numa-test.c | 53 +
2 files changed, 54 insertions(+),
On 10/05/2024 11:49, Philippe Mathieu-Daudé wrote:
Align the framebuffer backend with the other legacy ones,
register it via xen_backend_init() when '-vga xenfb' is
used. It is safe because MODULE_INIT_XEN_BACKEND is called
in xen_bus_realize(), long after CLI processing initialized
the vga_inter
On Fri, 31 May 2024 at 09:54, Alex Bennée wrote:
>
> Brian Cain writes:
> > Related: would a .clang-format file also be useful? git-clang-format
> > can be used to apply formatting changes only on the code that's been
> > changed.
>
> As a pre-commit hook? Or via something like clangd?
I think l
On Wed, 29 May 2024 22:17:44 +0200
Nam Cao wrote:
> Set link width to x1 and link speed to 2.5 Gb/s as specified by the
> datasheet. Without this, these fields in the link status register read
> zero, which is incorrect.
>
> This problem appeared since 3d67447fe7c2 ("pcie: Fill PCIESlot link fie
Hi Itaru,
On Fri, May 31, 2024 at 10:57:13AM +0100, Peter Maydell wrote:
> On Fri, 31 May 2024 at 05:20, Itaru Kitayama wrote:
> >
> >
> >
> > > On May 30, 2024, at 22:30, Philippe Mathieu-Daudé
> > > wrote:
> > >
> > > Cc'ing more developers
> > >
> > > On 30/5/24 06:30, Itaru Kitayama wrote:
On Fri, May 31, 2024 at 11:14:00AM +0100, Jonathan Cameron wrote:
> On Wed, 29 May 2024 22:17:44 +0200
> Nam Cao wrote:
>
> > Set link width to x1 and link speed to 2.5 Gb/s as specified by the
> > datasheet. Without this, these fields in the link status register read
> > zero, which is incorrect
On Tue, 30 Apr 2024 at 15:00, Peter Maydell wrote:
>
> FEAT_WFxT introduces new instructions WFIT and WFET, which are like
> the existing WFI and WFE but allow the guest to pass a timeout value
> in a register. The instructions will wait for an interrupt/event as
> usual, but will also stop waiti
On 31/5/24 09:46, Cédric Le Goater wrote:
Hello Jamin,
I refer to versal_create_apu_gic function,
https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
and updated aspeed_soc_ast2700_gic as following.
If you have any concerned about the new changes, please let me know.
Thanks-Jamin
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
>
> -#define TYPE_SEV_GUEST "sev-guest"
> -OBJECT_DECLARE_SIMPLE_TYPE(SevGuestState, SEV_GUEST)
>
> +OBJECT_DECLARE_TYPE(SevCommonState, SevCommonStateClass, SEV_COMMON)
> +OBJECT_DECLARE_TYPE(SevGuestState, SevGuestStateClass, SEV_GUEST)
A sepa
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
> +++ b/qapi/qom.json
> @@ -928,6 +928,61 @@
> '*policy': 'uint32',
> '*handle': 'uint32',
> '*legacy-vm-type': 'bool' } }
Nit, missing empty line here.
> +##
> +# @SevSnpGuestProperties:
> +#
[...]
> d
On 24-05-31 11:34:54, Changqi Lu wrote:
> Add reservation acquire, reservation register,
> reservation release and reservation report commands
> in the nvme device layer.
>
> By introducing these commands, this enables the nvme
> device to perform reservation-related tasks, including
> querying ke
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
> +/*
> + * SEV uses these notifiers to register/pin pages prior to guest use,
> + * but SNP relies on guest_memfd for private pages, which has it's
> + * own internal mechanisms for registering/pinning private memory.
> + */
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
> +} else if (x86ms->smm == ON_OFF_AUTO_ON) {
> +error_setg(errp, "SEV-SNP does not support SMM.");
> +ram_block_discard_disable(false);
Unnecessary line, there is no matching ram_block_discard_disable(true).
Paolo
On 5/31/24 11:08, David Hildenbrand wrote:
> On 31.05.24 10:12, Philippe Mathieu-Daudé wrote:
>> On 31/5/24 10:01, David Hildenbrand wrote:
>>> On 31.05.24 09:57, Philippe Mathieu-Daudé wrote:
Hi Michal,
On 31/5/24 09:28, Michal Privoznik wrote:
> The unspoken premise of qemu_mad
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
>
> Add launch_update_data() in SevCommonStateClass and
> invoke as sev_launch_update_data() for SEV object.
>
> Signed-off-by: Pankaj Gupta
> ---
> target/i386/sev.c | 15 +++
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> d
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
>
> From: Dov Murik
>
> Move the declaration of PaddedSevHashTable before SevSnpGuest so
> we can add a new such field to the latter.
> No functional change intended.
>
> Signed-off-by: Dov Murik
> Signed-off-by: Michael Roth
> Signed-off-by:
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
>
> From: Dov Murik
>
> In SNP, the hashes page designated with a specific metadata entry
> published in AmdSev OVMF.
>
> Therefore, if the user enabled kernel hashes (for measured direct boot),
> QEMU should prepare the content of hashes table,
On Thu, May 30, 2024 at 1:16 PM Pankaj Gupta wrote:
>
> These patches implement SEV-SNP base support along with CPUID enforcement
> support for QEMU, and are also available at:
>
> https://github.com/pagupta/qemu/tree/snp_v4
>
> Latest version of kvm changes are posted here [2] and also queued in
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
> if (bios_size <= 0 ||
> (bios_size % 65536) != 0) {
> -goto bios_error;
> +if (!machine_require_guest_memfd(MACHINE(x86ms))) {
> +g_warning("%s: Unaligned BIOS size %d", __func__, bios_size);
> +
Ask the ConfidentialGuestSupport object whether to use guest_memfd
for KVM-backend private memory. This bool can be set in instance_init
(or user_complete) so that it is available when the machine is created.
Signed-off-by: Paolo Bonzini
---
include/exec/confidential-guest-support.h | 5 +
On Thu, May 30, 2024 at 1:17 PM Pankaj Gupta wrote:
>
> From: Michael Roth
>
> Current SNP guest kernels will attempt to access these regions with
> with C-bit set, so guest_memfd is needed to handle that. Otherwise,
> kvm_convert_memory() will fail when the guest kernel tries to access it
> and
From: Richard Henderson
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-7-richard.hender...@linaro.org
Signed-off-by: Peter Ma
From: Sebastian Huber
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Se
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-20-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/arm/tcg
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-28-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 ++
2 files
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-21-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 6 --
target/arm/tcg/translate.h | 5 ++
target/arm/tcg/gengvec.c
From: Richard Henderson
This eliminates the last uses of these neon helpers.
Incorporate the MO_64 expanders as an option to the vector expander.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-6-richard.hender...@linaro.org
Signed-off-by: Peter Ma
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-26-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 11 +++
2 files changed, 5 in
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4 +++
target/arm/tcg/translate-a64.c | 48 -
From: David Hubbard
This changes the ohci validation to not assert if invalid data is fed to the
ohci controller. The poc in https://bugs.launchpad.net/qemu/+bug/1907042 and
migrated to bug #303 does the following to feed it a SETUP pid (valid)
at an EndPt of 1 (invalid - all SETUP pids must be a
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 ++
target/arm/tcg/translate-a64.c | 40 +-
From: Richard Henderson
These are the last instructions within disas_simd_three_reg_same
and disas_simd_scalar_three_reg_same, so remove them.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-32-richard.hender...@linaro.org
Signed-off-by: Peter Mayd
From: Richard Henderson
These are the only instructions in the 3 source scalar class.
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-33-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 10 ++
target
tags/pull-target-arm-20240531
for you to fetch changes up to 3c3c233677d4f2fe5f35c5d6d6e9b53df48054f4:
hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT (2024-05-31 11:26:00
+0100)
target-arm:
* hw/intc/arm_gic: Fix set pendi
From: Marcin Juszkiewicz
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
Reported-by: Marcin Juszkiewicz
Signed-off-by: Richard Henderson
Signed-off-by: Marcin Juszkiewicz
Message-id: 20240526204551.553282-1-richard.hender...@linaro.org
Reviewed-by: Pete
From: Richard Henderson
We already have a gvec helper for the operations, but we aren't
using it on the aa32 neon side. Create a unified expander for
use by both aa32 and aa64 translators.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-31-richard
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 11
target/arm/tcg/translate-a64.c | 96 +++--
The TCGCPUOps::cpu_exec_halt method is called from cpu_handle_halt()
when the CPU is halted, so that a target CPU emulation can do
anything target-specific it needs to do. (At the moment we only use
this on i386.)
The current specification of the method doesn't allow the target
specific code to d
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 22 +++---
2 files
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 8 ++
target/arm/tcg/translate.h | 4 +++
target/arm/tcg/neon-dp.
FEAT_WFxT introduces new instructions WFIT and WFET, which are like
the existing WFI and WFE but allow the guest to pass a timeout value
in a register. The instructions will wait for an interrupt/event as
usual, but will also stop waiting when the value of CNTVCT_EL0 is
greater than or equal to th
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-34-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 4 ++
target/arm/tcg/translate-a64.c | 108 ++--
From: Sebastian Huber
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the
corresponding Qemu device to the xilinx-zynq-a9 machine.
Signed-off-by: Sebastian Huber
Message-id: 20240524120837.10057-2-sebastian.hu...@embedded-brains.de
Reviewed-by: Peter Maydell
Signed-off-by:
From: Richard Henderson
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h| 16 +
target/arm/tcg/translate-a64.h | 6 ++
target/arm/tcg/gengvec64.c | 110 +
From: Richard Henderson
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-18-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 12 +++
target/arm/tcg/translate-a64.c | 132 ---
From: Richard Henderson
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/tcg/gengvec.c | 9 +
1 file changed, 9 insertions(+)
diff --gi
From: Richard Henderson
These are faux 2-operand instructions, reading from rd.
Sort them next to the other three-operand same insns for clarity.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20240528203044.612851-9-richard.hender...@linaro.org
Signed-off-by: Peter Ma
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20240528203044.612851-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/helper.h | 8
target/arm/tcg/translate.h | 4
target/arm/tcg/neon-
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