On 5/27/24 17:58, Philippe Mathieu-Daudé wrote:
Hi,
On 27/5/24 10:02, Jamin Lin wrote:
AST2700 fmc/spi controller's address decoding unit is 64KB
and only bits [31:16] are used for decoding. Introduce seg_to_reg
and reg_to_seg handlers for ast2700 fmc/spi controller.
In addition, adds ast2700 f
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: A
Introduce 'PnvChipClass::logical_pvr' to know corresponding logical PVR
of a PowerPC CPU.
This helps to have a one-to-one mapping between PVR and logical PVR for
a CPU, and used in a later commit to handle cases where PCR of two
generations of Power chip is same, which causes regressions with compa
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
--
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicho
Overview
Add support for Power11 pseries and powernv machine types, to emulate VMs
running on Power11.
As Power11 core is same as Power10, hence much of the code has been reused from
Power10.
Power11 was added in Linux in:
commit c2ed087ed35c ("powerpc: Add Power11 architected and
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Power11 has the same PCR (Processor Compatibility Register) value, as
Power10.
Due to this, QEMU considers Power11 as a valid compat-mode for Power10,
ie. earlier it was possible to run QEMU with '-M
pseries,max-compat-mode=power11 --cpu power10'
Same PCR also introduced a regression where `-M p
Add sPAPR CPU Core definition for Power11
Cc: David Gibson (reviewer:sPAPR (pseries))
Cc: Harsh Prateek Bora (reviewer:sPAPR (pseries))
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Ad
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
This will allow different settings and checks for different
machine types with later changes.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 35 ++-
1 file changed, 30 insertions(+), 5 deletions(-)
diff --
Hi Zhiwei,
On Tue, May 28, 2024 at 8:57 AM LIU Zhiwei wrote:
>
> Hi Alexandre,
>
> I have sent the patch set about Zabha before last week.
Sorry I did not check!
>
> https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15...@linux.alibaba.com/T/
>
> Welcome to review it and give comments.
On 5/28/24 09:05, Aditya Gupta wrote:
Skiboot/OPAL patches are in discussion upstream [1], with corresponding
commits in github repository [2].
Update skiboot.lid, with binary built from 'upstream_power11' branch
of skiboot repository with Power11 enablement patches [2].
---
This patch can be s
On 5/27/24 8:01 PM, Philippe Mathieu-Daudé wrote:
Hi Daniil,
On 21/5/24 10:08, Daniil Tatianin wrote:
Could you please take a look at this revision? I think I've taken
everyone's feedback into account.
Sorry for the delay, I missed your patch since you didn't Cc me
(Markus asked me to look a
This can be used to force-synchronize the time in guest after a long
stop-cont pause, which can be useful for serverless-type workload.
Also add a comment to highlight the fact that this (and one other QMP
command) only works for the MC146818 RTC controller.
Acked-by: Philippe Mathieu-Daudé
Sign
If the breakpoint belongs to the userspace then set the ret value.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the control flag
when t
This series implements QEMU KVM Guest Debug on RISC-V, with which we
could debug RISC-V KVM guest from the host side, using software
breakpoints.
This series is based on riscv-to-apply.next branch (v9.0.0) and is also
available at:
https://github.com/Du-Chao/alistair23-qemu/tree/riscv-to-apply.nex
To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
configs/targets/riscv64-softmmu.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/riscv64-softmmu.mak
b/configs/targets/riscv6
This series adds few updates to RISC-V ACPI namespace for virt platform.
1) PCI Link devices need to be created outside the scope of the PCI root
complex to ensure correct probe ordering by the OS. This matches the
example given in ACPI spec as well.
2) Add PLIC and APLIC as platform devices as w
PLIC and APLIC should be in namespace as well. So, add them using the
defined HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 832
RISC-V is going to use new HID RSCV0003 for generi UART. So, update the
HID.
Signed-off-by: Sunil V L
---
hw/riscv/virt-acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 47ec78e432..7f80368415 100644
---
Currently, PCI link devices (PNP0C0F) are always created within the
scope of the PCI root complex. However, RISC-V needs PCI link devices to
be outside the scope of the PCI host bridge to properly enable the probe
order. This matches the example given in the ACPI specification section
6.2.13.1 as w
Hi Stefan,
[snip]
> > diff --git a/scripts/simpletrace-rust/.rustfmt.toml
> > b/scripts/simpletrace-rust/.rustfmt.toml
> > new file mode 100644
> > index ..97a97c24ebfb
> > --- /dev/null
> > +++ b/scripts/simpletrace-rust/.rustfmt.toml
> > @@ -0,0 +1,9 @@
> > +brace_style = "AlwaysNe
Hello Aditya
On 5/28/24 09:05, Aditya Gupta wrote:
Power11 core is same as Power10, use the existing functionalities to
introduce a Power11 chip and machine, with Power10 chip as parent of
Power11 chip, thus going through similar class_init paths
This patch should come last, after all the POWE
On 5/28/24 09:10, Harsh Prateek Bora wrote:
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
This will allow different settings and checks for different
machine types with later changes.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 35 ++-
1 file chang
On 5/28/24 08:28, Harsh Prateek Bora wrote:
On 5/26/24 17:56, Nicholas Piggin wrote:
The timebase state machine is per per-core state and can be driven
by any thread in the core. It is currently implemented as a hack
where the state is in a CPU structure and only thread 0's state is
accessed b
If the breakpoint belongs to the userspace then set the ret value.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/
This series implements QEMU KVM Guest Debug on RISC-V, with which we
could debug RISC-V KVM guest from the host side, using software
breakpoints.
This series is based on riscv-to-apply.next branch (v9.0.0) and is also
available at:
https://github.com/Du-Chao/alistair23-qemu/tree/riscv-to-apply.nex
To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
configs/targets/riscv64-softmmu.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/targets/riscv64-softmmu.mak
b/configs/targets/riscv6
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the control flag
when t
> > +/*
> > + * Refer to the description of ALLOWED_TYPES in
> > + * scripts/tracetool/__init__.py.
>
> Please don't reference the Python implementation because this will not
> age well. It may bitrot if the Python code changes or if the Python
> implementation is deprecated then the source file w
Add loongarch virt machine to the graph. It is a modified copy of
the existing riscv virtmachine in riscv-virt-machine.c
It contains a generic-pcihost controller, and an extra function
loongarch_config_qpci_bus() to configure GPEX pci host controller
information, such as ecam and pio_base addresse
Add numa test case for loongarch system, it passes to run
with command "make check-qtest".
Signed-off-by: Bibo Mao
---
tests/qtest/meson.build | 2 +-
tests/qtest/numa-test.c | 53 +
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/tests/qte
> > +fn read_type(mut fobj: &File) -> Result
> > +{
> > +let mut tbuf = [0u8; 8];
> > +if let Err(e) = fobj.read_exact(&mut tbuf) {
> > +if e.kind() == ErrorKind::UnexpectedEof {
> > +return Ok(RecordType::Empty);
> > +} else {
> > +
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST
On 5/26/24 17:56, Nicholas Piggin wrote:
The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated topolo
I have not found much time to work on qemu due to being busy with
firmware (edk2 for the most part). Time to update the MAINTAINERS
file entries to match reality.
I drop spice, ui, audio and usb due to lack of time.
I drop virtio-gpu, I don't follow recent development (venus etc.)
close enough t
This patch adds a new board attribute 'v-eiointc'.
A value of true enables the virt extended I/O interrupt controller.
VMs working in kvm mode have 'v-eiointc' enabled by default.
Signed-off-by: Song Gao
---
include/hw/loongarch/virt.h | 1 +
target/loongarch/cpu.h | 1 +
hw/loongarch/vir
On LoongArch, IRQs can be routed to four vcpus with hardware extended
IRQ model. This patch adds the virt extension definition so that
the IRQ can route to 256 vcpus.
1.Extended IRQ model:
|
+---+ +-|+ +---+
Remove myself from virtio-gpu entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a0375627
Remove myself from spice and ui entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 37f2be
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 36
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 4db0d82dbd
Remove myself from usb entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Manos Pitsidianakis
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 58e44885ce94..a
Remove myself from audio (both devices and backend) entries.
Flip status to "Orphan" for entries which have nobody else listed.
Cc: Manos Pitsidianakis
Cc: Matias Ezequiel Vara Larsen
Cc: Thomas Huth
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 30 ++
1 file chan
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension support so that the IRQ can
route to 256 vcpus.
v4:
- Put patch3 ahead of patch2;
- patch1 Introduce two IRQ model(Extended IRQ model and Virt extended IRQ
model);
- Link to v3:
https:/
On 5/26/24 17:56, Nicholas Piggin wrote:
The way SMT thread siblings are matched is clunky, using hard-coded
logic that checks the PIR SPR.
Change that to use a new core_index variable in the CPUPPCState,
where all siblings have the same core_index. CPU realize routines have
flexibility in se
On 5/27/24 10:02, Jamin Lin wrote:
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers
On 5/27/24 10:02, Jamin Lin wrote:
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST
In function kvm_virtio_pci_vector_use_one(), the function will only use
the irqfd/vector for itself. Therefore, in the undo label, the failing
process is incorrect.
To fix this, we can just remove this label.
Fixes: f9a09ca3ea ("vhost: add support for configure interrupt")
Cc: qemu-sta...@nongnu.o
corrected typo, it's bitwise.
On 5/28/24 14:18, Harsh Prateek Bora wrote:
- (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value &
~(cs->nr_threads - 1))
+ (POWERPC_CPU(cs)->env.core_index)
Dont we want to keep the bitwise & with ~(cs->nr_threads - 1) ?
How's it taken care ?
On Tue, 28 May 2024 at 11:39, Gerd Hoffmann wrote:
>
> Remove myself from audio (both devices and backend) entries.
> Flip status to "Orphan" for entries which have nobody else listed.
> Signed-off-by: Gerd Hoffmann
> ---
> MAINTAINERS | 30 ++
> 1 file changed, 10 in
Hi Peter,
> -Original Message-
> From: Peter Xu [mailto:pet...@redhat.com]
> Sent: Wednesday, May 22, 2024 6:15 AM
> To: Yu Zhang
> Cc: Michael Galaxy ; Jinpu Wang
> ; Elmar Gerdes ;
> zhengchuan ; Gonglei (Arei)
> ; Daniel P. Berrangé ;
> Markus Armbruster ; Zhijian Li (Fujitsu)
> ; qemu
Hi Gonglei,
On Tue, May 28, 2024 at 11:06 AM Gonglei (Arei) wrote:
>
> Hi Peter,
>
> > -Original Message-
> > From: Peter Xu [mailto:pet...@redhat.com]
> > Sent: Wednesday, May 22, 2024 6:15 AM
> > To: Yu Zhang
> > Cc: Michael Galaxy ; Jinpu Wang
> > ; Elmar Gerdes ;
> > zhengchuan ; Gon
> > +fn read_trace_records(
> > +events: &Vec,
> > +fobj: &File,
> > +analyzer: &mut Formatter,
> > +read_header: bool,
> > +) -> Result>
> > +{
> > +/* backtrace::Backtrace needs this env variable. */
> > +env::set_var("RUST_BACKTRACE", "1");
> > +let bt = Backtrace::ne
On 5/26/24 17:56, Nicholas Piggin wrote:
Add helpers for TCG code to determine if there are SMT siblings
sharing per-core and per-lpar registers. This simplifies the
callers and makes SMT register topology simpler to modify with
later changes.
Signed-off-by: Nicholas Piggin
---
target/ppc/
On Fri, 24 May 2024 13:00:14 -0700
Zide Chen wrote:
> Currently, if running "-overcommit cpu-pm=on" on hosts that don't
> have MWAIT support, the MWAIT/MONITOR feature is advertised to the
> guest and executing MWAIT/MONITOR on the guest triggers #UD.
this is missing proper description how do yo
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 28, 2024 2:34 PM
> To: Jamin Lin ; Philippe Mathieu-Daudé
> ; Peter Maydell ; Andrew
> Jeffery ; Joel Stanley ;
> Alistair Francis ; Cleber Rosa ;
> Wainer dos Santos Moschetta ; Beraldo Leal
> ; open list:ASPEED
[ ... ]
I don't think this is necessary to do so now. Possibly, increase the version
number in the vmstate when resending a v5.
If I understand your request, do you mean to change as following in this patch?
static const VMStateDescription vmstate_aspeed_sdmc = {
.name = "aspeed.sdmc",
Signed-off-by: Gerd Hoffmann
---
hw/usb/Kconfig | 10 ++
hw/usb/meson.build | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index f569ed7eeaa1..84bc7fbe36cd 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -65,6 +65,16 @@ c
The xhci host adapter is the much better choice.
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-ohci-pci.c | 1 +
hw/usb/Kconfig| 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c
index 33ed9b6f5a52..88de657def71 100644
--- a/hw/
Add deprecation_note field (string) to ObjectClass.
Add deprecated bool to ObjectTypeInfo, report in 'qom-list-types'.
Print the note when listing devices via '-device help'.
Signed-off-by: Gerd Hoffmann
---
include/qom/object.h | 1 +
qom/qom-qmp-cmds.c| 4
system/qdev-monitor.c | 5 +
Hi Cedric,
> From: Cédric Le Goater
> [ ... ]
>
> >> I don't think this is necessary to do so now. Possibly, increase the
> >> version number in the vmstate when resending a v5.
> >>
> > If I understand your request, do you mean to change as following in this
> patch?
> >
> > static const VMState
The hub supports only USB 1.1. When running out of usb ports it is in
almost all cases the much better choice to add another usb host adapter
(or increase the number of root ports when using xhci) instead of using
the usb hub.
Signed-off-by: Gerd Hoffmann
---
hw/usb/dev-hub.c | 1 +
hw/usb/Kcon
Put some infrastructure in place to allow tagging objects (including
devices) as deprected. Use it to mark the ohci pci host adapter and
the usb hub as deprecated.
Gerd Hoffmann (4):
qom: allow to mark objects (including devices) as deprecated.
usb: add config options for the hub and hid devi
Jamin,
I think you should add your self as a Reviewer to the ASPEED BMCs
machine in the MAINTAINERS files. Would you agree ?
Thanks,
C.
On 5/27/24 10:02, Jamin Lin wrote:
Changes from v1:
The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
Changes from v2:
- replac
Hi,
> > virtio-snd
> > -M: Gerd Hoffmann
> > -R: Manos Pitsidianakis
> > +M: Manos Pitsidianakis
> > +R: Matias Ezequiel Vara Larsen
> > S: Supported
> > F: hw/audio/virtio-snd.c
> > F: hw/audio/virtio-snd-pci.c
>
> While extra reviewers are always helpful, someone like Volker would
> m
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 28, 2024 5:56 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ;
> Cleber
> Rosa ; Philippe Mathieu-Daudé ;
> Wainer dos Santos Moschetta ; Beraldo Leal
> ; open list:AS
在 2024/5/24 23:15, Shiyang Ruan 写道:
在 2024/5/22 14:45, Dan Williams 写道:
Shiyang Ruan wrote:
[..]
My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event
reported errors since action is only required for direct consumption
events and those need not be reported through the devi
On 5/28/24 12:02, Jamin Lin wrote:
Hi Cedric,
-Original Message-
From: Cédric Le Goater
Sent: Tuesday, May 28, 2024 5:56 PM
To: Jamin Lin ; Peter Maydell
; Andrew Jeffery ;
Joel Stanley ; Alistair Francis ; Cleber
Rosa ; Philippe Mathieu-Daudé ;
Wainer dos Santos Moschetta ; Beraldo Le
Issue #2294: Machine microvm doesn't run under Xen accel for
qemu-system-x86_64.
Solution: microvm is now not build if only Xen is available.
Signed-off-by: Will Gyda
---
configs/devices/i386-softmmu/default.mak | 2 +-
hw/i386/Kconfig | 2 ++
2 files changed, 3 inser
On 28/05/2024 11.54, Gerd Hoffmann wrote:
The xhci host adapter is the much better choice.
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-ohci-pci.c | 1 +
hw/usb/Kconfig| 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c
in
On some OS (e.g. macOS) sendmsg() returns -1 (errno EINVAL) if
the `struct msghdr` has the field `msg_controllen` set to 0, but
`msg_control` is not NULL.
Reviewed-by: Eric Blake
Reviewed-by: David Hildenbrand
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Stef
On macOS passing `-s /tmp/vhost.socket` parameter to the vhost-user-blk
application, the bind was done on `/tmp/vhost.socke` pathname,
missing the last character.
This sounds like one of the portability problems described in the
unix(7) manpage:
Pathname sockets
When binding a socket
v1: https://patchew.org/QEMU/20240228114759.44758-1-sgarz...@redhat.com/
v2: https://patchew.org/QEMU/20240326133936.125332-1-sgarz...@redhat.com/
v3: https://patchew.org/QEMU/20240404122330.92710-1-sgarz...@redhat.com/
v4: https://patchew.org/QEMU/20240508074457.12367-1-sgarz...@redhat.com/
v5: ht
The vhost-user protocol is not really Linux-specific so let's enable
vhost-user frontends for any POSIX system.
In vhost_net.c we use VHOST_FILE_UNBIND which is defined in a Linux
specific header, let's define it for other systems as well.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe
In vhost-user-server we set all fd received from the other peer
in non-blocking mode. For some of them (e.g. memfd, shm_open, etc.)
it's not really needed, because we don't use these fd with blocking
operations, but only to map memory.
In addition, in some systems this operation can fail (e.g. in
Let's replace the calls to le*toh() and htole*() with qemu/bswap.h
helpers to make the code more portable.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Signed-off-by: Stefano
In vu_message_write() we use sendmsg() to send the message header,
then a write() to send the payload.
If sendmsg() fails we should avoid sending the payload, since we
were unable to send the header.
Discovered before fixing the issue with the previous patch, where
sendmsg() failed on macOS due t
The vhost-user protocol is not really Linux-specific so let's enable
libvhost-user for any POSIX system.
Compiling it on macOS and FreeBSD some problems came up:
- avoid to include linux/vhost.h which is available only on Linux
(vhost_types.h contains many of the things we need)
- macOS doesn't
libvhost-user will panic when receiving VHOST_USER_GET_INFLIGHT_FD
message if MFD_ALLOW_SEALING is not defined, since it's not able
to create a memfd.
VHOST_USER_GET_INFLIGHT_FD is used only if
VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD is negotiated. So, let's mask
that feature if the backend is not ab
Let's make the code more portable by adding defines from
block/file-posix.c to support O_DIRECT in other systems (e.g. macOS).
vhost-user-server.c is a dependency, let's enable it for any POSIX
system.
Acked-by: Stefan Hajnoczi
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Dau
shm_open() creates and opens a new POSIX shared memory object.
A POSIX shared memory object allows creating memory backend with an
associated file descriptor that can be shared with external processes
(e.g. vhost-user).
The new `memory-backend-shm` can be used as an alternative when
`memory-backen
`memory-backend-shm` can be used with vhost-user devices, so let's
add a new test case for it.
Acked-by: Thomas Huth
Acked-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Signed-off-by: Stefano Garzarella
---
tests/qtest/vhost-user-test.c | 23 +++
1 file changed, 23 in
`memory-backend-memfd` is available only on Linux while the new
`memory-backend-shm` can be used on any POSIX-compliant operating
system. Let's use it so we can run the test in multiple environments.
Since we are here, let`s remove `share=on` which is the default for shm
(and also for memfd).
Ack
On 28/05/2024 11.54, Gerd Hoffmann wrote:
Signed-off-by: Gerd Hoffmann
---
hw/usb/Kconfig | 10 ++
hw/usb/meson.build | 4 ++--
2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Thomas Huth
Akihiko Odaki writes:
> -fsanitize=undefined complains if function pointers are casted. It
> also prevents enabling teh strict mode of CFI which is currently
Typo: the
> disabled with -fsanitize-cfi-icall-generalize-pointers.
The above describes the problem the patch solves. Good! Two
sugges
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
discard requests and
In the context of backup fleecing, discarding the source will not work
when the fleecing image has a larger granularity than the one used for
block-copy operations (can happen if the backup target has smaller
cluster size), because cbw_co_pdiscard_snapshot() will align down the
discard requests and
Based-on:
https://lore.kernel.org/qemu-devel/20240429115157.2260885-1-vsement...@yandex-team.ru/
Discussion for v1:
https://lore.kernel.org/qemu-devel/20240308155158.830258-1-f.eb...@proxmox.com/
Changes in v2:
* Use 'size' type in QAPI.
* Remove option in cbw_parse_options(), i.e. before parsin
On Sat, 25 May 2024 at 00:23, Richard Henderson
wrote:
>
> Load and zero-extend float16 into a TCGv_i32 before
> all scalar operations.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
Sorry, I had the bad mail client setting. Please ignore the previous email,
and I will resubmit the patch.
--
Jerry
Jerry ZJ 於 2024年5月28日 週二 下午8:12寫道：
>
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On Sat, 25 May 2024 at 00:22, Richard Henderson
wrote:
>
> All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
> Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
>
> Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in
> simd_scalar_pairwise")
> Signed-off-by: Ri
On Sat, 25 May 2024 at 00:30, Richard Henderson
wrote:
>
> The decode of FMOV (vector, immediate, half-precision) vs
> invalid cases of MOVI are incorrect.
>
> Fixes RISU mismatch for invalid insn 0x2f01fd31.
>
> Fixes: 70b4e6a4457 ("arm/translate-a64: add FP16 FMOV to simd_mod_imm")
> Signed-off-
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On 28/5/24 12:38, Stefano Garzarella wrote:
`memory-backend-shm` can be used with vhost-user devices, so let's
add a new test case for it.
Acked-by: Thomas Huth
Acked-by: Stefan Hajnoczi
Reviewed-by: David Hildenbrand
Signed-off-by: Stefano Garzarella
---
tests/qtest/vhost-user-test.c | 23
On Sat, 25 May 2024 at 00:23, Richard Henderson
wrote:
>
> Fixes RISU mismatch for "fcvtzs h31, h0, #14".
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl
On 30.04.24 12:13, Vladimir Sementsov-Ogievskiy wrote:
We want to have similar QMP objects in different tests. Reworking these
objects to make common parts by calling some helper functions doesn't
seem good. It's a lot more comfortable to see the whole QAPI request in
one place.
So, let's increa
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