[PATCH v3 3/6] vvfat: Fix reading files with non-continuous clusters

When reading with `read_cluster` we get the `mapping` with `find_mapping_for_cluster` and then we call `open_file` for this mapping. The issue appear when its the same file, but a second cluster that is not immediately after it, imagine clusters `500 -> 503`, this will give us 2 mappings one has th

[PATCH v3 4/6] iotests: Add `vvfat` tests

Added several tests to verify the implementation of the vvfat driver. We needed a way to interact with it, so created a basic `fat16.py` driver that handled writing correct sectors for us. Signed-off-by: Amjad Alsharafi --- tests/qemu-iotests/check | 2 +- tests/qemu-iotests/fat16.

[PATCH v3 5/6] iotests: Filter out `vvfat` fmt from failing tests

`vvfat` is a special format and not all tests (even generic) can run without crashing. So, added `unsupported_fmt: vvfat` to all failling tests. Also added `vvfat` format into `meson.build`, vvfaat tests can be run on the `block-thorough` suite. Signed-off-by: Amjad Alsharafi --- .gitlab-ci.d

[PATCH v3 2/6] vvfat: Fix usage of `info.file.offset`

The field is marked as "the offset in the file (in clusters)", but it was being used like this `cluster_size*(nums)+mapping->info.file.offset`, which is incorrect. Additionally, removed the `abort` when `first_mapping_index` does not match, as this matches the case when adding new clusters for fil

[PATCH v3 6/6] iotests: Add `create_file` test for `vvfat` driver

We test the ability to create new files in the filesystem, this is done by adding an entry in the desired directory list. The file will also be created in the host filesystem with matching filename. Signed-off-by: Amjad Alsharafi --- tests/qemu-iotests/fat16.py| 124 +

[PATCH v3 0/6] vvfat: Fix write bugs for large files and add iotests

These patches fix some bugs found when modifying files in vvfat. First, there was a bug when writing to the cluster 2 or above of a file, it will copy the cluster before it instead, so, when writing to cluster=2, the content of cluster=1 will be copied into disk instead in its place. Another issue

[PATCH v3 1/6] vvfat: Fix bug in writing to middle of file

Before this commit, the behavior when calling `commit_one_file` for example with `offset=0x2000` (second cluster), what will happen is that we won't fetch the next cluster from the fat, and instead use the first cluster for the read operation. This is due to off-by-one error here, where `i=0x2000

[RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore

The timebase state machine is per per-core state and can be driven by any thread in the core. It is currently implemented as a hack where the state is in a CPU structure and only thread 0's state is accessed by the chiptod, which limits programming the timebase side of the state machine to thread 0

[RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option

Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread" modes. In per-core mode, some SPRs and IPI doorbells are shared between threads in a core. In per-thread mode, supervisor and user state is not shared between threads. OpenPOWER systems use LPAR per thread mode as it is required

[RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling

POWER9 and POWER10 machines come in two variants, "big-core" and "small-core". Big core machines are SMT8 from the software point of view, but in the low level platform topology ("xscom registers and pervasive addressing"), these look more like a pair of small cores ganged together. Presently, th

[RFC PATCH 03/10] target/ppc: Improve SPR indirect registers

SPRC/SPRD were recently added to all BookS CPUs supported, but they are only tested on POWER9 and POWER10, so restrict them to those CPUs. SPR indirect scratch registers presently replicated per-CPU like SMT SPRs, but the PnvCore is a better place for them since they are restricted to P9/P10. Als

[RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads

Add helpers for TCG code to determine if there are SMT siblings sharing per-core and per-lpar registers. This simplifies the callers and makes SMT register topology simpler to modify with later changes. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 7 +++ target/ppc/cpu_

[RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines

This will allow different settings and checks for different machine types with later changes. Signed-off-by: Nicholas Piggin --- hw/ppc/pnv.c | 35 ++- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6e3a5ccdec..a70

[RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore

This helps move core state from CPU to core structures. Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_core.h | 1 + hw/ppc/pnv_core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c6d62fd145..30c1e5b1a3 100644

[RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs

The way SMT thread siblings are matched is clunky, using hard-coded logic that checks the PIR SPR. Change that to use a new core_index variable in the CPUPPCState, where all siblings have the same core_index. CPU realize routines have flexibility in setting core/sibling topology. Signed-off-by: N

[RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well

The chip_pir chip class method allows the platform to set the PIR processor identification register. Extend this to a more general ID function which also allows the TIR to be set. This is in preparation for "big core", which is a more complicated topology of cores and threads. Signed-off-by: Nicho

[RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit

Primary motivation for this series is to improve big-core support. Other things like SPR indirect, timebase state, PC xscom, are required for minimal big core support. I'm still not 100% happy with the big-core topology model after this. Maybe one day we add pnv big core and pnv small core structu

[RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls

The PC unit in the processor core contains xscom registers that provide low level status and control of the CPU. This implements "direct controls" sufficient for OPAL (skiboot) firmware use, which is to stop threads and send them non-maskable IPIs in the form of SRESET interrupts. POWER10 is suff

Re: [RFC PATCH 1/3] hw/intc/s390_flic: Migrate pending state

Am 25.05.24 um 15:12 schrieb Nicholas Piggin: The flic pending state is not migrated, so if the machine is migrated while an interrupt is pending, it can be lost. This shows up in qtest migration test, an extint is pending (due to console writes?) and the CPU waits via s390_cpu_set_psw and expect

Re: [PATCH 0/6] target/riscv: Support Zabha extension

On 5/25/24 21:37, LIU Zhiwei wrote: On 2024/5/24 19:44, Daniel Henrique Barboza wrote: Hi Zhiwei! On 5/23/24 09:40, LIU Zhiwei wrote: Zabha adds support AMO operations for byte and half word. If zacas has been implemented, zabha also adds support amocas.b and amocas.h. More details is

[PATCH RISU v2 00/13] ELF and Sparc64 support

Let risu accept elf test files, adjusted from v1. Adjust risugen to invoke the assembler and linker, with a cross-compiler prefix if needed. Add some sparc64 testing which utilizes this. Changes for v2: - Implement VIS2 through VIS4. There's something odd going on with the Sparc M8 Solaris host

[PATCH RISU v2 02/13] Build elf test cases instead of raw binaries

For test_arch64.s and test_arm.s, use '.inst' so that the risu control insns are marked as instructions for disassembly. For test_i386.S, split the data to be loaded into the data section; fix an error aligning the data: 16 not 2**16. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard He

[PATCH RISU v2 04/13] risu: Add initial sparc64 support

Best effort for both Linux and Solaris as a host, since the gcc compile farm has more working Sparc Solaris hosts than Sparc Linux hosts. What's missing is a value for %gsr from Solaris. This could complicate comparison of VIS instructions. Signed-off-by: Richard Henderson --- Makefile

[PATCH RISU v2 12/13] sparc64: Add IMA instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 7 +++ 1 file changed, 7 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index ca7ed35..271fee0 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -243,3 +243,10 @@ MOVxTOd VIS3 10 rd:5 110110 0 1 0001 1000 rs2:5 \ # !

[PATCH RISU v2 09/13] sparc64: Add VIS1 instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 91 1 file changed, 91 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index b45ea86..10a8510 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -28,3 +28,94 @@ XOR_r SPARC 10 r

[PATCH RISU v2 11/13] sparc64: Add VIS3 instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 88 1 file changed, 88 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 5b90b70..ca7ed35 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -155,3 +155,91 @@ FNMSUBs FMAF 10

[PATCH RISU v2 03/13] Introduce host_context_t

Most hosts pass ucontext_t as the third parameter of signal handlers. In one existing usage, loongarch64 is using the kernel's struct ucontext instead of libc's ucontext_t. This is probably a simple mistake that could be fixed, but the structure member names differ, so the change would not be com

[PATCH RISU v2 08/13] sparc64: Add a few logical insns

Just a token to verify the script is working. Signed-off-by: Richard Henderson --- sparc64.risu | 30 ++ 1 file changed, 30 insertions(+) create mode 100644 sparc64.risu diff --git a/sparc64.risu b/sparc64.risu new file mode 100644 index 000..b45ea86 --- /dev/nu

[PATCH RISU v2 01/13] risu: Allow use of ELF test files

By using elf files, we make it easier to disassemble the test file, to match comparison failures to code. Signed-off-by: Richard Henderson --- risu.c | 57 - 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/risu.c b/risu.c ind

[PATCH RISU v2 05/13] risugen: Be explicit about print destinations

Printing directly to STDOUT and STDERR will allow the print destination to be selected elsewhere. Signed-off-by: Richard Henderson --- risugen_common.pm | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/risugen_common.pm b/risugen_common.pm index 71ee996..520

[PATCH RISU v2 07/13] contrib/generate_all: Do not rely on ag

Use plain grep instead. Signed-off-by: Richard Henderson --- contrib/generate_all.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/contrib/generate_all.sh b/contrib/generate_all.sh index 651cb23..5ff0b3e 100755 --- a/contrib/generate_all.sh +++ b/contrib/generate_all.sh

[PATCH RISU v2 13/13] sparc64: Add VIS4 instructions

Signed-off-by: Richard Henderson --- sparc64.risu | 46 ++ 1 file changed, 46 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 271fee0..1022a62 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -250,3 +250,49 @@ MOVxTOd VIS3 10 rd:5 1

[PATCH RISU v2 10/13] sparc64: Add VIS2 and FMAF insns

Signed-off-by: Richard Henderson --- sparc64.risu | 36 1 file changed, 36 insertions(+) diff --git a/sparc64.risu b/sparc64.risu index 10a8510..5b90b70 100644 --- a/sparc64.risu +++ b/sparc64.risu @@ -119,3 +119,39 @@ FEXPAND VIS1 10 rd:5 110110

[PATCH RISU v2 06/13] risugen: Add sparc64 support

Signed-off-by: Richard Henderson --- risugen| 10 +- risugen_common.pm | 50 +- risugen_sparc64.pm | 385 + 3 files changed, 443 insertions(+), 2 deletions(-) create mode 100644 risugen_sparc64.pm diff --git a/risugen b/risugen inde

[PATCH v2 22/37] target/sparc: Implement LZCNT

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 18 ++ 2 files changed, 19 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index fec055910e..4766964893 100644

[PATCH v2 00/37] target/sparc: Implement VIS4

Now tested with RISU, using a Solaris M8 host as reference. This exposed a few bugs in the existing VIS1 support as well, so fix those before anything else. It also exposed a few bugs in the implementation of VIS3, so fixes squashed there as well. r~ Richard Henderson (37): target/sparc: Fix

[PATCH v2 27/37] target/sparc: Enable VIS3 feature bit

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 1 + target/sparc/cpu.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6a1457346a..cb79580431 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1004,6 +1004,7 @@

[PATCH v2 29/37] target/sparc: Add feature bit for VIS4

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/translate.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index e2e6de9144..be81005237 100644

[PATCH v2 28/37] target/sparc: Implement IMA extension

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/insns.decode | 3 +++ linux-user/elfload.c | 1 + target/sparc/cpu.c | 3 +++ target/sparc/translate.c | 24 5

[PATCH v2 06/37] target/sparc: Remove gen_dest_fpr_D

Replace with tcg_temp_new_i64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 27 +++ 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f3c52c7c48

[PATCH v2 34/37] target/sparc: Implement SUBXC, SUBXCcc

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 14 ++ 2 files changed, 16 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2ebee5a1ca..a7720560f8 100644 ---

[PATCH v2 35/37] target/sparc: Implement MWAIT

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 11 +++ 2 files changed, 12 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a7720560f8..fbcb4f7aef 100644 --- a/target/sparc/insns.decode +++ b/target

[PATCH v2 13/37] target/sparc: Implement FCHKSM16

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 32 target/sparc/vis_helper.c | 23 +++ 4 files changed, 57 insertions(+) diff --git a/target/sparc/helper.h b

[PATCH v2 02/37] target/sparc: Rewrite gen_edge

Drop the tables and compute the left and right edges directly. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 98 +++- 1 file changed, 37 insertions(+), 61 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dc

[PATCH v2 37/37] target/sparc: Enable VIS4 feature bit

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 88da5254e8..9bacfb68cb 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -552,6 +552,7 @@ sta

[PATCH v2 26/37] target/sparc: Implement XMULX

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 4 target/sparc/vis_helper.c | 11 +++ 4 files changed, 19 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 4ae97866a

[PATCH v2 23/37] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 6 ++ target/sparc/translate.c | 36 2 files changed, 42 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4766964893..e0e9248982 100644 --- a/target/s

[PATCH v2 17/37] target/sparc: Implement FPADD64, FPSUB64

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index febd1a4a13..70ca41a69a 100644 --- a/target/spar

[PATCH v2 12/37] target/sparc: Implement CMASK instructions

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 3 +++ target/sparc/insns.decode | 4 target/sparc/translate.c | 13 + target/sparc/vis_helper.c | 38 ++ 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h

[PATCH v2 09/37] target/sparc: Implement FMAf extension

Rearrange PDIST so that do_ is general purpose and may be re-used for FMADDd etc. Add pickNaN and pickNaNMulAdd. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 2 + target/sparc/cpu-feature.h.inc | 1 + target/sparc/insns.decode | 23 +- linux-user/elfl

[PATCH v2 31/37] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 + target/sparc/translate.c | 11 +++ 2 files changed, 20 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0913fe7a86..80579642d1 100644

[PATCH v2 16/37] target/sparc: Implement FMEAN16

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 30 ++ target/sparc/vis_helper.c | 21 + 4 files changed, 53 insertions(+) diff --git a/target/sparc/helper.h b/tar

[PATCH v2 14/37] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 5 +++ target/sparc/insns.decode | 11 ++ target/sparc/fop_helper.c | 68 +++ target/sparc/translate.c | 76 +++ 4 files changed, 160 insertions(+) diff --gi

[PATCH v2 01/37] target/sparc: Fix ARRAY8

Follow the Oracle Sparc 2015 implementation note and bound the input value of N to 5 from the lower 3 bits of rs2. Spell out all of the intermediate values, matching the diagram in the manual. Fix extraction of upper_x and upper_y for N=0. Signed-off-by: Richard Henderson --- target/sparc/vis_h

[PATCH v2 18/37] target/sparc: Implement FPADDS, FPSUBS

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 + target/sparc/translate.c | 82 +++ 2 files changed, 91 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 70ca41a69a..b6553362eb 100644 --- a/target

[PATCH v2 03/37] target/sparc: Fix do_dc

Apply DFPREG to compute the register number. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 00c2a11353..1eb1a6decf 100644 --- a/target/sparc/translate.c +++ b/target/sparc

[PATCH v2 20/37] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 9 + target/sparc/translate.c | 11 +++ target/sparc/vis_helper.c | 36 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h

[PATCH v2 04/37] target/sparc: Fix helper_fmul8ulx16

This operation returns the high 16 bits of a 24-bit multiply that has been sign-extended to 32 bits. Signed-off-by: Richard Henderson --- target/sparc/vis_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c in

[PATCH v2 15/37] target/sparc: Implement FLCMP

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 4 target/sparc/fop_helper.c | 46 +++ target/sparc/translate.c | 34 + 4 files changed, 86 insertions(+) diff --git a/target

[PATCH v2 19/37] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 4 target/sparc/insns.decode | 5 + target/sparc/translate.c | 9 + target/sparc/vis_helper.c | 40 +++ 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h b

[PATCH v2 07/37] target/sparc: Remove cpu_fpr[]

Use explicit loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 158 +-- 1 file changed, 84 insertions(+), 74 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 750a3e6554..362e88d

[PATCH v2 24/37] target/sparc: Implement PDISTN

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 11 +++ 2 files changed, 12 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index e0e9248982..09c8adca37 100644 --- a/t

Re: [RFC PATCH 1/3] hw/intc/s390_flic: Migrate pending state

On 5/26/24 08:53, David Hildenbrand wrote: Am 25.05.24 um 15:12 schrieb Nicholas Piggin: The flic pending state is not migrated, so if the machine is migrated while an interrupt is pending, it can be lost. This shows up in qtest migration test, an extint is pending (due to console writes?) and t

[PATCH v2 21/37] target/sparc: Implement LDXEFSR

Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/fop_helper.c | 6 ++ target/sparc/translate.c | 11 +-- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h

[PATCH v2 30/37] target/sparc: Implement FALIGNDATAi

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 33 ++--- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5d85e124ed..0913fe7a86 100644 --- a/

[PATCH v2 32/37] target/sparc: Implement VIS4 comparisons

VIS4 completes the set, adding missing signed 8-bit ops and missing unsigned 16 and 32-bit ops. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 12 +-- target/sparc/insns.decode | 6 ++ target/sparc/translate.c | 12 +++ target/sparc/vis_helper.c | 170 +

[PATCH v2 11/37] target/sparc: Implement ADDXC, ADDXCcc

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 14 ++ 2 files changed, 17 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 056fba98f9..5d1c55aa78 100644 --

[PATCH v2 05/37] target/sparc: Perform DFPREG/QFPREG in decodetree

Form the proper register decoding from the start. Because we're removing the translation from the inner-most gen_load_fpr_* and gen_store_fpr_* routines, this must be done for all insns at once. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode

[PATCH v2 25/37] target/sparc: Implement UMULXHI

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 8 2 files changed, 9 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 09c8adca37..508175eccd 100644 --- a/target/sparc/insns.decode +++ b/target/sparc

[PATCH v2 36/37] target/sparc: Implement monitor ASIs

Ignore the "monitor" portion and treat them the same as their base ASIs. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/asi.h | 4 target/sparc/ldst_helper.c | 4 target/sparc/translate.c | 8 3 files changed, 16 insertions(+)

[PATCH v2 33/37] target/sparc: Implement FPMIN, FPMAX

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 14 ++ target/sparc/translate.c | 14 ++ 2 files changed, 28 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index be591171ad..2ebee5a1c

[PATCH v2 08/37] target/sparc: Use gvec for VIS1 parallel add/sub

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 362e88de18..8731e4f8bb 100644 --- a/target/sparc/tra

[PATCH v2 10/37] target/sparc: Add feature bits for VIS 3

The manual separates VIS 3 and VIS 3B, even though they are both present in all extant cpus. For clarity, let the translator match the manual but otherwise leave them on the same feature bit. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu-feature.h.in

[PATCH 2/2] block: add test non-active commit with zeroed data

Signed-off-by: Vincent Vanlaer --- tests/qemu-iotests/315 | 95 ++ tests/qemu-iotests/315.out | 54 ++ 2 files changed, 149 insertions(+) create mode 100755 tests/qemu-iotests/315 create mode 100644 tests/qemu-iotests/315.out diff --g

[PATCH 1/2] block: allow commit to unmap zero blocks

Non-active block commits do not discard blocks only containing zeros, causing images to lose sparseness after the commit. This commit fixes that by writing zero blocks using blk_co_pwrite_zeroes rather than writing them out as any oother arbitrary data. Signed-off-by: Vincent Vanlaer --- block/c

[PATCH 0/2] block: allow commit to unmap zero blocks

This patch series adds support for zero blocks in non-active commits. The first patch in the series contains the actual changes to the commit code, the second patch adds a test for the new functionality. Vincent Vanlaer (2): block: allow commit to unmap zero blocks block: add test non-active c

Re: [RFC PATCH 1/3] hw/intc/s390_flic: Migrate pending state

Am 26.05.24 um 21:44 schrieb Richard Henderson: On 5/26/24 08:53, David Hildenbrand wrote: Am 25.05.24 um 15:12 schrieb Nicholas Piggin: The flic pending state is not migrated, so if the machine is migrated while an interrupt is pending, it can be lost. This shows up in qtest migration test, an

[PATCH] target/arm: Disable SVE extensions when SVE is disabled

From: Marcin Juszkiewicz Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 Reported-by: Marcin Juszkiewicz Signed-off-by: Richard Henderson --- Marcin added the correct patch to the issue 3 weeks ago, so I'm giving him authorship here. I only updated the

Re: [PATCH] target/arm: Disable SVE extensions when SVE is disabled

W dniu 26.05.2024 o 22:45, Richard Henderson pisze: From: Marcin Juszkiewicz Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 Reported-by: Marcin Juszkiewicz Signed-off-by: Richard Henderson Signed-off-by: Marcin Juszkiewicz --- Marcin added the co

[PATCH 03/43] target/ppc/mmu_common.c: Remove single use local variable

The ptem variable in ppc6xx_tlb_pte_check() is used only once, simplify by removing it as the value is already clear itself without adding a local name for it. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/

[PATCH 06/43] target/ppc/mmu_common.c: Remove yet another single use local variable

In ppc6xx_tlb_pte_check() the pp variable is used only once to pass it to a function parameter with the same name. Remove the local and inline the value. Also use named constant for the hex value to make it clearer. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 5 ++--- 1 file chan

[PATCH 21/43] target/ppc/mmu_common.c: Remove key field from mmu_ctx_t

Pass it as a function parameter and remove it from mmu_ctx_t. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 26 ++ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index fe321ab49c..be09c3b1a3

[PATCH 14/43] target/ppc/mmu_common.c: Remove single use local variable

In mmu6xx_get_physical_address() tagtet_page_bits local is declared only to use TARGET_PAGE_BITS once. Drop the unneeded variable. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc

[PATCH 08/43] target/ppc/mmu_common.c: Simplify ppc6xx_tlb_pte_check()

Invert conditions to avoid deep nested ifs and return early instead. Remove some obvious comments that don't add more clarity. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 43 ++--- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a

[PATCH 00/43] Remaining MMU clean up patches

This is the rest of the MMU clean up series the first part of which was merged. Here are the remaining patches rebased and some more added. Regards, BALATON Zoltan BALATON Zoltan (43): target/ppc: Reorganise and rename ppc_hash32_pp_prot() target/ppc/mmu_common.c: Remove local name for a cons

[PATCH 19/43] target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_prot()

This is used only once and can be inlined. Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 19 --- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 93559447ff..160311de87 100644 --- a/target/ppc/mmu

[PATCH 13/43] target/ppc/mmu_common.c: Convert local variable to bool

In mmu6xx_get_physical_address() ds is used as bool, declare it as such. Also use named constant instead of hex value. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_comm

[PATCH 05/43] target/ppc/mmu_common.c: Remove another single use local variable

In ppc6xx_tlb_pte_check() the pteh variable is used only once to compare to the h parameter of the function. Inline its value and use pteh name for the function parameter which is more descriptive. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 7 +++ 1 file changed, 3 insertion

[PATCH 18/43] target/ppc: Add function to get protection key for hash32 MMU

Add a function to get key bit from SR and use it instead of open coded version. Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 9 ++--- target/ppc/mmu-hash32.h | 5 + target/ppc/mmu_common.c | 3 +-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/ppc/

[PATCH 09/43] target/ppc/mmu_common.c: Remove unused field from mmu_ctx_t

The eaddr field of mmu_ctx_t is set once but never used so can be removed. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 28adb3ca10..0a07023f48 100644 --- a/target/ppc/mmu_com

[PATCH 39/43] target/ppc: Change parameter type of some inline functions

These functions take PowerPCCPU but only need the env from it. Change their parameter to CPUPPCState *env. Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 13 +++-- target/ppc/mmu-hash32.h | 12 ++-- target/ppc/mmu_common.c | 20 +--- 3 files changed,

[PATCH 26/43] target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb()

Pass raddr and prot in function parameters instead Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 624ed51a92..4770b43630 100644 --- a/target/pp

[PATCH 07/43] target/ppc/mmu_common.c: Return directly in ppc6xx_tlb_pte_check()

Instead of using a local ret variable return directly and remove the local. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 799d2ced9b..a5ae11394d 1006

[PATCH 20/43] target/ppc/mmu_common.c: Init variable in function that relies on it

The ppc6xx_tlb_check() relies on the caller to initialise raddr field in ctx. Move this init from the only caller into the function. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/

[PATCH 35/43] target/ppc/mmu-hash32.c: Change parameter type of ppc_hash32_bat_lookup()

This function takes PowerPCCPU but only needs the env from it. Change its parameter to CPUPPCState *env. Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 44b1

[PATCH 23/43] target/ppc/mmu_common.c: Rename function parameter

Rename parameter of get_bat_6xx_tlb() from virtual to eaddr to match other functions. Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index ede409eb9

[PATCH 24/43] target/ppc/mmu_common.c: Use defines instead of numeric constants

Replace some BAT related constants with defines from mmu-hash32.h Signed-off-by: BALATON Zoltan --- target/ppc/mmu_common.c | 26 +- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 110936ca83..aa002bb

[PATCH 40/43] target/ppc: Change parameter type of ppc64_v3_radix()

This function takes PowerPCCPU but only needs the env from it. Change its parameter to CPUPPCState *env. Signed-off-by: BALATON Zoltan --- hw/ppc/spapr_rtas.c| 2 +- target/ppc/mmu-book3s-v3.h | 4 ++-- target/ppc/mmu_common.c| 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)

[PATCH 28/43] target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr()

This function is used only once and does not add more clarity than doing it inline. Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 18 +- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 6f0f0bbb00

[PATCH 01/43] target/ppc: Reorganise and rename ppc_hash32_pp_prot()

Reorganise ppc_hash32_pp_prot() swapping the if legs so it does not test for negative first and clean up to make it shorter. Also rename it to ppc_hash32_prot(). Signed-off-by: BALATON Zoltan --- target/ppc/mmu-hash32.c | 2 +- target/ppc/mmu-hash32.h | 35 +-- t

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