On May 17 17:52, Changqi Lu wrote:
> This commit enables the rescap function in the
> namespace by detecting the supported reservation
> function in the backend driver.
>
> Signed-off-by: Changqi Lu
> Signed-off-by: zhenwei pi
> ---
> hw/nvme/ns.c | 8
> 1 file changed, 8 insertions(+)
On May 17 17:52, Changqi Lu wrote:
> This commit enables ONCS to support the reservation
> function at the controller level. It also lays the
> groundwork for detecting and enabling the reservation
> function on a per-namespace basis in RESCAP.
>
> Signed-off-by: Changqi Lu
> Signed-off-by: zhenw
On May 17 17:52, Changqi Lu wrote:
> Add constants for the NVMe persistent command protocol.
> The constants include the reservation command opcode and
> reservation type values defined in section 7 of the NVMe
> 2.0 specification.
>
> Signed-off-by: Changqi Lu
> Signed-off-by: zhenwei pi
> ---
On 5/23/24 10:45, Daniel P. Berrangé wrote:
On Thu, May 23, 2024 at 08:11:18AM +0300, Artyom Kunakovsky wrote:
Fix linker error if the project was configured by the './configure
--cpu=unknown --target-list=riscv64-softmmu' command
As with v1, why are you intentionally passing a bogus CPU targ
On May 17 17:52, Changqi Lu wrote:
> This commit enables the rescap function in the
> namespace by detecting the supported reservation
> function in the backend driver.
>
> Signed-off-by: Changqi Lu
> Signed-off-by: zhenwei pi
> ---
> hw/nvme/ns.c | 8
> 1 file changed, 8 insertions(+)
On May 17 17:52, Changqi Lu wrote:
> Add reservation acquire, reservation register,
> reservation release and reservation report commands
> in the nvme device layer.
>
> By introducing these commands, this enables the nvme
> device to perform reservation-related tasks, including
> querying keys, q
We used to request declare_dependency() to link_whole static libraries.
If a static library is a thin archive, GNU ld needs to open all object
files referenced by the archieve, and sometimes reaches to the open
file limit.
Another problem with link_whole is that it does not propagate
dependencies.
This reverts commit 3eacf70bb5a83e4775ad8003cbca63a40f70c8c2.
Signed-off-by: Akihiko Odaki
---
meson.build| 4 ++--
block/meson.build | 2 +-
io/meson.build | 2 +-
storage-daemon/meson.build | 2 +-
ui/meson.build | 2 +-
5 files changed, 6 inser
Based-on: <20240524-xkb-v4-0-2de564e5c...@daynix.com>
("[PATCH v4 0/4] Fix sanitizer errors with clang 18.1.1")
This is changes suggested by Paolo Bonzini at:
https://lore.kernel.org/all/CABgObfYoEFZsW-H4WJ7xW0B85OqFi932d3-DmNAb6zTohFn=o...@mail.gmail.com/
Unfortunately it br
On May 8 09:36, Vincent Fu wrote:
> On 5/7/24 10:05, Vincent Fu wrote:
> > On 5/6/24 04:06, Klaus Jensen wrote:
> > > The Management Operation field of I/O Management Send is only 8 bits,
> > > not 16.
> > >
> > > Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation")
> > > Signed-off
On 2024/05/22 22:45, Paolo Bonzini wrote:
On Wed, May 22, 2024 at 12:49 PM Akihiko Odaki wrote:
The non-standard .fa library prefix breaks the link source
de-duplication done by Meson so drop it.
Can you show the difference in the command lines?
Without this patch:
clang -o qemu-io qemu-io
This is already handled in gen_eob(). Before adding another DISAS_*
case, remove the double calls.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 76be7425800..f44ed
This is an invariant, since these cases of tb_stop() should only
be reached through the "instruction decoding completed" path of
i386_tr_translate_insn().
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.
Some cleanups in translate.c, which I could make now that the
it's smaller and it's easier to understand how the various
utility functions are used.
1-7: cleanups for gen_eob
8-14: inlining and removing macros
15-16: cleanups for cc_op vs. helpers
Paolo
Paolo Bonzini (16):
target/i386: remov
No need to set it again at the end of the translation block, cc_op_dirty
can be set to false.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 37 -
target/i386/tcg/emit.c.inc | 2 +-
2 files changed, 25 insertions(+), 14 deletions(-)
diff --g
It is always s->aflag.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 20 ++--
target/i386/tcg/emit.c.inc | 6 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 18d8c0de674..1a
Place DISAS_* constants that update cpu_eip first, and
the "jump" ones last. Add comments explaining the differences
and usage.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/target/i386
sti only has one exit, so it does not need to generate the
end-of-translation code inline. It can be deferred to tb_stop.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 13 -
target/i386/tcg/emit.c.inc | 4 +---
2 files changed, 1 insertion(+), 16 deletions(-)
dif
Use mo_stacksize for all stack accesses, including when
a 64-bit code segment is impossible and the code is
therefore checking only for SS32(s).
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/i386/tc
The is_store argument of gen_ldst_modrm has only ever been passed
a constant. Just split the function in two.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 52 +
1 file changed, 29 insertions(+), 23 deletions(-)
diff --git a/target/i386/tcg/
Generalize gen_stack_A0() to include an initial add and to use an arbitrary
destination. This is a common pattern and it is not a huge burden to
add the extra arguments to the only caller of gen_stack_A0().
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 51 +++---
gen_helper_rsm cannot generate an exception, and reloads the flags.
So there's no need to spill cc_op and update cpu_eip, but on the
other hand cc_op must be reset to CC_OP_EFLAGS before returning.
It all works by chance, because by spilling cc_op before the call
to the helper, it becomes non-dirt
Values other than OR_TMP0 were only ever used by MOV and MOVNTI
opcodes. Now that these have been converted to the new decoder,
remove the argument.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 33 -
1 file changed, 12 insertions(+), 21 deletion
syscall and sysret only have one exit, so they do not need to
generate the end-of-translation code inline. It can be
deferred to tb_stop.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/i386/t
It is only used in MONITOR, where a direct call of gen_lea_v_seg
is simpler, and in XLAT. Inline it in the latter.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 9 +
target/i386/tcg/emit.c.inc | 2 +-
2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/targe
Make gen_eob take the DISAS_* constant as an argument, so that
it is not necessary to have wrappers around it.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 60 +
1 file changed, 14 insertions(+), 46 deletions(-)
diff --git a/target/i386/tcg/
Mark cc_op as clean and do not spill it at the end of the translation block.
Technically this is a tiny bit less efficient, but:
* it results in translations that are a tiny bit smaller
* for most of these instructions, it is not unlikely that they are close to
the end of the basic block, in whic
Do not bother generating inline wrappers for gen_repz and gen_repz2;
use s->prefix to separate REPZ from REPNZ in the case of SCAS and
CMPS.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 22 --
target/i386/tcg/emit.c.inc | 22 +-
2 files
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH] intel_iommu: Use the latest fault reasons defined by
>spec
>
>On Tue, May 21, 2024 at 6:25 PM Duan, Zhenzhong
> wrote:
>>
>>
>>
>> >-Original Message-
>> >From: Jason Wang
>> >Subject: Re: [PATCH] intel_iommu: Use the l
On 5/21/24 07:56, Björn Töpel wrote:
From: Björn Töpel
Virtio-based memory devices (virtio-mem/virtio-pmem) allows for
dynamic resizing of virtual machine memory, and requires proper
hotplugging (add/remove) support to work.
Add device memory support for RISC-V "virt" machine, and enable
vi
On 5/21/24 07:56, Björn Töpel wrote:
From: Björn Töpel
Add ACPI GED for the RISC-V "virt" machine, and wire up PC-DIMM memory
hotplugging support. Heavily based/copied from hw/arm/virt.c.
Signed-off-by: Björn Töpel
---
hw/riscv/Kconfig | 3 ++
hw/riscv/virt-acpi-build.c | 1
On Fri, May 24, 2024 at 10:00 AM Akihiko Odaki wrote:
>
> Based-on: <20240524-xkb-v4-0-2de564e5c...@daynix.com>
> ("[PATCH v4 0/4] Fix sanitizer errors with clang 18.1.1")
>
> This is changes suggested by Paolo Bonzini at:
> https://lore.kernel.org/all/C
ping.
> -Original Message-
> From: Yao Xingtao
> Sent: Wednesday, May 8, 2024 8:53 AM
> To: jonathan.came...@huawei.com; fan...@samsung.com
> Cc: qemu-devel@nongnu.org; Yao, Xingtao/姚 幸涛
> Subject: [PATCH v3] mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
>
> Since the kernel do
On 5/22/24 03:29, LIU Zhiwei wrote:
Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
additionally defines 8 MOP instructions named MOP.RR.n, where n
is an
On 5/22/24 03:29, LIU Zhiwei wrote:
Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
the reserved encoding space corresponding to C.LUI xn, 0.
Unlike the MOPs defined in the Zimop extension, the C.MOP.n ins
23.05.2024 04:46, Song Gao wrote:
vmstate does not save kvm_state_conter,
which can cause VM recovery from disk to fail.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Song Gao
Acked-by: Peter Xu
Message-Id: <20240508024732.3127792-1-gaos...@loongson.cn>
---
target/loongarch/machine.c | 6 --
Hello Hyman,
* Is this the same patch series as sent before..?
-> https://lists.nongnu.org/archive/html/qemu-devel/2024-04/msg00816.html
On Fri, 24 May 2024 at 12:02, Hyman Huang wrote:
> For VMs configured with the USB CDROM device:
>
> -drive file=/path/to/local/file,id=drive-usb-disk0,media
v2: Improve (mostly add detail) the qmp documentatation (thanks Markus!)
ACPI 6.5 introduced Generic Port Affinity Structures to close a system
description gap that was a problem for CXL memory systems.
It defines an new SRAT Affinity structure (and hence allows creation of an
ACPI Proximity Node
Before making additional modification, tidy up this misleading indentation.
Reviewed-by: Ankit Agrawal
Signed-off-by: Jonathan Cameron
---
hw/acpi/acpi_generic_initiator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/acpi/acpi_generic_initiator.c b/hw/acpi/acpi_generic
This will simplify reuse when adding acpi-generic-port.
Note that some error_printf() messages will now print acpi-generic-node
whereas others will move to type specific cases in next patch so
are left alone for now.
Signed-off-by: Jonathan Cameron
---
v2: Fix a typo in comment.
---
include/hw/a
The test to be added exercises many corners of the SRAT and HMAT
table generation.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +
tests/data/acpi/q35/APIC.acpihmat-generic-x | 0
tests/data/acpi/q35/CEDT.acpihmat-generic-x | 0
tests/data/acpi/q35/DSDT
These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators. Here we add these ports such that they may
be targets of hmat_lb records to describe the latenc
Add a test with 6 nodes to exercise most interesting corner cases
of SRAT and HMAT generation including the new Generic Initiator
and Generic Port Affinity structures. More details of the
set up in the following patch adding the table data.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-t
Given this is a new configuration, there are affects on APIC, CEDT
and DSDT, but the key elements are in SRAT (plus related data in
HMAT). The configuration has node to exercise many different combinations.
0) CPUs + Memory
1) GI only
2) GP only
3) CPUS only
4) Memory only
5) CPUs + HP memory
GI
23.05.2024 04:46, Song Gao wrote:
From: Jiaxun Yang
Higher bits for memory nodes were omitted at qemu_fdt_setprop_cells.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Jiaxun Yang
Reviewed-by: Song Gao
Message-Id: <20240520-loongarch-fdt-memnode-v1-1-5ea9be939...@flygoat.com>
Signed-off-by: Song
From: "Edgar E. Iglesias"
For xen, when checking for the first RAM (xen_memory), use
xen_mr_is_memory() rather than checking for a RAMBlock with
offset 0.
All Xen machines create xen_memory first so this has no
functional change for existing machines.
Signed-off-by: Edgar E. Iglesias
Reviewed-
From: "Edgar E. Iglesias"
Make MCACHE_BUCKET_SHIFT runtime configurable per cache instance.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
---
hw/xen/xen-mapcache.c | 54 ++-
1 file changed, 33 insertions(+), 21 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Always pass address with offset to xen_map_cache().
This is in preparation for support for grant mappings.
Since this is within a block that checks for offset == 0,
this has no functional changes.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
Revie
From: "Edgar E. Iglesias"
Add xen_mr_is_memory() to abstract away tests for the
xen_memory MR.
No functional changes.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
Acked-by: David Hildenbrand
---
hw/xen/xen-hvm-common.c | 10 --
include/sysemu/xen.h| 8 ++
From: "Edgar E. Iglesias"
Hi,
Grant mappings are a mechanism in Xen for guests to grant each other
permissions to map and share pages. These grants can be temporary
so both map and unmaps must be respected. See here for more info:
https://github.com/xen-project/xen/blob/master/docs/misc/grant-ta
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
Reviewed-by: Manos Pitsidianakis
---
hw/arm/xen_arm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
index 15fa7dfa84..6fad829ede 100644
--- a/hw/arm/xen_ar
From: "Edgar E. Iglesias"
Pass the ram_addr offset to xen_map_cache.
This is in preparation for adding grant mappings that need
to compute the address within the RAMBlock.
No functional changes.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: David Hildenbrand
Reviewed-by: Stefano Stabellini
-
From: "Edgar E. Iglesias"
When invalidating memory ranges, if we happen to hit the first
entry in a bucket we were never unmapping it. This was harmless
for foreign mappings but now that we're looking to reuse the
mapcache for transient grant mappings, we must unmap entries
when invalidated.
Sig
From: "Edgar E. Iglesias"
Add a second mapcache for grant mappings. The mapcache for
grants needs to work with XC_PAGE_SIZE granularity since
we can't map larger ranges than what has been granted to us.
Like with foreign mappings (xen_memory), machines using grants
are expected to initialize the
On Fri, 24 May 2024 at 00:38, Fabiano Rosas wrote:
> This is further indicated by the presence of the 'offset'
> argument, which indicates the start of the region where QEMU is
> allowed to write.
>
> Fix the issue by replacing the O_TRUNC flag on open by an ftruncate
> call, which will take the o
在2024年5月24日五月 上午11:10，Michael Tokarev写道：
> 23.05.2024 04:46, Song Gao wrote:
>> From: Jiaxun Yang
>>
>> Higher bits for memory nodes were omitted at qemu_fdt_setprop_cells.
>>
>> Cc: qemu-sta...@nongnu.org
>> Signed-off-by: Jiaxun Yang
>> Reviewed-by: Song Gao
>> Message-Id: <20240520-loong
On Fri, May 24, 2024 at 6:01 PM Prasad Pandit wrote:
> Hello Hyman,
>
> * Is this the same patch series as sent before..?
> ->
> https://lists.nongnu.org/archive/html/qemu-devel/2024-04/msg00816.html
Yes, exactly the same, I just refine the comment
>
>
> On Fri, 24 May 2024 at 12:02, Hyman H
On 5/22/24 06:13, LIU Zhiwei wrote:
Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to AMOs, loads
and stores defined in the base ISAs, and loads and stores of no more
than X
v2:
* Fix handling of SPIs.
* Remove pending state if not in new target list.
Sebastian Huber (2):
hw/intc/arm_gic: Fix set pending of PPIs
hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn
hw/intc/arm_gic.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
--
2.35.3
According to the GICv2 specification section 4.3.12, "Interrupt Processor
Targets Registers, GICD_ITARGETSRn":
"Any change to a CPU targets field value:
[...]
* Has an effect on any pending interrupts. This means:
- adding a CPU interface to the target list of a pending interrupt makes that
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Sebastian Huber
---
hw/i
On 5/23/24 09:40, LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 21d4e36405..9ec03a1edc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -118,6 +118,7 @@ const
Hi Zhiwei!
On 5/23/24 09:40, LIU Zhiwei wrote:
Zabha adds support AMO operations for byte and half word. If zacas has been
implemented,
zabha also adds support amocas.b and amocas.h.
More details is on the specification here:
https://github.com/riscv/riscv-zabha
The implemenation of zabha f
From: Nikita Shubin
Add a memcpy only model of I/OAT DMA found on some Xeon based
motherboards.
Signed-off-by: Nikita Shubin
---
Started as complementary device for a driver that can't get working
without any DMA.
So it's worth (at least) mentioning it on mail lists.
Tested with Linux dmates
Hello Peter,
thanks for the review.
On 20.05.24 15:58, Peter Maydell wrote:
On Tue, 7 May 2024 at 14:04, Sebastian Huber
wrote:
The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only
one core). Add support for up to two simulated cores.
Signed-off-by: Sebastian Huber
The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only
one core). Add support for up to two simulated cores.
Signed-off-by: Sebastian Huber
---
hw/arm/xilinx_zynq.c | 54 +++-
1 file changed, 33 insertions(+), 21 deletions(-)
diff
v2:
* Add Kconfig support
* Add array of CPUs to ZynqMachineState
* Add FIQ support
Sebastian Huber (2):
hw/arm/xilinx_zynq: Add cache controller
hw/arm/xilinx_zynq: Support up to two CPU cores
hw/arm/Kconfig | 1 +
hw/arm/xilinx_zynq.c | 55 +++-
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the
corresponding Qemu device to the xilinx-zynq-a9 machine.
Signed-off-by: Sebastian Huber
---
hw/arm/Kconfig | 1 +
hw/arm/xilinx_zynq.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kcon
Thomas Huth writes:
> On 24/05/2024 02.05, Nicholas Piggin wrote:
>> On Wed May 22, 2024 at 7:12 PM AEST, Thomas Huth wrote:
>>> On s390x, we recently had a regression that broke migration / savevm
>>> (see commit bebe9603fc ("hw/intc/s390_flic: Fix crash that occurs when
>>> saving the machine s
Prasad Pandit writes:
> On Fri, 24 May 2024 at 00:38, Fabiano Rosas wrote:
>> This is further indicated by the presence of the 'offset'
>> argument, which indicates the start of the region where QEMU is
>> allowed to write.
>>
>> Fix the issue by replacing the O_TRUNC flag on open by an ftruncat
Steve Sistare writes:
> Add blockers for cpr-exec migration mode for devices and options that do
> not support it.
>
> Signed-off-by: Steve Sistare
> ---
> accel/xen/xen-all.c| 5 +
> backends/hostmem-epc.c | 12 ++--
> hw/vfio/migration.c| 3 ++-
> replay/replay.c
Steve Sistare writes:
> This patch series adds the live migration cpr-exec mode. In this mode, QEMU
> stops the VM, writes VM state to the migration URI, and directly exec's a
> new version of QEMU on the same host, replacing the original process while
> retaining its PID. Guest RAM is preserve
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
Since s390_ccw_get_dev_info() takes an 'Error **' argument, best
practices suggest to return a bool. See the qapi/error.h Rules
section. While at it, modify the call in s390_ccw_realize().
Signed-off-by: Cédric Le Goater
Reviewed-by: Anthony Krow
On 5/21/24 07:56, Björn Töpel wrote:
From: Björn Töpel
Virtio-based memory devices (virtio-mem/virtio-pmem) allows for
dynamic resizing of virtual machine memory, and requires proper
hotplugging (add/remove) support to work.
Add device memory support for RISC-V "virt" machine, and enable
vi
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
The local error variable is kept for vfio_ccw_register_irq_notifier()
because it is not considered as a failing condition. We will change
how error reporting is done in following changes.
Remove the error_propagate() call.
Cc: Zhenzhong Duan
Signed
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
Since the realize() handler of CCWDeviceClass takes an 'Error **'
argument, best practices suggest to return a bool. See the api/error.h
Rules section. While at it, modify the call in s390_ccw_realize().
Signed-off-by: Cédric Le Goater
Reviewed-b
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
vfio_ccw_register_irq_notifier() and vfio_ap_register_irq_notifier()
errors are currently reported using error_report_err(). Since they are
not considered as failing conditions, using warn_report_err() is more
appropriate.
Signed-off-by: Cédric Le Go
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
Since the realize() handler of S390CCWDeviceClass takes an 'Error **'
argument, best practices suggest to return a bool. See the api/error.h
Rules section. While at it, modify the call in vfio_ccw_realize().
Signed-off-by: Cédric Le Goater
Review
On 5/22/24 1:01 PM, Cédric Le Goater wrote:
Use the 'Error **errp' argument of s390_ccw_realize() instead and
remove the error_propagate() call.
Signed-off-by: Cédric Le Goater
Reviewed-by: Anthony Krowiak
---
hw/s390x/s390-ccw.c | 13 +
1 file changed, 5 insertions(+),
On 5/15/24 4:20 AM, Zhenzhong Duan wrote:
This is to follow the coding standand in qapi/error.h to return bool
for bool-valued functions.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 4 ++--
hw/vfio/ap.c | 8 +++
On 5/15/24 4:20 AM, Zhenzhong Duan wrote:
This is to follow the coding standand in qapi/error.h to return bool
for bool-valued functions.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 2 +-
hw/vfio/ap.c | 2 +-
hw/vfio/c
On 5/23/24 16:53, Nicholas Piggin wrote:
This replaces the previous PR for tags/pull-ppc-for-9.1-1-20240524 note
this tag is tags/pull-ppc-for-9.1-1-20240524-1 (added -1 suffix). The
changelog and code are unchanged. Subject for BHRB patches are fixed
and trimmed for some MMU cleanup patches. So
Hi Zhenzhong
On 22/05/2024 08:23, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
Hi Zhenzhong
On 22/05/2024 08:23, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> According to spec, Page-Selective-within-Domain Invalidation (11b):
>
> 1. IOTLB entries
Hi Zhenzhong,
I already sent you my comments about this patch earlier (question about
checking pgtt) but here is a style review
On 22/05/2024 08:23, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you kno
Steve Sistare writes:
> Provide the VMStateDescription precreate field to mark objects that must
> be loaded on the incoming side before devices have been created, because
> they provide properties that will be needed at creation time. They will
> be saved to and loaded from their own QEMUFile,
On 5/24/2024 9:02 AM, Fabiano Rosas wrote:
Steve Sistare writes:
This patch series adds the live migration cpr-exec mode. In this mode, QEMU
stops the VM, writes VM state to the migration URI, and directly exec's a
new version of QEMU on the same host, replacing the original process while
ret
On 5/24/24 01:10, Paolo Bonzini wrote:
This is already handled in gen_eob(). Before adding another DISAS_*
case, remove the double calls.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 5/24/24 01:10, Paolo Bonzini wrote:
gen_helper_rsm cannot generate an exception, and reloads the flags.
So there's no need to spill cc_op and update cpu_eip, but on the
other hand cc_op must be reset to CC_OP_EFLAGS before returning.
It all works by chance, because by spilling cc_op before th
On 5/24/24 01:10, Paolo Bonzini wrote:
Place DISAS_* constants that update cpu_eip first, and
the "jump" ones last. Add comments explaining the differences
and usage.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 25 ++---
1 file changed, 22 insertions(+)
On 5/24/24 01:10, Paolo Bonzini wrote:
Place DISAS_* constants that update cpu_eip first, and
the "jump" ones last. Add comments explaining the differences
and usage.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 25 ++---
1 file changed, 22 insertions(+
On 5/24/24 01:10, Paolo Bonzini wrote:
syscall and sysret only have one exit, so they do not need to
generate the end-of-translation code inline. It can be
deferred to tb_stop.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 13 +++--
1 file changed, 11 insertions(+),
On 5/24/24 01:10, Paolo Bonzini wrote:
sti only has one exit, so it does not need to generate the
end-of-translation code inline. It can be deferred to tb_stop.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 13 -
target/i386/tcg/emit.c.inc | 4 +---
2 files ch
On 5/24/24 01:10, Paolo Bonzini wrote:
This is an invariant, since these cases of tb_stop() should only
be reached through the "instruction decoding completed" path of
i386_tr_translate_insn().
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+
On 5/24/24 01:10, Paolo Bonzini wrote:
Make gen_eob take the DISAS_* constant as an argument, so that
it is not necessary to have wrappers around it.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 60 +
1 file changed, 14 insertions(+), 46 d
On 5/24/24 01:10, Paolo Bonzini wrote:
Values other than OR_TMP0 were only ever used by MOV and MOVNTI
opcodes. Now that these have been converted to the new decoder,
remove the argument.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 33 -
1 f
On 5/24/24 01:10, Paolo Bonzini wrote:
The is_store argument of gen_ldst_modrm has only ever been passed
a constant. Just split the function in two.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 52 +
1 file changed, 29 insertions(+), 23 d
On 5/24/24 01:10, Paolo Bonzini wrote:
It is only used in MONITOR, where a direct call of gen_lea_v_seg
is simpler, and in XLAT. Inline it in the latter.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 9 +
target/i386/tcg/emit.c.inc | 2 +-
2 files changed, 2 insert
On 5/24/24 01:10, Paolo Bonzini wrote:
Use mo_stacksize for all stack accesses, including when
a 64-bit code segment is impossible and the code is
therefore checking only for SS32(s).
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 8
1 file changed, 4 insertions(+), 4
On 5/24/24 01:10, Paolo Bonzini wrote:
Generalize gen_stack_A0() to include an initial add and to use an arbitrary
destination. This is a common pattern and it is not a huge burden to
add the extra arguments to the only caller of gen_stack_A0().
Signed-off-by: Paolo Bonzini
---
target/i386/tc
1 - 100 of 209 matches
Mail list logo
