Hi Salil,
On 5/23/24 02:41, Salil Mehta wrote:
+void kvm_park_vcpu(CPUState *cpu);
+
+/**
+ * kvm_unpark_vcpu - unpark QEMU KVM vCPU context
+ * @s: KVM State
+ * @cpu: Architecture vCPU ID of the parked vCPU
s/@cpu/@vcpuid ?
Thanks
Harsh
+ *
+ * @returns: KVM fd
+ */
+int kvm_unpark_vcpu(KV
ase-commit: 7e1c0047015ffbd408e1aa4a5ec1abe4751dbf7e
change-id: 20240523-debugexit-22e7587adbeb
Best regards,
--
Thomas Weißschuh
On Mon, 20 May 2024 00:27, Dmitry Osipenko
wrote:
From: Pierre-Eric Pelloux-Prayer
virtio_gpu_virgl_get_num_capsets will return "num_capsets", but we can't
assume that capset_index 1 is always VIRGL2 once we'll support more capsets,
like Venus and DRM capsets. Register capsets dynamically to
On 5/22/24 18:10, Daniel P. Berrangé wrote:
On Wed, May 22, 2024 at 05:06:57PM +0200, Alexander Ivanov wrote:
Add an interactive mode to the guest-exec command in the QEMU Guest Agent
using the VSOCK communication mechanism. It enables interactive sessions
with the executed command in the guest,
On Mon, 20 May 2024 00:27, Dmitry Osipenko
wrote:
From: Antonio Caggiano
Request Venus when initializing VirGL and if venus=true flag is set for
virtio-gpu-gl device.
Signed-off-by: Antonio Caggiano
Signed-off-by: Huang Rui
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-gl.c
On Thu, 16 May 2024 15:03, Gerd Hoffmann wrote:
Remove myself from spice and ui entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINE
On Thu, 16 May 2024 15:03, Gerd Hoffmann wrote:
Remove myself from virtio-gpu entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
On Thu, 16 May 2024 15:03, Gerd Hoffmann wrote:
Remove myself from usb entries.
Flip status to "Orphan" for entries which have nobody else listed.
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
leading to termination of guest since errp is set to &error_fatal while
calling kvm_init_vcpu. This unexpected behaviour can be avoided by
pre-creating and par
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
leading to termination of guest since errp is set to &error_fatal while
calling kvm_init_vcpu. This unexpected behaviour can be avoided by
pre-creating and par
There are distinct helpers for creating and parking a KVM vCPU.
However, there can be cases where a platform needs to create and
immediately park the vCPU during early stages of vcpu init which
can later be reused when vcpu thread gets initialized. This would
help detect failures with kvm_create_vc
This helper provides an easy way to identify the next available free cpu
index which can be used for vcpu creation. Until now, this is being
called at a very later stage and there is a need to be able to call it
earlier (for now, with ppc64) hence the need to export.
Suggested-by: Nicholas Piggin
On Thu, 16 May 2024 18:48, "Edgar E. Iglesias" wrote:
From: "Edgar E. Iglesias"
Add a second mapcache for grant mappings. The mapcache for
grants needs to work with XC_PAGE_SIZE granularity since
we can't map larger ranges than what has been granted to us.
Like with foreign mappings (xen_memo
On Thu, 16 May 2024 18:48, "Edgar E. Iglesias" wrote:
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Stefano Stabellini
---
hw/arm/xen_arm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xen_arm.c b/hw/arm/xen_arm.c
index 15fa7dfa84..6fad829ede 10064
On Thu, May 23, 2024 at 09:12:51AM +0200, Denis V. Lunev wrote:
> On 5/22/24 18:10, Daniel P. Berrangé wrote:
> > On Wed, May 22, 2024 at 05:06:57PM +0200, Alexander Ivanov wrote:
> > > Add an interactive mode to the guest-exec command in the QEMU Guest Agent
> > > using the VSOCK communication mec
On 5/22/24 18:10, Daniel P. Berrangé wrote:
On Wed, May 22, 2024 at 05:06:57PM +0200, Alexander Ivanov wrote:
Add an interactive mode to the guest-exec command in the QEMU Guest Agent
using the VSOCK communication mechanism. It enables interactive sessions
with the executed command in the gue
On Wed, May 22, 2024 at 10:30:16PM +0300, Artyom Kunakovsky wrote:
> fix linker error if the project was configured by the './configure
> --cpu=unknown --target-list=riscv64-softmmu' command
Isn't this simply user error, with the right answer being
to pass a valid CPU target to --cpu, rather than
On 2024/5/21 下午8:32, Song Gao wrote:
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension definition so that the IRQ can
route to 256 vcpus.
Signed-off-by: Song Gao
---
include/hw/intc/loongarch_extioi.h | 21 +++
hw/intc/loonga
On 2024/5/21 下午8:32, Song Gao wrote:
Use MemTxAttrs interface read_with_attrs/write_with_attrs
for virt_iocsr_misc_ops.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw
The compilation error caused by attempting of use 128 bit
'__sync_val_compare_and_swap_16', which is supported on the host but not
enabled, I don't think this is expected behavior.
Also the patch is little incomplete, I already sent v2 patch, that applying the
flag only for x86_64 host.
With r
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 1/7] hw/s390x/ccw: Make s390_ccw_get_dev_info() return
>a bool
>
>Since s390_ccw_get_dev_info() takes an 'Error **' argument, best
>practices suggest to return a bool. See the qapi/error.h Rules
>section. While at it, modify th
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 2/7] s390x/css: Make CCWDeviceClass::realize return bool
>
>Since the realize() handler of CCWDeviceClass takes an 'Error **'
>argument, best practices suggest to return a bool. See the api/error.h
>Rules section. While at it,
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 3/7] hw/s390x/ccw: Remove local Error variable from
>s390_ccw_realize()
>
>Use the 'Error **errp' argument of s390_ccw_realize() instead and
>remove the error_propagate() call.
>
>Signed-off-by: Cédric Le Goater
Reviewed-by:
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 4/7] s390x/css: Make S390CCWDeviceClass::realize return
>bool
>
>Since the realize() handler of S390CCWDeviceClass takes an 'Error **'
>argument, best practices suggest to return a bool. See the api/error.h
>Rules section. Whil
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 5/7] vfio/ccw: Use the 'Error **errp' argument of
>vfio_ccw_realize()
>
>The local error variable is kept for vfio_ccw_register_irq_notifier()
>because it is not considered as a failing condition. We will change
>how error repo
On Thu, May 23, 2024 at 08:11:18AM +0300, Artyom Kunakovsky wrote:
> Fix linker error if the project was configured by the './configure
> --cpu=unknown --target-list=riscv64-softmmu' command
As with v1, why are you intentionally passing a bogus CPU target
name to the --cpu arg ? QEMU already cor
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH 7/7] vfio/{ap,ccw}: Use warn_report_err() for IRQ notifier
>registration errors
>
>vfio_ccw_register_irq_notifier() and vfio_ap_register_irq_notifier()
>errors are currently reported using error_report_err(). Since they are
>no
On Thu, 23 May 2024 at 09:04, Daniel P. Berrangé wrote:
>
> On Wed, May 22, 2024 at 10:30:16PM +0300, Artyom Kunakovsky wrote:
> > fix linker error if the project was configured by the './configure
> > --cpu=unknown --target-list=riscv64-softmmu' command
>
> Isn't this simply user error, with the
On 5/22/24 19:01, Cédric Le Goater wrote:
From: Zhenzhong Duan
When get name failed, we should call unrealize() so that
vfio_ccw_realize() is self contained.
Fixes: 909a6254eda ("vfio/ccw: Make vfio cdev pre-openable by passing a file
handle")
Signed-off-by: Zhenzhong Duan
Reviewed-by: Cé
On Thu, May 23, 2024 at 09:52:35AM +0100, Peter Maydell wrote:
> On Thu, 23 May 2024 at 09:04, Daniel P. Berrangé wrote:
> >
> > On Wed, May 22, 2024 at 10:30:16PM +0300, Artyom Kunakovsky wrote:
> > > fix linker error if the project was configured by the './configure
> > > --cpu=unknown --target
Am 22. Mai 2024 10:43:04 UTC schrieb Akihiko Odaki :
>The non-standard .fa library prefix breaks the link source
s/prefix/suffix/ in the commit message and subject.
Best regards,
Bernhard
>de-duplication done by Meson so drop it.
>
>The lack of link source de-duplication causes AddressSanitiz
>-Original Message-
>From: Jason Wang
>Subject: Re: [PATCH rfcv2 00/17] intel_iommu: Enable stage-1 translation
>for emulated device
>
>On Wed, May 22, 2024 at 2:25 PM Zhenzhong Duan
> wrote:
>>
>> Hi,
>>
>> Per Jason Wang's suggestion, iommufd nesting series[1] is split into
>> "Enable
Moving the following instructions to decodetree specification :
v{add,sub}{u,s}{b,h,w}s : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rat
Change Log :
1. Changes addressing all review comments by Richard in v1 :
Having seperate ops table instead of using a 3D array, using
TRANS_FLAGS instead of sinking flag check in the helper, proper flag
checks for the insns left behind from GEN_VXFORM_DUAL declarations.
2. Added a second
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vmx-impl.c.inc | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
>-Original Message-
>From: Thomas Huth
>Subject: Re: [PATCH rfcv2 17/17] tests/qtest: Add intel-iommu test
>
>On 22/05/2024 08.23, Zhenzhong Duan wrote:
>> Add the framework to test the intel-iommu device.
>>
>> Currently only tested cap/ecap bits correctness in scalable
>> modern mode.
Moving the following instructions to decodetree specification:
x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form
The changes were verfied by validating that the tcg ops generated by those
instructions remain the same, which were
Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.
Signed-off-by: Chinmay Rath
---
target/ppc/translate/vsx-impl.c.inc | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/tar
Moving a number of VSX arithmetic, max/min and logical instructions to
decodetree specification.
Also moving ISA300 flag check in the do_helper_XX3 methods in
vsx-impl.c.inc file; out of it, to make it usable for a larger num of
instructions.
Chinmay Rath (3):
target/ppc: Move ISA300 flag check
Moving the following instructions to decodetree specification :
xxl{and, andc, or, orc, nor, xor, nand, eqv}: XX3-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-of
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 21 +++--
> target/arm/tcg/translate-a64.c | 86 +++---
> 2 files changed, 54 insertions(+), 53 deletions(-)
Reviewed-by: Peter May
On 2024/05/22 23:36, Peter Maydell wrote:
On Wed, 22 May 2024 at 12:47, Daniel P. Berrangé wrote:
On Wed, May 22, 2024 at 12:35:23PM +0100, Peter Maydell wrote:
On Wed, 22 May 2024 at 11:49, Akihiko Odaki wrote:
This fixes LeakSanitizer complaints with xkbcommon 1.6.0.
Signed-off-by: Akih
Alexander Ivanov writes:
> There are two python scripts in the attachment:
> vsock_guest_exec_simple.py - simple example of a client;
> vsock_guest_exec_test.py - tests with different payload size.
>
> The last file should be copied to a guest VM. Edit SRV_PATH variable
> in the host copy of the
On 5/22/24 11:44 AM, Eugenio Perez Martin wrote:
On Mon, May 20, 2024 at 3:01 PM Jonah Palmer wrote:
Add the boolean 'in_order_filled' member to the VirtQueueElement structure.
The use of this boolean will signify whether the element has been processed
and is ready to be flushed (so long as
On 5/22/24 11:45 AM, Eugenio Perez Martin wrote:
On Mon, May 20, 2024 at 3:01 PM Jonah Palmer wrote:
Add VIRTIO_F_IN_ORDER feature support in virtqueue_split_pop and
virtqueue_packed_pop.
VirtQueueElements popped from the available/descritpor ring are added to
the VirtQueue's used_elems ar
> From: Harsh Prateek Bora
> Sent: Thursday, May 23, 2024 8:05 AM
>
> Hi Salil,
>
> On 5/23/24 02:41, Salil Mehta wrote:
> > +void kvm_park_vcpu(CPUState *cpu);
> > +
> > +/**
> > + * kvm_unpark_vcpu - unpark QEMU KVM vCPU context
> > + * @s: KVM State
> > + * @cpu: Architecture vCPU
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 11 +
> target/arm/tcg/translate-a64.c | 78 +-
> 2 files changed, 21 insertions(+), 68 deletions(-)
Reviewed-by: Peter Maydell
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 6
> target/arm/tcg/translate-a64.c | 54 +++---
> 2 files changed, 10 insertions(+), 50 deletions(-)
>
Reviewed-by: Peter Maydel
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 11
> target/arm/tcg/translate-a64.c | 97 --
> 2 files changed, 32 insertions(+), 76 deletions(-)
Reviewed-by: Peter Maydell
On Mon, 6 May 2024 at 02:16, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 5
> target/arm/tcg/translate-a64.c | 50 ++
> 2 files changed, 8 insertions(+), 47 deletions(-)
Reviewed-by: Peter Maydell
On 5/22/24 21:30, Artyom Kunakovsky wrote:
fix linker error if the project was configured by the './configure
--cpu=unknown --target-list=riscv64-softmmu' command
Signed-off-by: Artyom Kunakovsky
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 8 ++
> target/arm/tcg/translate-a64.c | 132 +++--
> 2 files changed, 51 insertions(+), 89 deletions(-)
>
Reviewed-by: Peter Maydell
On Mon, 6 May 2024 at 02:04, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 10
> target/arm/tcg/translate-a64.c | 43 ++
> 2 files changed, 22 insertions(+), 31 deletions(-)
>
Reviewed-by: Peter Ma
On Thu, May 23, 2024 at 9:47 AM Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> wrote:
> On Thu, 16 May 2024 18:48, "Edgar E. Iglesias"
> wrote:
> >From: "Edgar E. Iglesias"
> >
> >Add a second mapcache for grant mappings. The mapcache for
> >grants needs to work with XC_PAGE_SIZE granular
If QTestState was already CLOSED due to error, calling qtest_clock_step()
afterwards makes no sense and only raises false-crash with message:
"assertion timer != NULL failed".
Signed-off-by: Dmitry Frolov
---
tests/qtest/fuzz/virtio_net_fuzz.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
On 5/22/24 12:07 PM, Eugenio Perez Martin wrote:
On Mon, May 20, 2024 at 3:01 PM Jonah Palmer wrote:
Add VIRTIO_F_IN_ORDER feature support for the virtqueue_fill operation.
The goal of the virtqueue_ordered_fill operation when the
VIRTIO_F_IN_ORDER feature has been negotiated is to search
On Wednesday, May 22, 2024 2:54:51 PM CEST Thomas Huth wrote:
> On 16/05/2024 14.03, Gerd Hoffmann wrote:
[...]
> > ALSA Audio backend
> > -M: Gerd Hoffmann
> > R: Christian Schoenebeck
> > S: Odd Fixes
> > F: audio/alsaaudio.c
>
> I'd also suggest that Christian either upgrade from R: t
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 4
> target/arm/tcg/translate-a64.c | 43 +++---
> 2 files changed, 18 insertions(+), 29 deletions(-)
>
Reviewed-by: Peter Maydel
On Thu, May 23, 2024 at 12:30 PM Jonah Palmer wrote:
>
>
>
> On 5/22/24 12:07 PM, Eugenio Perez Martin wrote:
> > On Mon, May 20, 2024 at 3:01 PM Jonah Palmer
> > wrote:
> >>
> >> Add VIRTIO_F_IN_ORDER feature support for the virtqueue_fill operation.
> >>
> >> The goal of the virtqueue_ordered_
On Tue, Apr 9, 2024 at 3:19 PM Ross Lagerwall wrote:
>
> On Tue, Apr 9, 2024 at 11:20 AM Anthony PERARD
> wrote:
> >
> > On Thu, Apr 04, 2024 at 03:08:33PM +0100, Ross Lagerwall wrote:
> > > diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
> > > index 1627da739822..1116b3978938 100
On 5/23/24 6:47 AM, Eugenio Perez Martin wrote:
On Thu, May 23, 2024 at 12:30 PM Jonah Palmer wrote:
On 5/22/24 12:07 PM, Eugenio Perez Martin wrote:
On Mon, May 20, 2024 at 3:01 PM Jonah Palmer wrote:
Add VIRTIO_F_IN_ORDER feature support for the virtqueue_fill operation.
The goal o
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 13 +
> target/arm/tcg/translate-a64.c | 426 +++--
> 2 files changed, 152 insertions(+), 287 deletions(-)
>
Reviewed-by: Peter Maydel
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Convert all forms (scalar, vector, scalar indexed, vector indexed),
> which allows us to remove switch table entries elsewhere.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 May 2024 at 02:08, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-a64.h| 4 +
> target/arm/tcg/translate.h | 5 +
> target/arm/tcg/a64.decode | 27 +
> target/arm/tcg/translate-a64.c | 205 +-
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 4 +
> target/arm/tcg/a64.decode | 17
> target/arm/tcg/translate-a64.c | 168 +
> target/arm/tcg/vec_helper.c| 4
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 6
> target/arm/tcg/translate.h | 30 +++
> target/arm/tcg/translate-a64.c | 44 +--
> target/arm/tcg/translate-vf
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> This is the last instruction within disas_fp_2src,
> so remove that and its subroutines.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 1 +
> target/arm/tcg/translate-a64.c | 177 +
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 2 +
> target/arm/tcg/a64.decode | 22 +++
> target/arm/tcg/translate-a64.c | 241 +
> target/arm/tcg/vec_helper.c| 14
On Mon, 6 May 2024 at 02:15, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 5 +
> target/arm/tcg/a64.decode | 30 ++
> target/arm/tcg/translate-a64.c | 188 +++--
> target/arm/tcg/vec_helper.c|
On Mon, 6 May 2024 at 02:09, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 1 +
> target/arm/tcg/a64.decode | 6
> target/arm/tcg/translate-a64.c | 60 ++
> target/arm/tcg/vec_helper.c| 6 ++
On Mon, 6 May 2024 at 02:07, Richard Henderson
wrote:
>
> These are the last instructions within handle_3same_float
> and disas_simd_scalar_three_reg_same_fp16 so remove them.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 12 ++
> target/arm/tcg/translate-a64.c |
On Mon, 6 May 2024 at 02:07, Richard Henderson
wrote:
>
> This fixes a bug in which scalar half-precision did not
> diagnose sz == 1 as UNDEFINED.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 4 ++
> target/arm/tcg/a64.decode | 12 +
> target/arm/tcg/tr
>From vmcoreinfo 'phys_base' is a decimal instead a hexadecimal so use base of
10 instead of 16 when converting this string.
Signed-off-by: Zhibin Li
---
Hi everyone. I'm trying to use 'dump-guest-memory' QMP command to generate a
kdump-compressed vmcore file which can be consumed by makedumpfil
Zabha adds support AMO operations for byte and half word. If zacas has been
implemented,
zabha also adds support amocas.b and amocas.h.
More details is on the specification here:
https://github.com/riscv/riscv-zabha
The implemenation of zabha follows the way of AMOs and zacas.
This patch set is
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rva.c.inc | 21 -
target/riscv/translate.c| 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131
target/riscv/translate.c| 4 +-
4 files changed, 155 insertions(+
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/translate.c| 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
b/target/riscv/insn_trans/tra
Signed-off-by: LIU Zhiwei
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8a4801d442..eee48f92d3 100644
--- a/tar
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 21d4e36405..9ec03a1edc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -118,6 +118,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
I
Signed-off-by: LIU Zhiwei
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 41050246f3..849af82ddf 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6 +954,26 @@ typedef enum {
r
On Wed, May 22, 2024 at 08:34:13PM +0800, Aaron Lu wrote:
>
> I do not have Windows VM right now and will report back once I finished
> testing there.
Tested with a Windows 10 VM and turnes out virtio pci devices always
use MSI no matter vIOMMU and bypass iommu are specified or not.
So according
Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
---
target/hexagon/idef-parser/idef-pars
Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.
Macros defining the sizes of these buffers were left behind, remove
them.
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
--
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
---
target/hexagon/idef-parser/parser-helpers.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/target/hexagon/idef-parser/parser-helpers.h
b/target/hexagon/idef-parser/parser-helpers.h
index 7
gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and in
Was running idef-parser with ASAN and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization. This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicate va
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Convert all forms (scalar, vector, scalar indexed, vector indexed),
> which allows us to remove switch table entries elsewhere.
>
> Signed-off-by: Richard Henderson
> @@ -671,3 +694,25 @@ INS_general 0 1 00 1110 000 imm:5 0 0011 1
On Thu, May 23, 2024 at 08:52:35PM +0800, Aaron Lu wrote:
> On Wed, May 22, 2024 at 08:34:13PM +0800, Aaron Lu wrote:
> >
> > I do not have Windows VM right now and will report back once I finished
> > testing there.
>
> Tested with a Windows 10 VM and turnes out virtio pci devices always
> use M
On 5/23/24 06:00, Peter Maydell wrote:
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
Convert all forms (scalar, vector, scalar indexed, vector indexed),
which allows us to remove switch table entries elsewhere.
Signed-off-by: Richard Henderson
@@ -671,3 +694,25 @@ INS_general
The default value of the @share option of the @MemoryBackendProperties
eally depends on the backend type, so let's document it explicitly and
add the default value where it was missing.
Cc: David Hildenbrand
Suggested-by: Markus Armbruster
Signed-off-by: Stefano Garzarella
---
I followed how we
On Mon, 6 May 2024 at 02:08, Richard Henderson
wrote:
>
> These are the last instructions within disas_simd_three_reg_same_fp16,
> so remove it.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h | 7 -
> target/arm/tcg/translate-neon.c | 55 ++---
> target/arm/tcg/vec_helper.c | 45 ---
> 3 files c
On Mon, 6 May 2024 at 02:07, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 5 ++
> target/arm/tcg/translate.h | 3 +
> target/arm/tcg/a64.decode | 6 ++
> target/arm/tcg/gengvec.c | 12
> target/arm/tcg/translate
On Mon, 6 May 2024 at 02:08, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> These are the last instructions within handle_simd_3same_pair
> so remove it.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 May 2024 at 02:14, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-neon.c | 78 ++---
> 1 file changed, 4 insertions(+), 74 deletions(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 6 May 2024 at 02:05, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/a64.decode | 10 +++
> target/arm/tcg/translate-a64.c | 144 ++---
> 2 files changed, 51 insertions(+), 103 deletions(-)
>
Reviewed-by: Peter Mayde
On Mon, 6 May 2024 at 02:06, Richard Henderson
wrote:
>
> This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 5/23/24 02:44, Chinmay Rath wrote:
Chinmay Rath (2):
target/ppc: Move VMX integer add/sub saturate insns to decodetree.
target/ppc: Improve VMX integer add/sub saturate instructions.
Reviewed-by: Richard Henderson
r~
On Mon, 6 May 2024 at 02:07, Richard Henderson
wrote:
>
> No need for a full comparison; xor produces non-zero bits
> for QC just fine.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/gengvec.c | 32
> 1 file changed, 16 insertions(+), 16 deletions(-)
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