Re: [PATCH v2 03/20] vfio/helpers: Use g_autofree in vfio_set_irq_signaling()

On 5/22/24 06:39, Zhenzhong Duan wrote: Local pointer irq_set is freed before return from vfio_set_irq_signaling(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan Reviewed-by: Cédric Le Goater Thanks, C. --- hw/vfio/helpers.c | 3 +-- 1 file changed, 1

Re: [PATCH v2 09/20] vfio/pci: Make vfio_pci_relocate_msix() and vfio_msix_early_setup() return a bool

On 5/22/24 06:40, Zhenzhong Duan wrote: Since vfio_pci_relocate_msix() and vfio_msix_early_setup() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_msix_early_setup() to avoid calling error_propa

Re: [PATCH v2 10/20] vfio/pci: Make vfio_populate_device() return a bool

On 5/22/24 06:40, Zhenzhong Duan wrote: Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. By this chance, pass errp directly to vfio_populate_device() to avoid calling error_propagate(). Signed-off-by: Zhenzho

[PATCH rfcv2 02/17] intel_iommu: Make pasid entry type check accurate

When guest configures Nested Translation(011b) or First-stage Translation only (001b), type check passed unaccurately. Fails the type check in those cases as their simulation isn't supported yet. Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation") Suggested-by: Yi Liu Signed-off-by: Zhen

[PATCH rfcv2 07/17] intel_iommu: check if the input address is canonical

From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 21 + 2 files changed

[PATCH rfcv2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

Add an new element scalable_mode in IntelIOMMUState to mark scalable modern mode, this element will be exposed as an intel_iommu property finally. For now, it's only a placehholder and used for cap/ecap initialization, compatibility check and block host device passthrough until nesting is supporte

[PATCH rfcv2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through (PGTT=100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=001b)

[PATCH rfcv2 12/17] intel_iommu: add an internal API to find an address space with PASID

From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/h

[PATCH rfcv2 06/17] intel_iommu: Implement stage-1 translation

From: Yi Liu This adds stage-1 page table walking to support stage-1 only transltion in scalable modern mode. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 17 + hw/i386/intel_iommu.c | 128 +++

[PATCH rfcv2 14/17] intel_iommu: piotlb invalidation should notify unmap

This is used by some emulated devices which caches address translation result. When piotlb invalidation issued in guest, those caches should be refreshed. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 35 ++- 1 file changed, 34 i

[PATCH rfcv2 08/17] intel_iommu: set accessed and dirty bits during first stage translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 + 2 files changed, 28 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH rfcv2 17/17] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan --- MAINTAINERS| 1 + tests/qtest/intel-iommu-test.c

[PATCH rfcv2 00/17] intel_iommu: Enable stage-1 translation for emulated device

Hi, Per Jason Wang's suggestion, iommufd nesting series[1] is split into "Enable stage-1 translation for emulated device" series and "Enable stage-1 translation for passthrough device" series. This series enables stage-1 translation support for emulated device in intel iommu which we called "mode

[PATCH rfcv2 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation

Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mdoe introduced, guest could send PADID-selective PASID-based iotlb invalidation to flush both stage-1 and stage-2 entries. Signed-off-by: Zhen

[PATCH rfcv2 01/17] intel_iommu: Update version to 3.0 and add the latest fault reasons

From: Yu Zhang The scalable mode was introduced in VTD spec 3.0, now that the scalable mode is already supported, bump version to 3.0. In spec 3.0 some more detailed fault reasons are defined for scalable mode. So introduce them into emulation code, see spec section 7.1.2 for details. Guest ker

[PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode. In other cases, it is still default to 39

[PATCH rfcv2 16/17] intel_iommu: Modify x-scalable-mode to be string option

From: Yi Liu Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. While this vIOMMU implementation wants to simplify it for user by providing typical combinations. User could config it by "x-scalabl

[PATCH rfcv2 05/17] intel_iommu: Rename slpte to pte

From: Yi Liu Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation, rename slpte to pte to make it generic. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 ++- include/hw/i386/intel_iommu.h | 2 +- hw

[PATCH rfcv2 11/17] intel_iommu: Extract device IOTLB invalidation logic

From: Clément Mathieu--Drif This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation No functional changes intended. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 57 ++

[PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension

The may be operation means that it has an initial behavior which can be redefined by later extensions to perform some other action. The May-Be-Operations includes two extension: zimop and zcmop. Zimop has 40 instructions, whose initial behavior is writing zero to the destination register. Zcmop,

[PATCH 1/4] target/riscv: Add zimop extension

Zimop extension defines an encoding space for 40 MOPs.The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and 7. These 40 MOPs i

[PATCH rfcv2 10/17] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3

[PATCH 2/4] disas/riscv: Support zimop disassemble

Signed-off-by: LIU Zhiwei --- disas/riscv.c | 100 ++ 1 file changed, 100 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e236c8b5b7..4cd769f165 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -906,6 +906,46 @@ typedef enum {

[PATCH rfcv2 13/17] intel_iommu: add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw/i386/intel_iommu_internal.

[PATCH 3/4] target/riscv: Add zcmop extension

Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions are defined to not write any re

[PATCH 4/4] disas/riscv: Support zcmop disassemble

Although in QEMU disassemble, we usually lift compressed instruction to an normal format when display the instruction name. For C.MOP.n, it is more reasonable to directly display its compressed name, because its behavior can be redefined by later extension. Signed-off-by: LIU Zhiwei --- disas/ri

Re: [PATCH v3 2/2] cxl/core: add poison creation event handler

Shiyang Ruan wrote: [..] > >> My expectation is MF_ACTION_REQUIRED is not appropriate for CXL event > >> reported errors since action is only required for direct consumption > >> events and those need not be reported through the device event queue. > > Got it. > > I'm not very sure about 'Host wri

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