Re: [PATCH ats_vtd v1 03/24] intel_iommu: check if the input address is canonical

Hi zhenzhong, On 14/05/2024 09:34, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi Clement, > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Subject

Re: [PATCH v6 3/9] migration: Extend migration_file_set_error() with Error* argument

Hi Cédric, On 5/14/24 17:31, Cédric Le Goater wrote: > Use it to update the current error of the migration stream if > available and if not, simply print out the error. Next changes will > update with an error to report. > > Reviewed-by: Avihai Horon > Acked-by: Fabiano Rosas > Signed-off-by: C

[PATCH ats_vtd v2 05/25] intel_iommu: return page walk level even when the translation fails

We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clément Mathieu--Drif -

[PATCH ats_vtd v2 09/25] pcie: add helper to declare PASID capability for a pcie device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1 + 4 files changed, 33 inserti

[PATCH ats_vtd v2 02/25] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb (avoids a 'loosing precision' warning). VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd v2 12/25] intel_iommu: add an internal API to find an address space with PASID

This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3bb4d385a8

[PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 53f17d66c0..c4ebd4569e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2299,6 +2299,7 @@ out: entry

[PATCH ats_vtd v2 17/25] intel_iommu: implement the get_address_space_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fd4710ba28..e48b169cda 100644 --- a/hw/i386/intel_i

[PATCH ats_vtd v2 16/25] pci: add a pci-level initialization function for iommu notifiers

We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd v2 00/25] ATS support for VT-d

This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on a PCI-level API for ATS to b

[PATCH ats_vtd v2 04/25] intel_iommu: set accessed and dirty bits during first stage translation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 25 + hw/i386/intel_iommu_internal.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0ecf00f37a..252364893b 100644 --- a/hw/i386/intel_io

[PATCH ats_vtd v2 19/25] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 2c0e964c07..198b71e9af 100644 --- a/include/exec/memory.h +++ b/include/exec/mem

[PATCH ats_vtd v2 01/25] intel_iommu: fix FRCD construction macro.

The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH ats_vtd v2 13/25] intel_iommu: add support for PASID-based device IOTLB invalidation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 42 ++ hw/i386/intel_iommu_internal.h | 10 2 files changed, 47 insertions(+), 5 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 166103510e..fd4710ba28

[PATCH ats_vtd v2 21/25] atc: generic ATC that can be used by PCIe devices that support SVM

As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build |

[PATCH ats_vtd v2 24/25] intel_iommu: set the address mask even when a translation fails

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_

[PATCH ats_vtd v2 25/25] intel_iommu: add support for ATS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 67b9ff4934..7421a99373 100644

[PATCH ats_vtd v2 18/25] intel_iommu: implement the get_memory_region_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e48b169cda..53f17d66c0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5997,9 +5997,24 @@ stat

[PATCH ats_vtd v2 07/25] intel_iommu: do not consider wait_desc as an invalid descriptor

Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index dbdf13470d..373f3d254a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3362,6

[PATCH ats_vtd v2 22/25] memory: add an API for ATS support

IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 ++ system/memory.c

[PATCH ats_vtd v2 10/25] pcie: helper functions to check if PASID and ATS are enabled

ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include/hw/pci/pcie.h | 3 +++ 2 fil

[PATCH ats_vtd v2 03/25] intel_iommu: check if the input address is canonical

First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 21 + hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i

Re: [PATCH 4/9] migration: Add direct-io parameter

Fabiano Rosas writes: > Markus Armbruster writes: > >> Peter Xu writes: >> >>> On Fri, May 03, 2024 at 05:49:32PM -0300, Fabiano Rosas wrote: Peter Xu writes: > On Fri, Apr 26, 2024 at 11:20:37AM -0300, Fabiano Rosas wrote: >> Add the direct-io migration parameter that tel

Re: [PATCH v2 06/15] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

On Wed, May 15, 2024 at 02:25:31PM GMT, Eric Cheng wrote: > On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > > > Generate device tree entry for riscv-iommu PCI device, along with > > mapping all PCI device identifiers to the single IOMMU device instance. > > > >

[PATCH ats_vtd v2 06/25] intel_iommu: extract device IOTLB invalidation logic

This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24 deletions(-)

[PATCH ats_vtd v2 11/25] intel_iommu: declare supported PASID size

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 373f3d254a..3bb4d385a8 100644 --- a/hw/i386/intel_iommu.c +++ b/h

[PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 045d69f4c1..e5f72f9f1d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/

[PATCH ats_vtd v2 08/25] memory: add permissions in IOMMUAccessFlags

This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification)

[PATCH ats_vtd v2 23/25] pci: add a pci-level API for ATS

Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clément Mathie

[PATCH ats_vtd v2 15/25] pci: add IOMMU operations to get address spaces and memory regions with PASID

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e5f72f9f1d..2b42b4e4cc 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci

Re: [PATCH v6 4/9] vfio/migration: Add an Error** argument to vfio_migration_set_state()

Hi Cédric, On 5/14/24 17:31, Cédric Le Goater wrote: > Add an Error** argument to vfio_migration_set_state() and adjust > callers, including vfio_save_setup(). The error will be propagated up > to qemu_savevm_state_setup() where the save_setup() handler is > executed. > > Modify vfio_vmstate_chan

Re: [PATCH v2 24/45] target/hppa: Use TCG_COND_TST* in trans_bb_imm

On 5/14/24 18:36, Helge Deller wrote: -tcg_gen_shli_i64(tmp, tcg_r, p); - -cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); +cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE, +load_gpr(ctx, a->r), 1ull << (63 - p)); I wonder if this ac

Re: [PATCH v2 32/45] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB

On 5/14/24 22:11, Helge Deller wrote: * Richard Henderson : In preparation for CF_PCREL. store the iaoq_f in 3 parts: high bits in cs_base, middle bits in pc, and low bits in priv. For iaoq_b, set a bit for either of space or page differing, else the page offset. Install iaq entries before goto

[PATCH v10 0/2] S3 support

Hi all, This is the v10 patch to support S3. v10 makes below changes: * patch#1 change the description of commit message. * patch#2 no changes. Best regards, Jiqian Chen v9 makes below changes: * patch#1 no changes * patch#2 remove unnecessary parentheses. add some comments to remind

[PATCH v10 2/2] virtio-pci: implement No_Soft_Reset bit

In current code, when guest does S3, virtio-gpu are reset due to the bit No_Soft_Reset is not set. After resetting, the display resources of virtio-gpu are destroyed, then the display can't come back and only show blank after resuming. Implement No_Soft_Reset bit of PCI_PM_CTRL register, then gues

[PATCH v10 1/2] virtio-pci: only reset pm state during resetting

Fix bug imported by 27ce0f3afc9dd ("fix Power Management Control Register for PCI Express virtio devices" After this change, observe that QEMU may erroneously clear the power status of the device, or may erroneously clear non writable registers, such as NO_SOFT_RESET, etc. Only state of PM_CTRL

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Thank you, I will correct it in the patch v2. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:55寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > From: Jim Shu > > > > Public the conversion function of priv_spec and string in cpu.h, so that > > tcg-cpu.c could also use it. > > > > Signed-off-by:

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Thank you, I will correct it in the patch v2. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:51寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in > > SMSTATEEN0 that controls access to the hedeleg. > > > > Signed-off-by: Fea.Wang

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

OK, I will correct it in the patch v2. Thank you. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:49寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH > > and HEDELEGH for exception codes 32-47 for reserving and exception codes > >

[PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Based on the change log for the RISC-V privilege 1.13 spec, add the support for ss1p13. Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 Lists what to do without clarification or document format. * Redefined misa.MXL to be read-only, making MXLEN a

[PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tc

[PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PATCH 2/5] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files ch

[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9 insertions(+

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be cont

[PULL 04/34] accel/tcg: Reorg translator_ld*

Reorg translator_access into translator_ld, with a more memcpy-ish interface. If both pages are in ram, do not go through the caller's slow path. Assert that the access is within the two pages that we are prepared to protect, per TranslationBlock. Allow access prior to pc_first, so long as it is

[PULL 03/34] accel/tcg: Pass DisasContextBase to translator_fake_ldb

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h| 5 +++-- accel/tcg/translator.c | 2 +- target/s390x/tcg/translate.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/translator.h b/include/exec/trans

[PULL 06/34] accel/tcg: Record mmio bytes during translation

This will be able to replace plugin_insn_append, and will be usable for disassembly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 12 accel/tcg/translator.c| 41 +++ 2 files changed, 53

[PULL 31/34] target/xtensa: Use translator_ldub in xtensa_insn_len

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 42109d33ad..75b7bfda4c 100644 --- a/target/xtensa/translate.c +++ b

[PULL 25/34] target/i386: Use translator_ldub for everything

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ed601474a9..76be742580 100644 --- a/target/i386/tcg/tra

[PULL 22/34] target/s390x: Disassemble EXECUTEd instructions

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 95d4d6ebc3..bac033c63c 100644 --- a/target/s390x/tcg/tr

[PULL 02/34] accel/tcg: Hide in_same_page outside of a target-specific context

While there are other methods that could be used to replace TARGET_PAGE_MASK, the function is not really required outside the context of target-specific translation. This makes the header usable by target independent code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PULL 28/34] target/cris: Use cris_fetch in translate_v10.c.inc

Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/translate.c | 1 - target/cris/translate_v10.c.inc | 30 +- 2 files changed, 9 insertions(+), 22 deletions(-) diff --git a/target/cris/transl

[PULL 13/34] plugins: Use DisasContextBase for qemu_plugin_insn_haddr

We can delay the computation of haddr until the plugin actually requests it. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 4 accel/tcg/plugin-gen.c | 20 plugins/api.c | 25 - 3 files chan

[PULL 34/34] tcg/loongarch64: Fill out tcg_out_{ld, st} for vector regs

TCG register spill/fill uses tcg_out_ld/st with all types, not necessarily going through INDEX_op_{ld,st}_vec. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2336 Signed-off-by: Richard Hende

[PULL 27/34] target/cris: Use translator_ld* in cris_fetch

Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/translate.c | 25 - 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index b5410189d4..bb2d

[PULL 29/34] target/riscv: Use translator_ld* for everything

Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c999e942e1..2c27fd4ce1 100644 --- a

[PULL 09/34] plugins: Copy memory in qemu_plugin_insn_data

Instead of returning a host pointer, copy the data into storage provided by the caller. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/qemu/qemu-plugin.h | 15 +++ contrib/plugins/execlog.c | 5 +++-- contrib/plugins/howvec.c | 4 ++-- plugins/

[PULL 00/34] tcg patch queue

The following changes since commit 3d48b6b687c558a042d91370633b91c6e29e0e05: Merge tag 'pull-request-2024-05-14' of https://gitlab.com/thuth/qemu into staging (2024-05-14 17:24:04 +0200) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202

[PULL 08/34] accel/tcg: Record DisasContextBase in tcg_ctx for plugins

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + accel/tcg/plugin-gen.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 135e36d729..2a1c080bab 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/

[PULL 32/34] target/s390x: Use translator_lduw in get_next_pc

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bac033c63c..ebd96abe6c 100644 --- a/target/s390x/tcg/trans

[PULL 33/34] accel/tcg: Remove cpu_ldsb_code / cpu_ldsw_code

From: Philippe Mathieu-Daudé Previous commits replaced them by translator_ld* calls. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240405131532.40913-1-phi...@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 10 -- 1 file changed, 10 deletions(-) diff

[PULL 24/34] target/microblaze: Use translator_ldl

Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9746a6d479..4beaf69e76

[PULL 14/34] plugins: Use DisasContextBase for qemu_plugin_tb_vaddr

We do not need to separately record the start of the TB. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 1 - accel/tcg/plugin-gen.c | 3 +-- plugins/api.c | 3 ++- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/

[PULL 30/34] target/rx: Use translator_ld*

Reviewed-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/rx/translate.c | 27 ++- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 92fb2b43ad..9b81cf20b3

[PULL 05/34] accel/tcg: Cap the translation block when we encounter mmio

Do not allow translation to proceed beyond one insn with mmio, as we will not be caching the TranslationBlock. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 4 1 file changed, 4 insertions(+) diff --git a/accel/tcg/translator.c b/accel/t

[PULL 07/34] accel/tcg: Record when translator_fake_ldb is used

Remove left-over comment from commit dcd092a063 ("accel/tcg: Improve can_do_io management"). Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 3 ++- accel/tcg/translator.c| 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git

Re: [PATCH 00/11] maintainer updates (plugins, testing) pre-PR

On Tue, May 14, 2024 at 06:42:42PM +0100, Alex Bennée wrote: > This is mostly plugin related stuff which is all ready to go however > I have a few miscellaneous testing updates which would appreciate the > review. Reviewed-by: Michael S. Tsirkin > Thanks. > > Alex Bennée (2): > tests/tcg: do

[PULL 11/34] plugins: Use translator_st for qemu_plugin_insn_data

Use the bytes that we record for the entire TB, rather than a per-insn GByteArray. Record the length of the insn in plugin_gen_insn_end rather than infering from the length of the array. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/qemu/plugin.h | 14 +-

[PULL 26/34] target/avr: Use translator_lduw

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 6df93d4c77..2d51892115 100644 --- a/target/avr/translate.c +++ b/target/avr/

[PULL 01/34] accel/tcg: Use vaddr in translator_ld*

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 21 + accel/tcg/translator.c| 15 --- target/hexagon/translate.c| 1 + target/microblaze/translate.c | 1 + 4 files changed, 19 insertions(+), 19

[PULL 16/34] accel/tcg: Provide default implementation of disas_log

Almost all of the disas_log implementations are identical. Unify them within translator_loop. Drop extra Priv/Virt logging from target/riscv. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 9 - target/alpha/translate.c

[PULL 18/34] disas: Split disas.c

The routines in disas-common.c are also used from disas-mon.c. Otherwise the rest of disassembly is only used from tcg. While we're at it, put host and target code into separate files. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- disas/disas-internal.h | 4 + inclu

[RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13

Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 4 files ch

[PULL 21/34] target/s390x: Fix translator_fake_ld length

The ilen value extracted from ex_value is the length of the EXECUTE instruction itself, and so is the increment to the pc. However, the length of the synthetic insn is located in the opcode like all other instructions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tar

[PULL 10/34] accel/tcg: Implement translator_st

Copy data out of a completed translation. This will be used for both plugins and disassembly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 23 accel/tcg/translator.c| 55 +++ 2 file

Re: [PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Sorry that I only put the patch version on the cover letter. I will resend the patches. Sincerely, Fea Fea.Wang 於 2024年5月15日 週三 下午3:48寫道： > Based on the change log for the RISC-V privilege 1.13 spec, add the > support for ss1p13. > > Ref: > https://github.com/riscv/riscv-isa-manual/blob/a7d93c9

[RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9 insertions(+

[RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be cont

[PULL 20/34] accel/tcg: Introduce translator_fake_ld

Replace translator_fake_ldb, which required multiple calls, with translator_fake_ld, which can take all data at once. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h| 8 accel/tcg/translator.c | 5 ++--- target/s390x/tcg/tran

[PULL 15/34] plugins: Merge alloc_tcg_plugin_context into plugin_gen_tb_start

We don't need to allocate plugin context at startup, we can wait until we actually use it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 36 tcg/tcg.c | 11 --- 2 files changed, 20 inse

[RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err

Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[PULL 12/34] plugins: Read mem_only directly from TB cflags

Do not pass around a boolean between multiple structures, just read it from the TranslationBlock in the TCGContext. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 7 +++ include/qemu/plugin.h | 3 --- accel/tcg/plugin-gen.c| 4

[PULL 23/34] target/hexagon: Use translator_ldl in pkt_crosses_page

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 61302d4f46..4b1bee3c6d 100644 --- a/target/hexagon/translate.c +

[RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Based on the change log for the RISC-V privilege 1.13 spec, add the support for ss1p13. Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 Lists what to do without clarification or document format. * Redefined misa.MXL to be read-only, making MXLEN a

[PULL 19/34] disas: Use translator_st to get disassembly data

Read from already translated pages, or saved mmio data. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/disas/disas.h | 5 +++-- include/exec/translator.h | 4 ++-- include/qemu/typedefs.h | 1 + accel/tcg/translator.c| 2 +- disas/disas-common.c

[RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec

From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tc

[PULL 17/34] accel/tcg: Return bool from TranslatorOps.disas_log

We have eliminated most uses of this hook. Reduce further by allowing the hook to handle only the special cases, returning false for normal processing. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h| 2 +- accel/tcg/translator.c |

[PATCH 01/16] vfio/display: Fix error path in call site of ramfb_setup()

vfio_display_dmabuf_init() and vfio_display_region_init() calls ramfb_setup() without checking its return value. So we may run into a situation that vfio_display_probe() succeed but errp is set. This is risky and may lead to assert failure in error_setv(). Cc: Gerd Hoffmann Fixes: b290659fc3d ("

[PATCH 02/16] vfio/display: Make vfio_display_*() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.h | 2 +- hw/vfio/display.c | 20 ++-- hw/vfio/pci.c | 3 +-- 3 files changed, 12 insertions(+),

[PATCH 12/16] vfio/pci: Make vfio_populate_vga() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.h | 2 +- hw/vfio/igd.c | 2 +- hw/vfio/pci.c | 11 +-- 3 files changed, 7 insertions(+), 8 deletions(-) diff -

[PATCH 07/16] vfio/ccw: Make vfio_ccw_get_region() return a bool

Since vfio_populate_device() takes an 'Error **' argument, best practices suggest to return a bool. See the qapi/error.h Rules section. Signed-off-by: Zhenzhong Duan --- hw/vfio/ccw.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.

[PATCH 16/16] vfio/pci-quirks: Make vfio_add_*_cap() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Include below functions: vfio_add_virt_caps() vfio_add_nv_gpudirect_cap() vfio_add_vmd_shadow_cap() Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.h| 2 +- hw/

[PATCH 04/16] vfio/helpers: Make vfio_set_irq_signaling() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 4 ++-- hw/vfio/ap.c | 8 +++ hw/vfio/ccw.c | 8 +++ hw/vf

[PATCH 03/16] vfio/helpers: Use g_autofree in hw/vfio/helpers.c

Changed functions include vfio_set_irq_signaling() and vfio_region_setup(). Signed-off-by: Zhenzhong Duan --- hw/vfio/helpers.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/vfio/helpers.c b/hw/vfio/helpers.c index 47b4096c05..0bb7b40a6a 100644 --- a/hw/vfio/helpe

[PATCH 15/16] vfio/pci-quirks: Make vfio_pci_igd_opregion_init() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.h| 6 +++--- hw/vfio/igd.c| 3 +-- hw/vfio/pci-quirks.c | 8 hw/vfio/pci.c| 3 +-- 4 file

[PATCH 13/16] vfio/pci: Make capability related functions return bool

The functions operating on capability don't have a consistent return style. Below functions are in bool-valued functions style: vfio_msi_setup() vfio_msix_setup() vfio_add_std_cap() vfio_add_capabilities() Below two are integer-valued functions: vfio_add_vendor_specific_cap() vfio_setup_pcie_cap(

[PATCH 11/16] vfio/pci: Make vfio_intx_enable() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c i

[PATCH 05/16] vfio/helpers: Make vfio_device_get_name() return bool

This is to follow the coding standand in qapi/error.h to return bool for bool-valued functions. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 2 +- hw/vfio/ap.c | 2 +- hw/vfio/ccw.c | 2 +- hw/vfio/helpers.c

[PATCH 14/16] vfio/pci: Use g_autofree for vfio_region_info pointer

Pointer opregion is freed after vfio_pci_igd_opregion_init(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index ecfbb9619f..be87478716 100644 ---

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