BookE does not have real mode so split off and handle it first in
get_physical_address_wtlb() before checking for real mode for other
MMU models.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 14 +++---
1 file changed, 7 insertions(+), 7 deleti
mmubooke206_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 32 ++--
1 file changed, 10 insertions(+
In mmu6xx_get_physical_address() we have a large if block with a two
line else branch that effectively returns. Invert the condition and
move the else there to allow deindenting the large if block to make
the flow easier to follow.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
value of prot2 directly to the destination, no need to have a separate
local variable for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 30 +-
1 file
Drop MPC8xx cases from get_physical_address_wtlb() and ppc_jumbo_xlate().
The default case would still catch this and abort the same way and
there is still a warning about it in ppc_tlb_invalidate_all() which is
called in ppc_cpu_reset_hold() so likely we never get here but to make
sure add a case
The real mode handling is identical in the remaining switch cases.
Split off these common real mode cases into a separate conditional to
leave only the else branches in the switch that are different.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 34 +++
The "2" in booke206_update_mas_tlb_miss() call corresponds to
MMU_INST_FETCH which is the value of access_type in this branch;
mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
code access so using MMU_DATA_LOAD here seems wrong so replace it with
access_type here as well that y
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 148 ++--
1 file changed, 98 insertions(+), 50 deletions(-)
diff --
The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
pp_check() in mmu_common.c, merge these to remove duplicated code.
Define the common function in internal.h as static lnline otherwise
exporting the function from mmu-hash32.c would stop the compiler
inlining it which results in sligh
The value is only used once so no need to introduce a local variable
for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu-radix64.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index
This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
hw/ppc/pegasos2.c| 2 +-
target/ppc/cpu.h | 5 -
target/ppc/c
Merge the code fetch and data access cases in a common switch.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 52 -
1 file changed, 20 insertions(+), 32 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/
Fix several qemu_log_mask() calls that are misindented.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 42 -
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_co
Move setting error_code that appears in every case out in front and
hoist the common fall through case for BOOKE206 as well which allows
removing the nested switches.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 41
Repurpose get_segment_6xx_tlb() to do the whole address translation
for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
renaming it to match other similar functions. These are only called
once together so no need to keep these separate functions and
combining them simplifies the ca
Now that some functions are external again the warnings don't appear
any more so the work around added earlier can be removed again.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
in
Move the debug logging within ppc6xx_tlb_check() from after its only
call to simplify the caller.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 54 ++---
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git
Several 4xx CPUs and e200 share the same TLB settings enclosed in an
ifdef. Split it off in a common function to reduce code duplication
and the number of ifdefs.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 46 --
As BookE never returns -4 we can drop BookE from the direct store case
in ppc_jumbo_xlate().
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_
mmu40x_get_physical_address() only uses the raddr and prot fields from
mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 37 +++--
1 file changed, 15 insertions(+
mmubooke_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 30 ++
1 file changed, 10 insertions(+), 20
Remove mmu_ctx_t definition from internal.h as this type is only used
within mmu_common.c.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/internal.h | 12
target/ppc/mmu_common.c | 11 +++
2 files changed, 11 insertions(+), 12 deletions(-)
diff
On Thu, 9 May 2024, Cord Amfmgm wrote:
On Thu, May 9, 2024 at 12:48 PM Peter Maydell
wrote:
On Wed, 8 May 2024 at 16:29, Cord Amfmgm wrote:
On Wed, May 8, 2024 at 3:45 AM Thomas Huth wrote:
Your Signed-off-by line does not match the From: line ... could you
please
fix this? (see
https
>-Original Message-
>From: Shivaprasad G Bhat
>Subject: [PATCH] vfio: container: Fix missing allocation of
>VFIOSpaprContainer
>
>The commit 6ad359ec29 "(vfio/spapr: Move prereg_listener into
>spapr container)" began to use the newly introduced VFIOSpaprContainer
>structure.
>
>After sev
On 5/10/24 02:22, Stefan Hajnoczi wrote:
On Wed, May 08, 2024 at 05:36:21PM +0800, Changqi Lu wrote:
[SNIP]
+
+/**
+ * Persist Through Power Loss(PTPL) is considered as required in QEMU
+ * block layer, the block driver need always enable PTPL.
+ */
What is the reasoning
On Thu, May 09, 2024 at 05:39:50PM +0200, Paolo Bonzini wrote:
> Date: Thu, 9 May 2024 17:39:50 +0200
> From: Paolo Bonzini
> Subject: [PATCH] target/i386: fix feature dependency for WAITPKG
> X-Mailer: git-send-email 2.45.0
>
> The VMX feature bit depends on general availability of WAITPKG,
> n
On Thu, May 09, 2024 at 05:39:52PM +0200, Paolo Bonzini wrote:
> Date: Thu, 9 May 2024 17:39:52 +0200
> From: Paolo Bonzini
> Subject: [PATCH] target/i386: add feature dependency for XSAVE
> X-Mailer: git-send-email 2.45.0
>
> The XSAVEOPT, XSAVEC, XGETBV1, XSAVES features make no sense if you
>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb1a2e7d6d..13cd34adbd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1535,7 +1535,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
On Thu, May 9, 2024 at 3:10 PM Eugenio Perez Martin wrote:
>
> On Thu, May 9, 2024 at 8:27 AM Jason Wang wrote:
> >
> > On Thu, May 9, 2024 at 1:16 AM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, May 8, 2024 at 4:29 AM Jason Wang wrote:
> > > >
> > > > On Tue, May 7, 2024 at 6:57 PM Eug
On 09/05/2024 10.47, Bibo Mao wrote:
Add boot-serial-test and filter test cases support on LoongArch system.
Signed-off-by: Bibo Mao
---
v1 ... v2:
1. Refresh the changelog, adding filter test case support also.
2. Adjust order of loongarch qtest in alphabetical order.
---
Reviewed-by: T
On 09/05/2024 19.00, Paolo Bonzini wrote:
This function has no dependency on the virtio-ccw machine type, though it
assumes that the CPU address corresponds to the core_id and the index.
If there is any need of something different or more fancy (unlikely)
S390 can include a MachineClass subclass
On 09/05/2024 19.00, Paolo Bonzini wrote:
Instead of mucking with css_migration_enabled(), add a property specific to
the FLIC device, similar to what is done for TYPE_S390_STATTRIB.
Signed-off-by: Paolo Bonzini
---
include/hw/s390x/s390_flic.h | 1 +
hw/intc/s390_flic.c | 6 +-
On 09/05/2024 19.00, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest.yml | 4 ++--
target/s390x/Kconfig | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index 13afd0df1f0..f850290
On 09/05/2024 19.00, Paolo Bonzini wrote:
Do the bare minimum to ensure that at least a vanilla
--without-default-devices build works for all targets except i386,
x86_64 and ppc64. In particular this fixes s390x-softmmu; i386 and
x86_64 have about a dozen failing tests that do not pass -M and th
On 5/9/24 01:35, Fabiano Rosas wrote:
The following changes since commit 4e66a08546a2588a4667766a1edab9caccf24ce3:
Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging
(2024-05-07 09:26:30 -0700)
are available in the Git repository at:
https://gitlab.com/farosas/qemu
g/qemu.git tags/pull-loongarch-20240509
for you to fetch changes up to 5872966db7abaa7f8753541b7a9f242df9752b50:
target/loongarch: Put cpucfg operation before CSR register (2024-05-09
15:19:22 +0800)
pull-loongarch-20240509
On 09/05/2024 19.00, Paolo Bonzini wrote:
The CSS subsystem uses global variables, just face the truth and use
a variable also for whether the CSS vmstate is in use; remove the
indirection of fetching it from the machine type, which makes the
TCG code depend unnecessarily on the virtio-ccw machin
On 09/05/2024 19.00, Paolo Bonzini wrote:
ARM/aarch64 are easy to fix because they already have to pass a machine
type by hand. Just guard the tests with a check that the machine actually
exists.
Signed-off-by: Paolo Bonzini
---
tests/qtest/arm-cpu-features.c | 4
tests/qtest/migration
On 08/05/2024 09.44, Stefano Garzarella wrote:
`memory-backend-memfd` is available only on Linux while the new
`memory-backend-shm` can be used on any POSIX-compliant operating
system. Let's use it so we can run the test in multiple environments.
Signed-off-by: Stefano Garzarella
---
tests/qt
On 08/05/2024 09.44, Stefano Garzarella wrote:
`memory-backend-shm` can be used with vhost-user devices, so let's
add a new test case for it.
Signed-off-by: Stefano Garzarella
---
tests/qtest/vhost-user-test.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/tests
From: Cédric Le Goater
Initialize directly SCLPDevice from the machine init handler and
remove s390_sclp_init(). We will use the SCLPDevice pointer later to
create the consoles.
Signed-off-by: Cédric Le Goater
Message-ID: <20240502131533.377719-2-...@redhat.com>
Reviewed-by: Thomas Huth
Signed
From: Cédric Le Goater
sclp_get_event_facility_bus() scans the whole machine to find a
TYPE_SCLP_EVENTS_BUS object. The SCLPDevice instance is now available
under the machine state, use it to simplify the lookup and adjust the
creation of the consoles.
Signed-off-by: Cédric Le Goater
Message-ID
From: Collin Walling
Retain a list of deprecated features disjoint from any particular
CPU model. A query-cpu-model-expansion reply will now provide a list of
properties (i.e. features) that are flagged as deprecated. Example:
{
"return": {
"model": {
"name": "z14.2-b
The old "-runas" option has the disadvantage that it is not visible
in the QAPI schema, so it is not available via the normal introspection
mechanisms. We've recently introduced the "-run-with" option for exactly
this purpose, which is meant to handle the options that affect the
runtime behavior. T
The following changes since commit 36fa7c686e9eac490002ffc439c4affaa352c17c:
gitlab: Update msys2-64bit runner tags (2024-05-09 05:46:21 +0200)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2024-05-10
for you to fetch changes up to 0d497106a71a3
From: Cédric Le Goater
get_sclp_device() scans the whole machine to find a TYPE_SCLP object.
Now that the SCLPDevice instance is available under the machine state,
use it to simplify the lookup. While at it, remove the inline to let
the compiler decide on how to optimize.
Signed-off-by: Cédric L
The sclpconsole currently does not have a proper parent in the QOM
tree, so it shows up under /machine/unattached - which is somewhat
ugly. We should rather attach it to /machine/sclp/s390-sclp-event-facility
where the other devices of type TYPE_SCLP_EVENT already reside.
Message-ID: <202404301908
From: Collin Walling
Add the CONSTRAINT_TRANSACTIONAL_EXE (cte) and TRANSACTIONAL_EXE (te)
to the list of deprecated features.
Signed-off-by: Collin Walling
Reviewed-by: David Hildenbrand
Message-ID: <20240429191059.11806-3-wall...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
target/s390x/c
From: Bibo Mao
Add boot-serial-test and filter test cases support on LoongArch system.
Signed-off-by: Bibo Mao
Message-ID: <20240509084745.2514607-1-maob...@loongson.cn>
Signed-off-by: Thomas Huth
---
tests/qtest/boot-serial-test.c | 10 ++
tests/qtest/meson.build| 3 +++
2 f
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