Re: CXL numa error on arm64 qemu virt machine

On Wed, 8 May 2024 16:00:51 +0800 Yuquan Wang wrote: > Hello, Jonathan > > Recently I run some cxl tests on qemu virt(branch:cxl-2024-04-22-draft) but > met some > problems. > > Problems: > 1) the virt machine could not set the right numa topology from user input; > > My Qemu numa set: > -ob

Re: [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together

On Tue May 7, 2024 at 10:31 PM AEST, BALATON Zoltan wrote: > On Tue, 7 May 2024, Nicholas Piggin wrote: > > What do you think about adding mmu-book3e.c instead? > > I have considered that but found that some functions have to be in the > same file and declared static for the compiler to inline the

Re: [PATCH v2] ppc: Deprecate 'ref405ep' machine and 405 CPUs

On Tue May 7, 2024 at 10:33 PM AEST, Cédric Le Goater wrote: > The 'ref405ep' machine and PPC 405 CPU have no known users, firmware > images are not available, OpenWRT dropped support in 2019, U-Boot in > 2017, Linux also is dropping support in 2024. It is time to let go of > this ancient hardware

[PATCH v3 1/4] hw/nvme: add Identify Endurance Group List

From: Minwoo Im Commit 73064edfb864 ("hw/nvme: flexible data placement emulation") intorudced NVMe FDP feature to nvme-subsys and nvme-ctrl with a single endurance group #1 supported. This means that controller should return proper identify data to host with Identify Endurance Group List (CNS 19

[PATCH v3 0/4] hw/nvme: FDP and SR-IOV enhancements

Hello, This patchset has rebased on the latest master and replaced 3rd patch to one which allocates a dynamic array for secondary controller list based on the maximum number of VFs (sriov_max_vfs) rather than a static size of static array as Klaus suggested. Rest of the patchset are the same with

[PATCH v3 3/4] hw/nvme: Allocate sec-ctrl-list as a dynamic array

From: Minwoo Im To prevent further bumping up the number of maximum VF te support, this patch allocates a dynamic array (NvmeCtrl *)->sec_ctrl_list based on number of VF supported by sriov_max_vfs property. Signed-off-by: Minwoo Im --- hw/nvme/ctrl.c | 8 +--- hw/nvme/nvme.h | 5 ++---

[PATCH v3 2/4] hw/nvme: separate identify data for sec. ctrl list

From: Minwoo Im Secondary controller list for virtualization has been managed by Identify Secondary Controller List data structure with NvmeSecCtrlList where up to 127 secondary controller entries can be managed. The problem hasn't arisen so far because NVME_MAX_VFS has been 127. This patch sep

[PATCH v3 4/4] hw/nvme: Expand VI/VQ resource to uint32

From: Minwoo Im VI and VQ resources cover queue resources in each VFs in SR-IOV. Current maximum I/O queue pair size is 0x, we can expand them to cover the full number of I/O queue pairs. This patch also fixed Identify Secondary Controller List overflow due to expand of number of secondary c

Re: [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env

On Wed May 8, 2024 at 2:02 AM AEST, BALATON Zoltan wrote: > On Tue, 7 May 2024, Nicholas Piggin wrote: > > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > >> This flag for split instruction/data TLBs is only set for 6xx soft TLB > >> MMU model and not used otherwise so no need to have a

Re: Hermetic virtio-vsock in QEMU

On 5/8/24 11:38, Stefano Garzarella wrote: On Wed, May 08, 2024 at 01:13:09PM GMT, Marc-André Lureau wrote: Hi On Wed, May 8, 2024 at 11:50 AM Stefano Garzarella wrote: Hi Roman, On Tue, May 07, 2024 at 11:20:50PM GMT, Roman Kiryanov wrote: >Hi Stefano, > >On Tue, May 7, 2024 at 1:10 AM St

Re: [PATCH v3 09/33] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address()

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Repurpose get_segment_6xx_tlb() to do the whole address translation > for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and > renaming it to match other similar functions. These are only called > once together so no need to

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

On 5/7/24 12:44, Peter Maydell wrote: On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza wrote: Hi, In this RFC I want to check with Gerd and others if it's ok to add a PCI id for the RISC-V IOMMU device. It's currently under review in [1]. The idea is to fold this patch into the RISC-V

Re: [PATCH v3 10/33] target/ppc/mmu_common.c: Move else branch to avoid large if block

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > In mmu6xx_get_physical_address() we have a large if block with a two > line else branch that effectively returns. Invert the condition and > move the else there to allow deindenting the large if block to make > the flow easier to follow.

Re: [PATCH v2 2/4] mirror: allow specifying working bitmap

Am 07.05.24 um 14:15 schrieb Fiona Ebner: > Am 02.04.24 um 22:14 schrieb Vladimir Sementsov-Ogievskiy: >> On 07.03.24 16:47, Fiona Ebner wrote: >>> +# @bitmap: The name of a bitmap to use as a working bitmap for >>> +# sync=full mode.  This argument must be not be present for other >>> +# s

Re: [PATCH v3 11/33] target/ppc/mmu_common.c: Move some debug logging

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Move the debug logging within ppc6xx_tlb_check() from after its only > call to simplify the caller. > I *think* the logic looks right. > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 55 +++---

Re: [PATCH v3 12/33] target/ppc/mmu_common.c: Eliminate ret from mmu6xx_get_physical_address()

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Return directly, which is simpler than dragging a return value through > multpile if and else blocks. Reviewed-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 84 +++

Re: [PATCH 2/9] migration: Fix file migration with fdset

On Wed, May 08, 2024 at 09:02:16AM +0100, Daniel P. Berrangé wrote: > On Fri, May 03, 2024 at 12:23:51PM -0400, Peter Xu wrote: > > On Fri, Apr 26, 2024 at 11:20:35AM -0300, Fabiano Rosas wrote: > > > When the migration using the "file:" URI was implemented, I don't > > > think any of us noticed th

Re: Hermetic virtio-vsock in QEMU

On Wed, May 08, 2024 at 02:37:52PM +0200, Paolo Bonzini wrote: > On 5/8/24 11:38, Stefano Garzarella wrote: > > On Wed, May 08, 2024 at 01:13:09PM GMT, Marc-André Lureau wrote: > > > Hi > > > > > > On Wed, May 8, 2024 at 11:50 AM Stefano Garzarella > > > wrote: > > > > > > > > Hi Roman, > > > >

Re: [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()

On Wed May 8, 2024 at 9:40 AM AEST, BALATON Zoltan wrote: > On Tue, 7 May 2024, Nicholas Piggin wrote: > > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote: > >> This function is no longer called for BookE MMU model so remove parts > >> related to it. This has uncovered a few may be used un

Re: [PATCH] hw/virtio: Fix obtain the buffer id from the last descriptor

On Mon, Apr 22, 2024 at 3:41 AM Wafer wrote: > > The virtio-1.3 specification > writes: > 2.8.6 Next Flag: Descriptor Chaining > Buffer ID is included in the last descriptor in the list. > > If the feature (_F_INDIRECT_DESC) h

Re: [PATCH v3 21/33] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > This function is not used from any other files so make it static and > fix the maybe used uninitialised warnings this has uncovered. Also > remove mmu_ctx_t definition from internal.h as this type is only used > within this file. If you

Re: [PATCH v3 23/33] target/ppc/mmu_common.c: Remove BookE from direct store handling

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > As BookE never returns -4 we can drop BookE from the direct store case > in ppc_jumbo_xlate(). > > Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin > --- > target/ppc/mmu_common.c | 7 +-- > 1 file changed, 1 insertion(

Re: [PATCH v3 22/33] target/ppc: Remove pp_check() and reuse ppc_hash32_pp_prot()

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as > pp_check() in mmu_common.c, merge these to remove duplicated code. > Define the common function in internal.h as static lnline otherwise > exporting the function from mmu-

Re: [PATCH v3 24/33] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to > reduce ppc_jumbo_xlate() further. > Reviewed-by: Nicholas Piggin > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 128

Re: Hermetic virtio-vsock in QEMU

On Wed, May 8, 2024 at 2:51 PM Daniel P. Berrangé wrote: > Designwise, a native VSOCK backend in QEMU really should implement the > same approach defined by firecracker, so that we have interoperability > with systemd, firecracker and cloud-hypervisor. See > > https://gitlab.com/qemu-project/qem

Re: [PATCH v2] hw/loongarch/virt: Fix memory leak

On Wed, 8 May 2024 at 03:30, Song Gao wrote: > > The char pointer 'ramName' point to a block of memory, but never free it. > Use a small fixed-size buffer for 'ramName'. > > Resolves: Coverity CID 1544773 > > Fixes: 0cf1478d6 ("hw/loongarch: Add numa support") > Signed-off-by: Song Gao > --- > v2

Re: [PATCH] hw/loongarch/virt: Fix memory leak

On Tue, 7 May 2024 at 10:52, Michael Tokarev wrote: > > 07.05.2024 05:22, Song Gao wrote: > > > for (i = 1; i < nb_numa_nodes; i++) { > > MemoryRegion *nodemem = g_new(MemoryRegion, 1); > > -ramName = g_strdup_printf("loongarch.node%d.ram", i); > > +g_autofree char

[PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS

Implement IOCSR address space get functions for MIPS/Loongson CPUs. For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR, which matches expected behavior on hardware. Signed-off-by: Jiaxun Yang --- I und

[PATCH 2/5] hw/intc/loongarch_ipi: Rename as loongson_ipi

This device will be shared among LoongArch and MIPS based Loongson machine, rename it as loongson_ipi to reflect this nature. Signed-off-by: Jiaxun Yang --- MAINTAINERS| 4 + hw/intc/Kconfig| 2 +- hw/intc/loongson_i

[PATCH 1/5] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check

Since cpuid will be checked by ipi_getcpu anyway, there is no point to enforce MAX_CPU here. This also saved us from including loongarch board header. Signed-off-by: Jiaxun Yang --- hw/intc/loongarch_ipi.c | 19 ++- hw/intc/trace-events| 2 -- 2 files changed, 2 insertions(

[PATCH 5/5] hw/mips/loongson3_virt: Wire up loongson_ipi device

Wire up loongson_ipi device for loongson3_virt machine, so we can have SMP support for TCG backend as well. Signed-off-by: Jiaxun Yang --- hw/mips/Kconfig | 1 + hw/mips/loongson3_bootp.c | 2 -- hw/mips/loongson3_bootp.h | 3 +++ hw/mips/loongson3_virt.c | 39 +

[PATCH 4/5] hw/intc/loongson_ipi: Provide per core MMIO address spaces

The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Signed-off-by: Jiaxun Yang --- hw/intc/

[PATCH 0/5] hw/mips/loongson3_virt: Implement IPI support

/hw/loongarch/virt.h| 2 +- 14 files changed, 475 insertions(+), 38 deletions(-) --- base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 change-id: 20240508-loongson3-ipi-65e99b47c400 Best regards, -- Jiaxun Yang

Re: [PATCH] scripts/simpletrace: Mark output with unstable timestamp as WARN

On 8/5/24 06:32, Zhao Liu wrote: In some trace log, there're unstable timestamp breaking temporal ordering of trace records. For example: kvm_run_exit -0.015 pid=3289596 cpu_index=0x0 reason=0x6 kvm_vm_ioctl -0.020 pid=3289596 type=0xc008ae67 arg=0x7ffeefb5aa60 kvm_vm_ioctl -0.021 pid=32

[PATCH 5/9] hw/scsi: add persistent reservation in/out api for scsi device

Add persistent reservation in/out operations in the SCSI device layer. By introducing the persistent reservation in/out api, this enables the SCSI device to perform reservation-related tasks, including querying keys, querying reservation status, registering reservation keys, initiating and releasin

Re: [PATCH v3 25/33] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb()

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > This function is no longer called for BookE MMU model so remove parts > related to it. This has uncovered a few may be used uninitialised > warnings that are also fixed. > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c

[PATCH 1/9] block: add persistent reservation in/out api

Add persistent reservation in/out operations at the block level. The following operations are included: - read_keys:retrieves the list of registered keys. - read_reservation: retrieves the current reservation status. - register: registers a new reservation key. - reserve:

[PATCH 4/9] scsi/util: add helper functions for persistent reservation types conversion

This commit introduces two helper functions that facilitate the conversion between the persistent reservation types used in the SCSI protocol and those used in the block layer. Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- include/scsi/utils.h | 5 + scsi/utils.c | 40 +++

[PATCH 9/9] block/iscsi: add persistent reservation in/out driver

Add persistent reservation in/out operations for iscsi driver. The following methods are implemented: bdrv_co_pr_read_keys, bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve, bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt. Signed-off-by: Changqi Lu Signed-off-by: z

[PATCH 8/9] hw/nvme: add reservation protocal command

Add reservation acquire, reservation register, reservation release and reservation report commands in the nvme device layer. By introducing these commands, this enables the nvme device to perform reservation-related tasks, including querying keys, querying reservation status, registering reservati

[PATCH 0/9] Support persistent reservation operations

Hi, I am going to introduce persistent reservation for QEMU block. There are three parts in this series: Firstly, at the block layer, the commit abstracts seven APIs related to the persistent reservation command. These APIs including reading keys, reading reservations, registering, reserving, rel

[PATCH 2/9] block/raw: add persistent reservation in/out driver

Add persistent reservation in/out operations for raw driver. The following methods are implemented: bdrv_co_pr_read_keys, bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve, bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt. Signed-off-by: Changqi Lu Signed-off-by: zhe

[PATCH 7/9] hw/nvme: add helper functions for converting reservation types

This commit introduces two helper functions that facilitate the conversion between the reservation types used in the NVME protocol and those used in the block layer. Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- hw/nvme/nvme.h | 40 1 file chan

[PATCH 6/9] block/nvme: add reservation command protocol constants

Add constants for the NVMe persistent command protocol. The constants include the reservation command opcode and reservation type values defined in section 7 of the NVMe 2.0 specification. Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- include/block/nvme.h | 30

[PATCH 3/9] scsi/constant: add persistent reservation in/out protocol constants

Add constants for the persistent reservation in/out protocol in the scsi/constant module. The constants include the persistent reservation command, type, and scope values defined in sections 6.13 and 6.14 of the SCSI Primary Commands-4 (SPC-4) specification. Signed-off-by: Changqi Lu Signed-off-b

Re: [PATCH v3 26/33] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Move setting error_code that appears in every case out in front and > hoist the common fall through case for BOOKE206 as well which allows > removing the nested switches. > Reviewed-by: Nicholas Piggin > Signed-off-by: BALATON Zoltan

Re: [PATCH v2] qemu-options: Deprecate "-runas" and introduce "-run-with user=..." instead

On 5/6/24 13:20, Thomas Huth wrote: > The old "-runas" option has the disadvantage that it is not visible > in the QAPI schema, so it is not available via the normal introspection > mechanisms. We've recently introduced the "-run-with" option for exactly > this purpose, which is meant to handle the

Re: [PATCH v3 27/33] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 2

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Merge the code fetch and data access cases in a common switch. > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu_common.c | 50 + > 1 file changed, 20 insertions(+), 30 deletions(-) > > dif

Re: [PATCH v3 28/33] target/ppc/mmu_common.c: Move BookE MMU functions together

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Signed-off-by: BALATON Zoltan Okay for now but we should split into a new file soon. Acked-by: Nicholas Piggin > --- > target/ppc/mmu_common.c | 226 > 1 file changed, 113 insertions(+), 113

Re: [PATCH v3 32/33] target/ppc/mmu-radix64.c: Drop a local variable

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > The value is only used once so no need to introduce a local variable > for it. Reviewed-by: Nicholas Piggin > > Signed-off-by: BALATON Zoltan > --- > target/ppc/mmu-radix64.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(

Re: [PATCH v3 31/33] target/ppc/mmu-hash32.c: Drop a local variable

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > In ppc_hash32_xlate() the value of need_prop is checked in two places > but precalculating it does not help because when we reach the first > check we always return and not reach the second place so the value > will only be used once. We

Re: [PATCH v3 33/33] target/ppc: Add a macro to check for page protection bit

On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: > Checking if a page protection bit is set for a given access type is a > common operation. Add a macro to avoid repeating the same check at > multiple places and also avoid a function call. As this relies on > access type and page protecti

Re: Hermetic virtio-vsock in QEMU

On Wed, May 08, 2024 at 03:00:30PM +0200, Paolo Bonzini wrote: > On Wed, May 8, 2024 at 2:51 PM Daniel P. Berrangé wrote: > > Designwise, a native VSOCK backend in QEMU really should implement the > > same approach defined by firecracker, so that we have interoperability > > with systemd, firecrac

Re: [PATCH v3 01/33] target/ppc: Fix gen_sc to use correct nip

On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote: > Most exceptions are raised with nip pointing to the faulting > instruction but the sc instruction generating a syscall exception > leaves nip pointing to next instruction. Fix gen_sc to not use > gen_exception_err() which sets nip back bu

Re: [PATCH] hw/nvme: fix mo field in io mgnt send

On 5/7/24 10:05, Vincent Fu wrote: On 5/6/24 04:06, Klaus Jensen wrote: The Management Operation field of I/O Management Send is only 8 bits, not 16. Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation") Signed-off-by: Klaus Jensen ---   hw/nvme/ctrl.c | 2 +-   1 file changed, 1 i

Re: [PATCH] scripts/simpletrace: Mark output with unstable timestamp as WARN

Hi Philippe, On Wed, May 08, 2024 at 03:09:39PM +0200, Philippe Mathieu-Daudé wrote: > Date: Wed, 8 May 2024 15:09:39 +0200 > From: Philippe Mathieu-Daudé > Subject: Re: [PATCH] scripts/simpletrace: Mark output with unstable > timestamp as WARN > > On 8/5/24 06:32, Zhao Liu wrote: > > In some t

Re: [PATCH v2] qemu-options: Deprecate "-runas" and introduce "-run-with user=..." instead

On 08/05/2024 15.20, Claudio Fontana wrote: On 5/6/24 13:20, Thomas Huth wrote: The old "-runas" option has the disadvantage that it is not visible in the QAPI schema, so it is not available via the normal introspection mechanisms. We've recently introduced the "-run-with" option for exactly thi

Re: [PATCH 3/4] hw/char: Add QOM property for STM32L4x5 USART clock frequency

Hi, On 7/5/24 11:54, Peter Maydell wrote: On Mon, 6 May 2024 at 10:34, Philippe Mathieu-Daudé wrote: Hi, On 5/5/24 16:05, Inès Varhol wrote: Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/char/stm32l4x5_usa

[PATCH] hw/clock: Expose 'freq-hz' QOM property

Expose the clock frequency via the QOM 'freq-hz' property, as it might be useful for QTests. HMP example: $ qemu-system-mips -S -monitor stdio -M mipssim (qemu) qom-get /machine/cpu-refclk freq-hz 1200 Inspired-by: Inès Varhol Signed-off-by: Philippe Mathieu-Daudé --- hw/core/clock.

Re: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

On 07/05/24, ltaylorsimp...@gmail.com wrote: > > > > -Original Message- > > From: 'Anton Johansson' > > Sent: Tuesday, May 7, 2024 4:47 AM > > To: ltaylorsimp...@gmail.com > > Cc: qemu-devel@nongnu.org; a...@rev.ng; bc...@quicinc.com > > Subject: Re: [PATCH 3/4] target/hexagon: idef-pars

Re: [PATCH] scripts/simpletrace: Mark output with unstable timestamp as WARN

On 8/5/24 15:55, Zhao Liu wrote: Hi Philippe, On Wed, May 08, 2024 at 03:09:39PM +0200, Philippe Mathieu-Daudé wrote: Date: Wed, 8 May 2024 15:09:39 +0200 From: Philippe Mathieu-Daudé Subject: Re: [PATCH] scripts/simpletrace: Mark output with unstable timestamp as WARN On 8/5/24 06:32, Zhao

Re: [PATCH v2 0/3] crypto: Allow building with GnuTLS but without Libtasn1

ping? On 2/5/24 11:56, Philippe Mathieu-Daudé wrote: Since v1: - split in 3 - remove "crypto-tls-x509-helpers.h" (danpb) - include pkix_asn1_tab.c.inc Philippe Mathieu-Daudé (3): crypto: Remove 'crypto-tls-x509-helpers.h' from crypto-tls-psk-helpers.c crypto: Restrict pkix_asn1_tab[]

[PATCH v2] hw/input/tsc2005: Fix -Wchar-subscripts warning in tsc2005_txrx()

Check the function index is in range and use an unsigned variable to avoid the following warning with GCC 13.2.0: [666/5358] Compiling C object libcommon.fa.p/hw_input_tsc2005.c.o hw/input/tsc2005.c: In function 'tsc2005_timer_tick': hw/input/tsc2005.c:416:26: warning: array subscript has ty

Re: [PATCH 1/2] util/iov: Do not assert offset is in iov

ping? On 28/4/24 13:11, Akihiko Odaki wrote: iov_from_buf(), iov_to_buf(), iov_memset(), and iov_copy() asserts that the given offset fits in the iov while tolerating the specified number of bytes to operate with to be greater than the size of iov. This is inconsistent so remove the assertions.

Re: [PATCH v2 0/6] This series changes the "isa-bios" MemoryRegion to be an alias rather than a

On 30/4/24 17:06, Bernhard Beschow wrote: Bernhard Beschow (6): hw/i386/x86: Eliminate two if statements in x86_bios_rom_init() hw/i386: Have x86_bios_rom_init() take X86MachineState rather than MachineState hw/i386/x86: Don't leak "isa-bios" memory regions Patches 1-3 queued.

Re: [PATCH v4 1/5] hw/loongarch: Rename LOONGARCH_MACHINE with LOONGARCH_VIRT_MACHINE

On 8/5/24 05:11, Bibo Mao wrote: On LoongArch system, there is only virt machine type now, name LOONGARCH_MACHINE is confused, rename it with LOONGARCH_VIRT_MACHINE. Machine name about Other real hw boards can be added in future. Signed-off-by: Bibo Mao --- hw/loongarch/acpi-build.c | 8 ++

Re: [PATCH v4 2/5] hw/loongarch: Rename LoongArchMachineState with LoongArchVirtMachineState

On 8/5/24 05:11, Bibo Mao wrote: Rename LoongArchMachineState with LoongArchVirtMachineState, and change variable name LoongArchMachineState *lams with LoongArchVirtMachineState *lvms. Rename function specific for virtmachine loongarch_xxx() with virt_xxx(). However some common functions keep un

Re: [PATCH v3 01/33] target/ppc: Fix gen_sc to use correct nip

On Wed, 8 May 2024, Nicholas Piggin wrote: On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote: Most exceptions are raised with nip pointing to the faulting instruction but the sc instruction generating a syscall exception leaves nip pointing to next instruction. Fix gen_sc to not use gen_

Re: [PATCH v2 10/33] accel/tcg: Implement translator_st

On 25/4/24 01:31, Richard Henderson wrote: Copy data out of a completed translation. This will be used for both plugins and disassembly. Signed-off-by: Richard Henderson --- include/exec/translator.h | 23 accel/tcg/translator.c| 55 +

Re: [PATCH v3 33/33] target/ppc: Add a macro to check for page protection bit

On Wed, 8 May 2024, Nicholas Piggin wrote: On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: Checking if a page protection bit is set for a given access type is a common operation. Add a macro to avoid repeating the same check at multiple places and also avoid a function call. As this r

Re: [PATCH v2 18/33] disas: Split disas.c

On 25/4/24 01:31, Richard Henderson wrote: The routines in disas-common.c are also used from disas-mon.c. Otherwise the rest of disassembly is only used from tcg. While we're at it, put host and target code into separate files. Signed-off-by: Richard Henderson --- disas/disas-internal.h | 4

Re: [PATCH v3 26/33] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() part 1

On Wed, 8 May 2024, Nicholas Piggin wrote: On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote: Move setting error_code that appears in every case out in front and hoist the common fall through case for BOOKE206 as well which allows removing the nested switches. Reviewed-by: Nicholas Pi

Re: [RFC 1/2] iova_tree: add an id member to DMAMap

On Wed, May 8, 2024 at 2:52 AM Si-Wei Liu wrote: > > > > On 5/1/2024 11:44 PM, Eugenio Perez Martin wrote: > > On Thu, May 2, 2024 at 1:16 AM Si-Wei Liu wrote: > >> > >> > >> On 4/30/2024 10:19 AM, Eugenio Perez Martin wrote: > >>> On Tue, Apr 30, 2024 at 7:55 AM Si-Wei Liu wrote: > >

Re: hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT

On Wed, May 8, 2024 at 4:53 AM Philippe Mathieu-Daudé wrote: > On 7/5/24 22:20, Cord Amfmgm wrote: > > > > > > On Wed, Apr 24, 2024 at 3:43 PM Cord Amfmgm > > wrote: > > > > On Thu, Apr 18, 2024 at 10:43 AM Michael Tokarev > > wrote: >

Re: [PATCH v2 19/33] disas: Use translator_st to get disassembly data

On 25/4/24 01:31, Richard Henderson wrote: Read from already translated pages, or saved mmio data. Signed-off-by: Richard Henderson --- include/disas/disas.h | 5 +++-- include/exec/translator.h | 4 ++-- include/qemu/typedefs.h | 1 + accel/tcg/translator.c| 2 +- disas/dis

Re: [PATCH] hw/mips/loongson3_virt: Emulate suspend function

On 8/5/24 11:31, Jiaxun Yang wrote: Suspend function is emulated as what hardware actually do. Doorbell register fields are updates to include suspend value, suspend vector is encoded in firmware blob and fw_cfg is updated to include S3 bits as what x86 did. Signed-off-by: Jiaxun Yang --- hw/

[PATCH] target/i386: remove PCOMMIT from TCG, deprecate property

The PCOMMIT instruction was never included in any physical processor. TCG implements it as a no-op instruction, but its utility is debatable to say the least. Drop it from the decoder since it is only available with "-cpu max", which does not guarantee migration compatibility across versions, and

Re: [PATCH v2 6/6] hw/i386/pc_sysfw: Alias rather than copy isa-bios region

On Tue, Apr 30, 2024 at 5:39 PM Philippe Mathieu-Daudé wrote: > I'm still not convinced we need a migration back compat for this... It's absolutely needed, memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size, &error_fatal); will register a RAM region

Re: [PATCH v3 2/2] cxl/core: add poison creation event handler

On Fri, 3 May 2024 18:42:31 +0800 Shiyang Ruan wrote: > 在 2024/4/24 1:57, Ira Weiny 写道: > > Shiyang Ruan wrote: > >> Currently driver only traces cxl events, poison creation (for both vmem > >> and pmem type) on cxl memdev is silent. OS needs to be notified then it > >> could handle poison pag

Re: [PATCH 3/5] hw/intc/loongson_ipi: Implement IOCSR address space for MIPS

On 8/5/24 15:06, Jiaxun Yang wrote: Implement IOCSR address space get functions for MIPS/Loongson CPUs. For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR, which matches expected behavior on hardware.

Re: [PATCH 1/5] hw/intc/loongarch_ipi: Remove pointless MAX_CPU check

On 8/5/24 15:06, Jiaxun Yang wrote: Since cpuid will be checked by ipi_getcpu anyway, there is no point to enforce MAX_CPU here. This also saved us from including loongarch board header. Signed-off-by: Jiaxun Yang --- hw/intc/loongarch_ipi.c | 19 ++- hw/intc/trace-events

Re: [PATCH 2/5] hw/intc/loongarch_ipi: Rename as loongson_ipi

On 8/5/24 15:06, Jiaxun Yang wrote: This device will be shared among LoongArch and MIPS based Loongson machine, rename it as loongson_ipi to reflect this nature. Signed-off-by: Jiaxun Yang --- MAINTAINERS| 4 + hw/intc/Kconfig

Re: [PATCH v2 29/33] target/riscv: Use translator_ld* for everything

On 25/4/24 01:31, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/riscv/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 22/33] target/s390x: Disassemble EXECUTEd instructions

On 25/4/24 01:31, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2 21/33] target/s390x: Fix translator_fake_ld length

On 25/4/24 01:31, Richard Henderson wrote: The ilen value extracted from ex_value is the length of the EXECUTE instruction itself, and so is the increment to the pc. However, the length of the synthetic insn is located in the opcode like all other instructions. Signed-off-by: Richard Henderson

Re: [PATCH] hw/mips/loongson3_virt: Emulate suspend function

On 8/5/24 17:35, Philippe Mathieu-Daudé wrote: On 8/5/24 11:31, Jiaxun Yang wrote: Suspend function is emulated as what hardware actually do. Doorbell register fields are updates to include suspend value, suspend vector is encoded in firmware blob and fw_cfg is updated to include S3 bits as what

Re: [RFC 0/2] Identify aliased maps in vdpa SVQ iova_tree

On Wed, May 8, 2024 at 4:29 AM Jason Wang wrote: > > On Tue, May 7, 2024 at 6:57 PM Eugenio Perez Martin > wrote: > > > > On Tue, May 7, 2024 at 9:29 AM Jason Wang wrote: > > > > > > On Fri, Apr 12, 2024 at 3:56 PM Eugenio Perez Martin > > > wrote: > > > > > > > > On Fri, Apr 12, 2024 at 8:47 

Re: [PATCH] hw/mips/loongson3_virt: Emulate suspend function

在2024年5月8日五月 下午5:48，Philippe Mathieu-Daudé写道： > On 8/5/24 17:35, Philippe Mathieu-Daudé wrote: >> On 8/5/24 11:31, Jiaxun Yang wrote: >>> Suspend function is emulated as what hardware actually do. >>> Doorbell register fields are updates to include suspend value, >>> suspend vector is encoded in

[PULL 02/26] target/ppc: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize t

[PULL 01/26] block/qcow2-bitmap: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize t

[PULL 00/26] Misc HW patches for 2024-05-08

The following changes since commit 4e66a08546a2588a4667766a1edab9caccf24ce3: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-05-07 09:26:30 -0700) are available in the Git repository at: https://github.com/philmd/qemu.git tags/hw-misc-20240508

[PULL 05/26] hw/remote/vfio-user: Fix config space access byte order

From: Mattias Nissler PCI config space is little-endian, so on a big-endian host we need to perform byte swaps for values as they are passed to and received from the generic PCI config space access machinery. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi Reviewed-by: Jaganna

[PULL 03/26] hw/hppa/machine: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize t

[PULL 07/26] system/physmem: Propagate AddressSpace to MapClient helpers

From: Mattias Nissler Propagate AddressSpace handler to following helpers: - register_map_client() - unregister_map_client() - notify_map_clients[_locked]() Rename them using 'address_space_' prefix instead of 'cpu_'. The AddressSpace argument will be used in the next commit. Reviewed-by: Pete

[PULL 16/26] hw/gpio: Handle clock migration in STM32L4x5 gpios

From: Inès Varhol STM32L4x5 GPIO wasn't migrating its clock. Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240507185854.34572-3-ines.var...@telecom-paris.fr> Signed-off-by: Philippe Mathieu-Daudé --- hw/gpio/stm32l4x5_gpio.c | 6 -- 1 file changed, 4 inser

[PULL 13/26] hw/i386: Have x86_bios_rom_init() take X86MachineState rather than MachineState

From: Bernhard Beschow The function creates and leaks two MemoryRegion objects regarding the BIOS which will be moved into X86MachineState in the next steps to avoid the leakage. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430150643.111976-3-shen...@gm

[PULL 12/26] hw/i386/x86: Eliminate two if statements in x86_bios_rom_init()

From: Bernhard Beschow Given that memory_region_set_readonly() is a no-op when the readonlyness is already as requested it is possible to simplify the pattern if (condition) { foo(true); } to foo(condition); which is shorter and allows to see the invariant of the code more easily.

[PULL 04/26] hw/ppc/spapr_pci: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize t

Re: [PATCH] hw/clock: Expose 'freq-hz' QOM property

On Wed, 8 May 2024 at 15:13, Philippe Mathieu-Daudé wrote: > > Expose the clock frequency via the QOM 'freq-hz' property, > as it might be useful for QTests. > > HMP example: > > $ qemu-system-mips -S -monitor stdio -M mipssim > (qemu) qom-get /machine/cpu-refclk freq-hz > 1200 > > Inspi

[PULL 09/26] hw/i386/pc: Allow to compile without CONFIG_FDC_ISA

From: Thomas Huth The q35 machine can work without FDC. But to be able to also link a QEMU binary that does not include the FDC code, we have to make it possible to disable the spots that call into the FDC code. Signed-off-by: Thomas Huth Acked-by: Philippe Mathieu-Daudé Message-ID: <202404251

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