On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote:
>
> Since virt machine is common for multiple architectures, add "arch" in
> the path to search expected AML files. Since the AML files are still
> under old path, support both by searching with and without arch in the
> path.
>
> Signed-off-by: Su
On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote:
>
> Since virt is a common machine name across architectures like ARM64 and
> RISC-V, move existing ARM64 ACPI tables under aarch64 folder so that
> RISC-V tables can be added under riscv64 folder in future.
>
> Signed-off-by: Sunil V L
Reviewed-
On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote:
>
> so that ACPI table test can be supported.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/meson.build b/meson.build
> index b
On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote:
>
> Update list of images supported in unpack_edk2_blobs to enable RISC-V
> ACPI table testing.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> pc-bios/meson.build | 2 ++
> tests/qtest/meson.build | 3 +++
> 2
On Thu, Mar 14, 2024 at 7:23 PM Huang Tao wrote:
>
> In this patch, we modify the decoder to be a freely composable data
> structure instead of a hardcoded one. It can be dynamically builded up
> according to the extensions.
> This approach has several benefits:
> 1. Provides support for heterogen
On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote:
>
> Update the list of supported architectures to include RISC-V.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> tests/data/acpi/rebuild-expected-aml.sh | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote:
>
> Add expected ACPI tables for RISC-V so that bios-table-test can be
> enabled for RISC-V.
Can you detail where and how these files are generated/built?
Alistair
>
> Signed-off-by: Sunil V L
> ---
> tests/data/acpi/virt/riscv64/APIC | Bin 0
On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote:
>
> Add basic ACPI table testing for RISC-V.
>
> Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Alistair
> ---
> tests/qtest/bios-tables-test.c | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/tes
On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote:
>
> Both CSRRS and CSRRC always read the addressed CSR and cause any read side
> effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
> holding a zero value other than x0, the instruction will still attempt to
> wri
On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote:
>
> Both CSRRS and CSRRC always read the addressed CSR and cause any read side
> effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
> holding a zero value other than x0, the instruction will still attempt to
> wri
On Fri, Mar 15, 2024 at 5:01 AM Himanshu Chauhan
wrote:
>
> Check if each element of array of pointers for itimer contains a non-null
> pointer before freeing.
>
> Signed-off-by: Himanshu Chauhan
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/debug.c | 5 -
> 1 file changed,
On Fri, Mar 15, 2024 at 5:01 AM Himanshu Chauhan
wrote:
>
> The mcontrol6 triggers are not defined in debug specification v0.13
> These triggers are defined in sdtrig ISA extension.
>
> This patch:
>* Adds ext_sdtrig capability which is used to select mcontrol6 triggers
>* Keeps the debug
Moving VMX instructions of the following types to decodetree
specification : storage access, integer logical & integer max/min.
Chinmay Rath (3):
target/ppc: Move VMX storage access instructions to decodetree
target/ppc: Move VMX integer logical instructions to decodetree
target/ppc: Move VM
Moving the following instructions to decodetree specification :
v{max, min}{u, s}{b, h, w, d} : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rat
Moving the following instructions to decodetree specification :
{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r}: X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_
Moving the following instructions to decodetree specification:
v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form
The changes were verified by validating that the tcp ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-
On Fri, Mar 15, 2024 at 5:02 AM Himanshu Chauhan
wrote:
>
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
>-cpu rv64,sdtrig=
> option can be used to dynamically turn sdtrig e
W dniu 26.04.2024 o 18:06, Richard Henderson pisze:
Isn't this basically what MPIDR_EL1 is supposed to indicate?
We do not yet implement all of that in QEMU, but should.
QEMU has socket/cluster/core/thread model which could map to
aff3/aff2/aff1/aff0 (or aff0/1/2/3) of MPIDR_EL1 register, righ
W dniu 26.04.2024 o 14:29, Peter Maydell pisze:
The default frequency used by the 'max' CPU is about to change, so
make the sbsa-ref board force the CPU frequency to the value which
the firmware expects.
Newer versions of TF-A will read the frequency from the CPU's
CNTFRQ_EL0 register:
https:
Fixes: 1590154ee437 ("target/loongarch: Fix qemu-system-loongarch64 assert
failed with the option '-d int'")
Signed-off-by: Michael Tokarev
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/targ
From: Thomas Huth
Printing a "PowerPC" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's
From: Daniel Henrique Barboza
Commit d424db2354 excluded some strerrorname_np() instances because they
break musl libc builds. Another instance happened to slip by via commit
d4ff3da8f4.
Remove it before it causes trouble again.
Fixes: d4ff3da8f4 (target/riscv/kvm: initialize 'vlenb' via get-re
From: Thomas Huth
Printing an "x86" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's si
From: Philippe Mathieu-Daudé
The .mailmap file fixes mistake we already did.
Do not use it when running checkpatch.pl, otherwise
we might commit the very same mistakes.
Reported-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael Tokarev
Signed-off-by: Michael Tokarev
From: Daniel Henrique Barboza
Commit d424db2354 removed an instance of strerrorname_np() because it
was breaking building with musl libc. A recent RISC-V patch ended up
re-introducing it again by accident.
Put this function in the baddies list in checkpatch.pl to avoid this
situation again. This
From: Thomas Huth
Printing an "s390x" in front of each CPU name is not helpful at all:
It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and
it also takes some precious space in the dense output of the CPU
entries. Let's
The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479:
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
(2024-04-26 15:28:13 -0700)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
for you to
From: Philippe Mathieu-Daudé
Commit f5177798d8 ("scripts: report on author emails
that are mangled by the mailing list") added a check
for qemu-devel@ list, extend the regexp to cover more
such qemu-trivial@, qemu-block@ and qemu-ppc@.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Michael
From: Li Zhijian via
It seems that this error does not need to be propagated to the upper,
directly output the error to avoid the leaks
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283
Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode")
Signed-off-by: Li Zhijian
Reviewed-b
Introduce HostIOMMUDevice as an abstraction of host IOMMU device.
Introduce .realize() to initialize HostIOMMUDevice further after
instance init.
Introduce a macro CONFIG_HOST_IOMMU_DEVICE to define the usage
for VFIO, and VDPA in the future.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzh
HostIOMMUDeviceLegacyVFIO represents a host IOMMU device under VFIO
legacy container backend.
It includes a link to VFIODevice.
Suggested-by: Eric Auger
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 12
hw/vfio/container.c
Hi,
The most important change in this version is instroducing a common
HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface
between vIOMMU and HostIOMMUDevice.
HostIOMMUDeviceClass::realize() is introduced to initialize
HostIOMMUDeviceCaps and other fields of HostIOMMUDevice varia
HostIOMMUDeviceIOMMUFDVFIO represents a host IOMMU device under VFIO
iommufd backend. It will be created during VFIO device attaching and
passed to vIOMMU.
It includes a link to VFIODevice so that we can do VFIO device
specific operations, i.e., [at/de]taching hwpt, etc.
Signed-off-by: Zhenzhong
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
backends/iommufd.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/backends/iommufd.c b/backends/iommufd.c
index d61209788a..28faec528e 100644
--- a/backends/iommufd.c
+++ b/backends/iommufd.c
@@ -233,6 +233
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
hw/vfio/container.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/vfio/container.c b/hw/vfio/container.c
index 863eec3943..3683487605 100644
--- a/hw/vfio/container.c
+++ b/hw/vfio/container.c
@@ -1164,11 +11
It calls iommufd_backend_get_device_info() to get host IOMMU
related information and translate it into HostIOMMUDeviceCaps
for query with .check_cap().
Introduce macro VTD_MGAW_FROM_CAP to get MGAW which equals to
(aw_bits - 1).
Signed-off-by: Zhenzhong Duan
---
include/hw/i386/intel_iommu.h |
With HostIOMMUDevice passed, vIOMMU can check compatibility with host
IOMMU, call into IOMMUFD specific methods, etc.
Originally-by: Yi Liu
Signed-off-by: Nicolin Chen
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw/vfio/pci.c | 20 +++-
1 file changed, 15 insertion
From: Yi Liu
pci_device_[set|unset]_iommu_device() call pci_device_get_iommu_bus_devfn()
to get iommu_bus->iommu_ops and call [set|unset]_iommu_device callback to
set/unset HostIOMMUDevice for a given PCI device.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Nicolin Chen
Signed-o
Utilize range_get_last_bit() to get host IOMMU address width and
package it in HostIOMMUDeviceCaps for query with .check_cap().
Signed-off-by: Zhenzhong Duan
---
hw/vfio/container.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/vfio/container.c b/hw/vfio/c
From: Yi Liu
Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU.
In set call, a new structure VTDHostIOMMUDevice which holds
a reference to HostIOMMUDevice is stored in hash table
indexed by PCI BDF.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
hw
Create host IOMMU device instance in vfio_attach_device() and call
.realize() to initialize it further.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-common.h | 1 +
hw/vfio/common.c | 18 +-
2 files changed, 18 insertions(+)
If check fails, host device (either VFIO or VDPA device) is not
compatible with current vIOMMU config and should not be passed to
guest.
Only aw_bits is checked for now, we don't care other capabilities
before scalable modern mode is introduced.
Signed-off-by: Yi Liu
Signed-off-by: Zhenzhong Dua
HostIOMMUDeviceCaps's elements map to the host IOMMU's capabilities.
Different platform IOMMU can support different elements.
Currently only two elements, type and aw_bits, type hints the host
platform IOMMU type, i.e., INTEL vtd, ARM smmu, etc; aw_bits hints
host IOMMU address width.
Introduce .
Extract out pci_device_get_iommu_bus_devfn() from
pci_device_iommu_address_space() to facilitate
implementation of pci_device_[set|unset]_iommu_device()
in following patch.
No functional change intended.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Nicolin Chen
Signed-off-by: Zhe
Introduce a helper function iommufd_backend_get_device_info() to get
host IOMMU related information through iommufd uAPI.
Signed-off-by: Yi Liu
Signed-off-by: Yi Sun
Signed-off-by: Zhenzhong Duan
---
include/sysemu/iommufd.h | 4
backends/iommufd.c | 24 +++-
2
Initialize attribute VFIOIOMMUClass::hiod_typename based on
VFIO backend type.
This attribute will facilitate HostIOMMUDevice creation in
vfio_attach_device().
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/hw/vfio/vfio-container-base.h | 3 +++
hw/vfio/container.c
Extract cap/ecap initialization in vtd_cap_init() to make code
cleaner.
No functional change intended.
Reviewed-by: Eric Auger
Signed-off-by: Zhenzhong Duan
---
hw/i386/intel_iommu.c | 93 ---
1 file changed, 51 insertions(+), 42 deletions(-)
diff --git
HostIOMMUDeviceIOMMUFD represents a host IOMMU device under iommufd
backend.
Currently it contains public iommufd handle and device id which
will be passed to vIOMMU to allocate/free ioas, hwpt, etc.
When nested translation is supported in future, vIOMMU will
request iommufd related operations li
This helper get the highest 1 bit position of the upper bound.
If the range is empty or upper bound is zero, -1 is returned.
Suggested-by: Cédric Le Goater
Signed-off-by: Zhenzhong Duan
---
include/qemu/range.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/qemu/range
201 - 249 of 249 matches
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