Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT

On Sun, Apr 21, 2024 at 11:40 AM Richard Henderson wrote: > > On 4/19/24 11:31, Dorjoy Chowdhury wrote: > > + > > +/* > > + * Instantiate a temporary CPU object to build mp_affinity > > + * of the possible CPUs. > > + */ > > +cpuobj = object_new(ms->cpu_type); > > +armcpu =

Re: Qemu for TC377

Hi Sameer, On Tue, Apr 16, 2024 at 02:26:10PM -0400, Sameer Kalliadan Poyil wrote: > Hi Bastian, > > Thanks for the information. I thought that I can do some prototyping before > the > HW arrives. :) > >  Yes I am interested for your bare metal program boot_to_main run it on TSIM.  >   > Is Infin

Re: [PATCH v3 2/2] cxl/core: add poison creation event handler

patch link: https://lore.kernel.org/r/20240417075053.3273543-3-ruansy.fnst%40fujitsu.com patch subject: [PATCH v3 2/2] cxl/core: add poison creation event handler config: csky-randconfig-002-20240421 (https://download.01.org/0day-ci/archive/20240421/202404212044.usxtgrtl-...@intel.com/config) compiler:

[PATCH v5 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 59 +++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/ar

[PATCH v5 3/5] hw/arm : Create Bl475eMachineState

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/b-l475e-iot01a.c | 46 - 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa4

[PATCH v5 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC

Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC to the optional DM163 display from the board code (GPIOs outputs need to be connected to both SYSCFG inputs and DM163 inputs). STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. Signed-off-by: Arnaud Minie

[PATCH v5 0/5] Add device DM163 (led driver, matrix colors shield & display)

This device implements the IM120417002 colors shield v1.1 for Arduino (which relies on the DM163 8x3-channel led driving logic) and features a simple display of an 8x8 RGB matrix. This color shield can be plugged on the Arduino board (or the B-L475E-IOT01A board) to drive an 8x8 RGB led matrix. Thi

[PATCH v5 1/5] hw/display : Add device DM163

This device implements the IM120417002 colors shield v1.1 for Arduino (which relies on the DM163 8x3-channel led driving logic) and features a simple display of an 8x8 RGB matrix. The columns of the matrix are driven by the DM163 and the rows are driven externally. Acked-by: Alistair Francis Sign

[PATCH v5 5/5] tests/qtest : Add testcase for DM163

`test_dm163_bank()` Checks that the pin "sout" of the DM163 led driver outputs the values received on pin "sin" with the expected latency (depending on the bank). `test_dm163_gpio_connection()` Check that changes to relevant STM32L4x5 GPIO pins are propagated to the DM163 device. Signed-off-by: A

[PATCH] hw/misc : Correct 5 spaces indents in stm32l4x5_exti

Signed-off-by: Inès Varhol --- hw/misc/stm32l4x5_exti.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c index 9fd859160d..5c55ee4268 100644 --- a/hw/misc/stm32l4x5_exti.c +++ b/hw/misc/stm32l4x5_exti.c @@ -59,22 +59,2

Re: [PATCH 05/24] exec: Restrict 'cpu_ldst.h' to TCG accelerator

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "exec/cpu_ldst.h" is specific to TCG, do not allow its inclusion from other accelerators. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu_ldst.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) Reviewed-by: Richard Henders

Re: [PATCH 06/24] exec: Have guest_addr_valid() methods take abi_ptr/size_t arguments

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: abi_ulong is target specific, replace by abi_ptr which isn't. Use size_t for the @len type. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu_ldst.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/c

Re: [PATCH 07/24] exec: Un-inline tlb_vaddr_to_host() and declare it in 'exec/cputlb.h'

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: Declare tlb_vaddr_to_host() in "exec/cputlb.h" with the CPU TLB API. Un-inline the user emulation definition to avoid including "exec/cpu_ldst.h" (which declares g2h) in "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu

Re: [PATCH 08/24] physmem: Move TCG CPU IOTLB methods around

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: The next commit will restrict TCG specific code in physmem.c using some #ifdef'ry. In order to keep it simple, move iotlb_to_section() and memory_region_section_get_iotlb() around close together. Signed-off-by: Philippe Mathieu-Daudé --- system/p

Re: [PATCH 10/24] exec: Reduce tlb_set_dirty() declaration scope

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: tlb_set_dirty() is only used in accel/tcg/cputlb.c, where it is defined. Declare it statically, removing the stub. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 1 - accel/stubs/tcg-stub.c | 4 accel/tcg/cputlb.c

Re: [PATCH 12/24] exec: Move CPUTLBEntry helpers to cputlb.c

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: The following CPUTLBEntry helpers are only used in accel/tcg/cputlb.c: - tlb_index() - tlb_entry() - tlb_read_idx() - tlb_addr_write() Move them to this file, allowing to remove the huge "cpu.h" header inclusion from "exec/cpu_ldst.h".

Re: [PATCH 13/24] target/sparc: Replace abi_ulong by uint32_t for TARGET_ABI32

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: We have abi_ulong == uint32_t for the 32-bit ABI. Use the generic type to avoid to depend on the "exec/user/abitypes.h" header. Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-

Re: [PATCH 17/24] exec: Include missing 'qemu/log-for-trace.h' header in 'exec/log.h'

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "exec/log.h" accesses the qemu_loglevel variable, which is declared in "qemu/log-for-trace.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/log.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/log.h b/include/exec/lo

Re: [PATCH 18/24] plugins: Include missing 'qemu/bitmap.h' header

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "qemu/plugin.h" uses DECLARE_BITMAP(), which is declared in "qemu/bitmap.h". Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/plugin.h | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson r~

Re: [PATCH 19/24] gdbstub: Avoid including 'cpu.h' in 'gdbstub/helpers.h'

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: We only need the "exec/tswap.h" and "cpu-param.h" headers. Only include "cpu.h" in the target gdbstub.c source files. Signed-off-by: Philippe Mathieu-Daudé --- include/gdbstub/helpers.h | 3 ++- target/avr/gdbstub.c | 1 + target/tricore/g

Re: [PATCH 21/24] plugins: Un-inline qemu_plugin_disable_mem_helpers()

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "qemu/plugin.h" only include the huge "hw/core/cpu.h" because qemu_plugin_disable_mem_helpers() accesses CPUState::plugin_mem_cbs. In order to avoid including it, un-inline qemu_plugin_disable_mem_helpers(). Signed-off-by: Philippe Mathieu-Daudé -

Re: [PATCH] target/riscv: Use get_address() to get address with Zicbom extensions

On 4/19/24 08:05, Philippe Mathieu-Daudé wrote: We need to use get_address() to get an address from cpu_gpr[], since $zero is "special" (NULL). Fixes: e05da09b7c ("target/riscv: implement Zicbom extension") Reported-by: Zhiwei Jiang (姜智伟) Signed-off-by: Philippe Mathieu-Daudé --- Reviewed

Re: [PATCH 23/24] exec: Remove 'disas/disas.h' from 'exec/log.h'

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: "exec/log.h" doesn't require "disas/disas.h". Remove it, including it in the sources when required. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/log.h | 1 - target/avr/translate.c | 1 + target/hexagon/transl

Re: [PATCH 24/24] exec: Remove unnecessary inclusions of 'hw/core/cpu.h'

On 4/18/24 12:25, Philippe Mathieu-Daudé wrote: When "hw/core/cpu.h" is not required, remove it. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h| 1 - include/exec/cpu-defs.h | 1 - include/hw/boards.h | 1 - include/hw/ppc/openpic.h | 1 - include/sysemu/hw_a

[PATCH] hw/virtio: Fix obtain the buffer id from the last descriptor

The virtio-1.3 specification writes: 2.8.6 Next Flag: Descriptor Chaining Buffer ID is included in the last descriptor in the list. If the feature (_F_INDIRECT_DESC) has been negotiated, install only one descriptor in the virt

Re: [PATCH v13 00/24] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI

On 2024/4/19 21:41, Peter Maydell wrote: > On Sun, 7 Apr 2024 at 09:19, Jinjie Ruan wrote: >> >> This patch set implements FEAT_NMI and FEAT_GICv3_NMI for ARMv8. These >> introduce support for a new category of interrupts in the architecture >> which we can use to provide NMI like functionality

Re: [RFC PATCH 1/3] target/riscv: change RISCV_EXCP_SEMIHOST exception number

On Thu, Apr 18, 2024 at 11:40 PM Clément Léger wrote: > > The double trap specification defines the double trap exception number > to be 16 which is actually used by the internal semihosting one. Change > it to some other value. > > Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Al

Re: [PATCH v3] riscv: thead: Add th.sxstatus CSR emulation

On Thu, Apr 18, 2024 at 8:55 AM Christoph Müllner wrote: > > The th.sxstatus CSR can be used to identify available custom extension > on T-Head CPUs. The CSR is documented here: > > https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc > > An important property of

Re: [PATCH v4] target/riscv/kvm/kvm-cpu.c: kvm_riscv_handle_sbi() fail with vendor-specific SBI

On Sat, Apr 13, 2024 at 9:26 PM Alexei Filippov wrote: > > kvm_riscv_handle_sbi() may return not supported return code to not trigger > qemu abort with vendor-specific sbi. > > Added SBI related return code's defines. > > Signed-off-by: Alexei Filippov > Fixes: 4eb47125 ("target/riscv: Handle KVM

[PATCH] hw/ufs: Fix buffer overflow bug

It fixes the buffer overflow vulnerability in the ufs device. The bug was detected by sanitizers. You can reproduce it by: cat << EOF |\ qemu-system-x86_64 \ -display none -machine accel=qtest -m 512M -M q35 -nodefaults -drive \ file=null-co://,if=none,id=disk0 -device ufs,id=ufs_bus -device \ uf

Re: [PATCH 5/8] target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree.

Hi Richard, On 4/20/24 21:21, Richard Henderson wrote: On 4/19/24 02:25, Chinmay Rath wrote: Hi Richard, On 4/17/24 00:06, Richard Henderson wrote: On 4/15/24 23:39, Chinmay Rath wrote: +static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a) ... +    tcg_gen_movi_i64(t1, 0); Drop t

Re: [PATCH v3] riscv: thead: Add th.sxstatus CSR emulation

On Mon, Apr 22, 2024 at 5:29 AM Alistair Francis wrote: > > On Thu, Apr 18, 2024 at 8:55 AM Christoph Müllner > wrote: > > > > The th.sxstatus CSR can be used to identify available custom extension > > on T-Head CPUs. The CSR is documented here: > > > > https://github.com/T-head-Semi/thead-ext

[PATCH v4] riscv: thead: Add th.sxstatus CSR emulation

The th.sxstatus CSR can be used to identify available custom extension on T-Head CPUs. The CSR is documented here: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc An important property of this patch is, that the th.sxstatus MAEE field is not set (indicating t