On Tue, Apr 16, 2024 at 9:54 AM Akihiko Odaki wrote:
>
> On 2024/04/16 13:00, Jason Wang wrote:
> > On Mon, Apr 15, 2024 at 10:05 PM Yuri Benditovich
> > wrote:
> >>
> >> On Wed, Apr 3, 2024 at 2:11 PM Akihiko Odaki
> >> wrote:
> >>>
> >>> vhost requires eBPF for RSS. When eBPF is not available
On 20.04.24 07:46, Thomas Huth wrote:
Printing an architecture prefix in front of each CPU name is not helpful
at all: It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and it also
takes some precious space in the dense o
On 4/19/24 02:25, Chinmay Rath wrote:
Hi Richard,
On 4/17/24 00:06, Richard Henderson wrote:
On 4/15/24 23:39, Chinmay Rath wrote:
+static bool trans_MADDHDU(DisasContext *ctx, arg_MADDHDU *a)
...
+ tcg_gen_movi_i64(t1, 0);
Drop the movi.
+ tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo,
On 4/19/24 04:05, Philippe Mathieu-Daudé wrote:
We need to use get_address() to get an address from cpu_gpr[],
since $zero is "special" (NULL).
Fixes: e05da09b7c ("target/riscv: implement Zicbom extension")
Reported-by: Zhiwei Jiang (姜智伟)
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/
On 4/19/24 22:46, Thomas Huth wrote:
Thomas Huth (3):
target/i386/cpu: Remove "x86" prefix from the CPU list
target/s390x/cpu_models: Rework the output of "-cpu help"
target/ppc/cpu_init: Remove "PowerPC" prefix from the CPU list
Reviewed-by: Richard Henderson
r~
On 4/19/24 01:48, Thomas Huth wrote:
Thomas Huth (4):
target/sparc/cpu: Rename the CPU models with a "+" in their names
target/sparc/cpu: Avoid spaces by default in the CPU names
docs/system/target-sparc: Improve the Sparc documentation
docs/about: Deprecate the old "UltraSparc" CPU n
On 4/19/24 01:58, Philippe Mathieu-Daudé wrote:
We are running this test since almost a year; it is
safe to remove its debug statements, which clutter
CI jobs output:
▶ 88/100 /nested-aio-poll OK
io_read 0x16bb26158
io_poll_true 0x16bb26158
> io_poll_ready
io
20.04.2024 08:46, Thomas Huth:
Printing an architecture prefix in front of each CPU name is not helpful
at all: It is confusing for the users since they don't know whether they
have to specify these letters for the "-cpu" parameter, too, and it also
takes some precious space in the dense output o
On 4/19/24 11:46, Peter Maydell wrote:
The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property. Clean it up:
On 4/19/24 11:46, Peter Maydell wrote:
In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequenc
Hi,
I have booted up the xlnx-versal-virt machine using qemu-system-aarch64. I
wanted to work with can device that has been modelled with this device. I
have used the xilinx_can.c driver for this device and can see two can
controllers. The problem is I am not able to see any interrupts in
/proc/int
Am 16.04.24 um 14:17 schrieb Stefan Weil:
Am 16.04.24 um 14:10 schrieb Peter Maydell:
The cross-i686-tci job is flaky again, with persistent intermittent
failures due to jobs timing out.
[...]
Some of these timeouts are very high -- no test should be taking
10 minutes, even given TCI and a sl
On Fri, Apr 19, 2024 at 11:43:14AM -0700, fan wrote:
> On Fri, Apr 19, 2024 at 02:24:36PM -0400, Gregory Price wrote:
> >
> > added review to all patches, will hopefully be able to add a Tested-by
> > tag early next week, along with a v1 RFC for MHD bit-tracking.
> >
> > We've been testing v5/v6
On 4/18/24 12:25, Philippe Mathieu-Daudé wrote:
The MMUAccessType enum is declared in "hw/core/cpu.h".
"hw/core/cpu.h" contains declarations related to CPUState
and CPUClass. Some source files only require MMUAccessType
and don't need to pull in all CPU* declarations. In order
to simplify, create
On 4/18/24 12:25, Philippe Mathieu-Daudé wrote:
The CPUBreakpoint and CPUWatchpoint structures are declared
in "hw/core/cpu.h", which contains declarations related to
CPUState and CPUClass. Some source files only require the
BP/WP definitions and don't need to pull in all CPU* API.
In order to si
On 4/18/24 12:25, Philippe Mathieu-Daudé wrote:
Only include what is required, avoiding the full
CPUState API from the huge "hw/core/cpu.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/tcg-cpu-ops.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by:
On 4/18/24 12:25, Philippe Mathieu-Daudé wrote:
Avoid TCG specific declarations being used from non-TCG accelerators.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 5 +
1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson
r~
On 4/19/24 11:31, Dorjoy Chowdhury wrote:
+
+/*
+ * Instantiate a temporary CPU object to build mp_affinity
+ * of the possible CPUs.
+ */
+cpuobj = object_new(ms->cpu_type);
+armcpu = ARM_CPU(cpuobj);
+
for (n = 0; n < ms->possible_cpus->len; n++) {
ms->po
18 matches
Mail list logo
