On Fri, Apr 12, 2024 at 12:15:40PM +0200, Eugenio Perez Martin wrote:
> Hi!
>
> I'm building a bridge to expose vhost-user devices through VDUSE. The
> code is still immature but I'm able to forward packets using
> dpdk-l2fwd through VDUSE to VM. I'm now developing exposing virtiofsd,
> but I've h
On Fri, 12 Apr 2024 at 19:55, Richard Henderson
wrote:
>
> Since this problem has 4 issues open, let's get it for 9.0.
>
>
> r~
>
>
> The following changes since commit be72d6ab361a26878752467a17289066dfd5bc28:
>
> Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
> (2024
On Sat, 13 Apr 2024, Philippe Mathieu-Daudé wrote:
On 11/4/24 21:24, BALATON Zoltan wrote:
Real 460EX SoC apparently does not expose a bridge device and having
it appear on PCI bus confuses an AmigaOS file system driver that uses
this to detect which machine it is running on.
Signed-off-by: BAL
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/b-l475e-iot01a.c | 44 +
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index d862aa43fc..2b570b3e09 100644
--- a/hw/arm/b
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.
Acked-by: Alistair Francis
Sign
`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).
`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
DM163 device.
Signed-off-by: A
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. This color shield can be plugged
on the Arduino board (or the B-L475E-IOT01A board) to drive an 8x8
RGB led matrix. Thi
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/b-l475e-iot01a.c | 59 +++--
hw/arm/Kconfig | 1 +
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 2b570b3e09..
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
Signed-off-by: Arnaud Minie
The messages for STM32L4x5 tests will be easier to understand with
`g_assert_cmphex` since the comparisions were made with hexadecimal
numbers.
Signed-off-by: Inès Varhol
---
tests/qtest/stm32l4x5_exti-test.c | 138 ++--
tests/qtest/stm32l4x5_syscfg-test.c | 74 +++
This is a note to let you know that I've just added the patch titled
virtio_net: Do not send RSS key if it is not supported
to the 6.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
Hi Sameer,
On 13/4/24 14:52, Sameer Kalliadan Poyil wrote:
Hello All,
I see that Latest qemu supports for tricore TC277 and TC377
image.png
But when I downloaded source code and checked for TC377 related file , I
didn't find anything
I want to run RTOS/bare metal code on TC377 . could you ple
Hi Inès,
On 14/4/24 15:24, Inès Varhol wrote:
The messages for STM32L4x5 tests will be easier to understand with
`g_assert_cmphex` since the comparisions were made with hexadecimal
"comparisons"
numbers.
Signed-off-by: Inès Varhol
---
tests/qtest/stm32l4x5_exti-test.c | 138 +++
- Le 14 Avr 24, à 18:19, Philippe Mathieu-Daudé phi...@linaro.org a écrit :
> Hi Inès,
Hello Philippe !
>
> On 14/4/24 15:24, Inès Varhol wrote:
>> The messages for STM32L4x5 tests will be easier to understand with
>> `g_assert_cmphex` since the comparisions were made with hexadecimal
>
On 4/13/24 18:54, M Bazz wrote:
This thought just came to me. `lda` is a privileged instruction. It has to
run in supervisor mode. So, I'm struggling to understand how the
kernel permission was wrong. Isn't that the right permission for this
instruction?
The "current" permission, as computed b
The messages for assertions using hexadecimal numbers will be
easier to understand with `g_assert_cmphex`.
Cases changed : "cmpuint.*0x", "cmpuint.*<<"
Signed-off-by: Inès Varhol
---
tests/qtest/aspeed_fsi-test.c | 20 ++--
tests/qtest/cmsdk-apb-dualtimer-test.c | 2 +-
tests/qtest/
Hi,
On Friday, April 5, 2024 12:36:02 AM IST Sahil wrote:
> [...]
> I'll set up this environment as well.
I would like to post an update here. I spent the last week
trying to set up the environment as described in the blog [1].
I initially tried to get the L1 VM running on my host machine
(Arch
PING
Hi all, could you have a look at this small patch?
See also:
https://patchew.org/QEMU/20240330203520.64892-1-giacomo.parmeggi...@gmail.com/
BR,
Giacomo Parmeggiani
On Sat, Mar 30, 2024 at 9:36 PM Giacomo Parmeggiani <
giacomo.parmeggi...@gmail.com> wrote:
> This introduces the GigaDevice G
Hi Henry,
I want to thank you for every chance I get to learn from you. Each
email excites me.
On Sun, Apr 14, 2024 at 1:20 PM Richard Henderson
wrote:
> The "current" permission, as computed by
>
> > -case ASI_KERNELTXT: /* Supervisor code access */
> > -oi = make_memop_idx(memop, c
QE tested this patch with regression tests, everything works fine.
Tested-by: Lei Yang
On Fri, Apr 12, 2024 at 2:37 PM Cindy Lu wrote:
>
> Hi All
> I apologize for bothering you again
> I send the new patch is because I found that the function
> kvm_virtio_pci_vector_use_one/kvm_virtio_pci_vect
Gentle ping...
On 2024-04-09 17:43, Chao Du wrote:
>
> Hi Daniel and all,
>
> The KVM patches have been reviewd and are in the queue.
> https://lore.kernel.org/all/20240402062628.5425-1-duc...@eswincomputing.com/
>
> Could you please review in the QEMU side ?
> Then I will rebase this series w
> -Original Message-
> From: Fabiano Rosas
> Sent: Thursday, April 11, 2024 10:40 PM
> To: Zhang, Hailiang ; Zhang, Chen
> ; Li Zhijian
> Cc: qemu-devel@nongnu.org; Peter Xu
> Subject: COLO state?
>
> Hi COLO maintainers,
>
> Would you please take a look at this issue?
>
> https://
On 14/04/2024 15.05, Inès Varhol wrote:
`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).
`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propaga
Ping
On Mon, Apr 8, 2024 at 8:08 PM Hyman Huang wrote:
> When configuring VMs with the CDROM device using the USB bus
> in Libvirt, do as follows:
>
>
>
>
>
>
>
>
>
>
> The destination Qemu process crashed, causing the VM migration
> to fail; the backtrace reveals the following
On Fri, Apr 12, 2024 at 2:28 PM Cindy Lu wrote:
>
> During the booting process of the non-standard image, the behavior of the
> called function in qemu is as follows:
>
> 1. vhost_net_stop() was triggered by guest image. This will call the function
> virtio_pci_set_guest_notifiers() with assgin= f
On 4/11/24 15:45, Philippe Mathieu-Daudé wrote:
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,
resulting in painful developper experience.
s/developper/developer ?
Replace sprintf() by snprintf() in order to avoid:
hw/ppc/spapr.c:385:5: warning: 'sprintf' is deprecat
When emulated with QEMU, interrupts will never come in the following
loop. However, if the NOP instruction is uncommented, interrupts will
fire as normal.
loop:
cli
call do_sti
jmp loop
do_sti:
sti
# n
The hart bit setting is different with Linux AIA driver[1] when the number
of hart is power of 2. For example, when the guest has 4 harts, the
estimated result of AIA driver is 2, whereas we pass 3 to RISC-V/KVM. Since
only 2 bits are needed to represent 4 harts, update the formula to get the
accur
A9MPCORE, ARM11MPCORE and A15MPCORE are defined twice, once in
hw/cpu/Kconfig and once in hw/arm/Kconfig. This is only possible
by accident, since hw/cpu/Kconfig is never included from hw/Kconfig.
Fix it by declaring the switches only in hw/cpu/Kconfig (since the
related files reside in the hw/cpu/
First patch fixes the problem that the file hw/cpu/Kconfig is
currently ignored and the switches there are duplicated in hw/arm/.
The second patch introduces a proper config switch for the cpu-cluster
device.
v2:
- Don't make core.c depend on the CPU_CLUSTER switch
- Added Philippe's Reviewed-bys
The cpu-cluster device is only needed for some few arm and riscv
machines. Let's avoid compiling and linking it if it is not really
necessary.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
hw/arm/Kconfig | 3 +++
hw/cpu/Kconfig | 3 +++
hw/cpu/meson.build | 3 ++-
h
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