Hi,
On 2/21/24 18:17, Nabih Estefan wrote:
> From: Roque Arcudia Hernandez
>
> According to the SMMU specification the StreamID construction and size is
> IMPLEMENTATION DEFINED, the size being between 0 and 32 bits.
>
> This patch creates virtual functions get_sid and get_iommu_mr to allow
> di
Hi Eric,
On 23/2/24 08:27, Eric Auger wrote:
We used to set the default granule to 4KB but with VFIO assignment
it makes more sense to use the actual host page size.
Indeed when hotplugging a VFIO device protected by a virtio-iommu
on a 64kB/64kB host/guest config, we current get a qemu crash:
Hi Philippe,
On 2/23/24 08:52, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 23/2/24 08:27, Eric Auger wrote:
>> Introduce a new enum type property allowing to set an
>> IOMMU granule. Values are 4K, 8K, 16K, 64K and host.
>> This latter indicates the vIOMMU granule will match
>> the host page s
Initialize apshift to avoid a maybe-uninitialized error:
C compiler for the host machine: cc -m64 -mbig-endian (gcc 13.2.0 "cc (Debian
13.2.0-10) 13.2.0")
C linker for the host machine: cc -m64 -mbig-endian ld.bfd 2.41.90.20240115
Host machine cpu family: ppc64
Host machine cpu: ppc64
.
Reviewed-by: Konstantin Kostiuk
On Thu, Feb 22, 2024 at 5:28 PM Philippe Mathieu-Daudé
wrote:
> Most of the code base use the 'const' qualifier *before*
> the type being qualified. Use the same style to unify.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> qga/commands-win32.c | 22 +++
On 2/23/24 08:57, Philippe Mathieu-Daudé wrote:
> On 23/2/24 08:27, Eric Auger wrote:
>> This allows to choose which granule will be used by
>> default by the virtio-iommu. Current page size mask
>> default is qemu_target_page_mask so this translates
>> into a 4K granule.
>>
>> Signed-off-by: Er
Reviewed-by: Konstantin Kostiuk
On Thu, Feb 22, 2024 at 5:28 PM Philippe Mathieu-Daudé
wrote:
> ga_get_win_name() iterates over all elements in the arrays by
> checking the 'version' field is non-NULL. Since the arrays are
> guarded by a NULL terminating element, we don't need to specify
> thei
On 2/23/24 09:08, Philippe Mathieu-Daudé wrote:
> Hi Eric,
>
> On 23/2/24 08:27, Eric Auger wrote:
>> We used to set the default granule to 4KB but with VFIO assignment
>> it makes more sense to use the actual host page size.
>>
>> Indeed when hotplugging a VFIO device protected by a virtio-iomm
Reviewed-by: Konstantin Kostiuk
On Thu, Feb 22, 2024 at 5:29 PM Philippe Mathieu-Daudé
wrote:
> From: Dehan Meng
>
> Add support of Windows Server 2025 in get-osinfo command
>
> Signed-off-by: Dehan Meng
> Message-ID: <20240222025352.58859-2-dem...@redhat.com>
> Signed-off-by: Philippe Mathie
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
Hi all,
This is my v2 series to clean and fix @errp dereference.
Introduction
The patches 1-6 fix the cases that deference @errp without
ERRP_GUARD(), and they are based on my previsous v1 [1].
The patch 7 is merged in this series from another single patch [2].
Ba
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts these restrict
From: Zhao Liu
IOAPICCommonClass implements its own private realize(), and this private
realize() allows error.
Since IOAPICCommonClass.realize() returns void, to check the error,
dereference @errp with ERRP_GUARD().
Signed-off-by: Zhao Liu
---
v2:
* Add the missing ERRP_GUARD(). (Markus)
*
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected
From: Shiju Jose
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patr
From: Shiju Jose
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
Get Supported Features retrieves the list of supported device specific
features. The settings of a feature can be retrieved using Get Feature and
op
From: Shiju Jose
Add support for the feature commands, device patrol scrub control and
DDR5 ECS control features.
CXL spec 3.1 section 8.2.9.6 describes optional device specific features.
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature.
CXL spec 3.1 section 8.
On Tue, Jan 02, 2024 at 08:49:54PM +0800, Marc-André Lureau wrote:
> Hi
>
> On Tue, Dec 19, 2023 at 11:55 AM Huang Rui wrote:
> >
> > From: Antonio Caggiano
> >
> > Enable resource UUID feature and implement command resource assign UUID.
> > This is done by introducing a hash table to map resour
On Tue, Jan 02, 2024 at 09:33:11PM +0800, Marc-André Lureau wrote:
> Hi
>
> On Tue, Dec 19, 2023 at 11:55 AM Huang Rui wrote:
> >
> > From: Antonio Caggiano
> >
> > Request Venus when initializing VirGL.
> >
> > Signed-off-by: Antonio Caggiano
> > Signed-off-by: Huang Rui
> > ---
> >
> > Chang
On Thu, 22 Feb 2024 at 12:58, Philippe Mathieu-Daudé wrote:
>
> The following changes since commit 760b4dcdddba4a40b9fa0eb78fdfc7eda7cb83d0:
>
> Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
> (2024-02-20 10:11:08 +)
>
> are available in the Git repository at:
>
>
On Thu, 22 Feb 2024 at 11:41, Daniel P. Berrangé wrote:
>
> Python is transitioning to a world where you're not allowed to use 'pip
> install' outside of a virutal env by default. The rationale is to stop
> use of pip clashing with distro provided python packages, which creates
> a major headache
On Thu, 22 Feb 2024 at 18:15, Kambalin, Sergey
wrote:
>
> Hi Peter!
>
> Sorry, it wasn't intentional.
>
> How can I keep the tags from v4?
If I reply with a 'Reviewed-by:' tag on a patch, and you
don't make major changes for the next version, copy that
tag into the commit message so it appears th
On Thu, 22 Feb 2024 at 21:21, Richard Henderson
wrote:
>
> On 2/19/24 06:12, Jonathan Cameron wrote:
> > I'm far from confident this handling here is correct. Hence
> > RFC. In particular not sure on what locks I should hold for this
> > to be even moderately safe.
> >
> > The function already ap
On Fri, 23 Feb 2024 at 06:23, Philippe Mathieu-Daudé wrote:
>
> Hi Peter,
>
> On 22/2/24 18:54, Peter Maydell wrote:
> > On Tue, 20 Feb 2024 at 13:42, Rayhan Faizel wrote:
> >>
> >> This patch series implements support for the Broadcom Serial Controller
> >> used
> >> by BCM2835 based boards for
On Tue, 20 Feb 2024 at 13:42, Rayhan Faizel wrote:
>
> A few deficiencies in the current device model need to be noted.
>
> 1. FIFOs are not used. All sends and receives are done directly.
> 2. Repeated starts are not emulated. Repeated starts can be triggered in real
> hardware by sending a new r
On Tue, 20 Feb 2024 at 13:42, Rayhan Faizel wrote:
>
> Simple testcase for validating proper operation of read and write for all
> three BSC controllers.
>
> Signed-off-by: Rayhan Faizel
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi all,
Yesterday, a bug but in hw/nvme (#2184) was filed
https://gitlab.com/qemu-project/qemu/-/issues/2184)
The reporter ran into an issue with hibernating a guest from QEMU v4.1.0
and trying to resume it on v8.2.1. hw/nvme has received some changes
since then, including a change in th
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
v3:
- Not include CPU_INTERRUPT_NMI when FEAT_NMI not enabled
- Add ARM_CPU_VNMI.
- Refator nmi mask in arm_excp_unmasked().
- Test SCTLR_ELx.NMI for ALLINT mask for NMI.
---
target/arm/cpu-qom.h | 4
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
target/arm/helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/targ
Support ALLINT msr access as follow:
mrs , ALLINT// read allint
msr ALLINT, // write allint with imm
Signed-off-by: Jinjie Ruan
---
v3:
- Remove EL0 check in aa64_allint_access() which alreay checks in .access
PL1_RW.
- Use arm_hcrx_el2_eff() in aa64_allint_acces
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Sorted to last.
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu64.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/d
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove the FIQ NMI handle.
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
d
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI, both
CPSR_I and ISR_IS must be set.
Signed-off-by: Jinjie Ruan
--
v3:
- CPU_INTERRUPT_NMI do not set FIQ, so remove it.
- With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set.
---
target/arm/cpu.h| 2 ++
target/a
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove EL0 check in allint_check().
- Add TALLINT check for EL1 in allint_check().
- Remove unnecessar
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
hw/intc/gicv3_internal.h | 1 +
include/hw/intc/
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_redist.c | 23 +++
hw/intc/gicv3_internal.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 815352
FEAT_NMI defines another thress new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Add HCRX_VINMI and HCRX_VFNMI support in HCRX_
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
---
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_gic_common.h | 2 ++
include/hw/intc/arm_gicv3_common.
A SPI, PPI or SGI interrupt can have a superpriority property. So
maintain superpriority information in PendingIrq and GICR/GICD.
Signed-off-by: Jinjie Ruan
Acked-by: Richard Henderson
---
v3:
- Place this ahead of implement GICR_INMIR.
- Add Acked-by.
---
include/hw/intc/arm_gicv3_common.h | 4
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FEAT_GICv3 supported.
Signed-off-by: Jinjie
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
---
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0af1943697..2d4a187fd5 100644
--- a/hw/arm/v
Add GICD_INMIR0, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
---
hw/intc/arm_gicv3_dist.c | 38 ++
hw/intc/gicv3_internal.h | 2 ++
2 files changed, 40 insertions(
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
---
v3:
- Remove nmi_is_irq flag in CPUARMState.
- Handle NMI same as IRQ in arm_phys_excp_targ
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan
Reviewed-by: Richard Henderson
---
v3:
- Add Reviewed-by.
- Adjust to before the MSR patches.
---
target/arm/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts.
Place this in its own field within ENV, as that will
make it easier to handle ALLINT set/clear.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie Ruan
---
v3:
- Re
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has super priority. And for ICC_NMIAR1_EL1
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pendi
On 2024/02/23 2:27, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/22 19:20, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/21 23:14, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/21 19:02, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/20 23:14, Alex Bennée wr
On 2024-02-16 12:03, Philippe Mathieu-Daudé wrote:
When the QOM parent is available, prefer object_initialize_child()
over object_initialize(), since it create the parent relationship.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
---
hw/net/can/xlnx-versal-canfd
On Fri, 23 Feb 2024 at 10:25, Klaus Jensen wrote:
>
> Hi all,
>
> Yesterday, a bug but in hw/nvme (#2184) was filed
>
> https://gitlab.com/qemu-project/qemu/-/issues/2184)
>
> The reporter ran into an issue with hibernating a guest from QEMU v4.1.0
> and trying to resume it on v8.2.1. hw/n
On 2024/02/23 2:10, Peter Maydell wrote:
On Thu, 22 Feb 2024 at 06:08, Michael Tokarev wrote:
[Adding a few more Ccs]
17.02.2024 18:58, David Parsons :
macOS Sonoma changes the NSView.clipsToBounds to false by default where it was
true in
earlier version of macOS. This causes the window con
On 23/2/24 09:38, Eric Auger wrote:
On 2/23/24 09:08, Philippe Mathieu-Daudé wrote:
Hi Eric,
On 23/2/24 08:27, Eric Auger wrote:
We used to set the default granule to 4KB but with VFIO assignment
it makes more sense to use the actual host page size.
Indeed when hotplugging a VFIO device pro
On 23/2/24 09:30, Eric Auger wrote:
Hi Philippe,
On 2/23/24 08:52, Philippe Mathieu-Daudé wrote:
Hi Eric,
On 23/2/24 08:27, Eric Auger wrote:
Introduce a new enum type property allowing to set an
IOMMU granule. Values are 4K, 8K, 16K, 64K and host.
This latter indicates the vIOMMU granule wil
On Thu, Feb 22, 2024 at 05:03:09PM -1000, Richard Henderson wrote:
> Handle combined host and guest alignment requirements.
> Handle host and guest page size differences.
> Handle SHM_EXEC.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/115
> Signed-off-by: Richard Henderson
> ---
>
Akihiko Odaki writes:
> On 2024/02/23 2:27, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> On 2024/02/22 19:20, Alex Bennée wrote:
Akihiko Odaki writes:
> On 2024/02/21 23:14, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> On 2024/02/21 19:02, Alex Bennée wro
On Thu, Feb 22, 2024 at 5:28 PM Philippe Mathieu-Daudé
wrote:
> ga_get_win_name() iterates over all elements in the arrays by
> checking the 'version' field is non-NULL. Since the arrays are
> guarded by a NULL terminating element, we don't need to specify
> their size:
>
> static char *ga_get_
Le 15/01/2024 à 11:16, Daniel Palmer a écrit :
From the 68010 a word with the frame format and exception vector
are placed on the stack before the PC and SR.
M68K_FEATURE_QUAD_MULDIV is currently checked to workout if to do
this or not for the configured CPU but that flag isn't set for
68010 so
Hi Inès,
On 7/2/24 14:23, Inès Varhol wrote:
Features supported :
- the 8 STM32L4x5 GPIOs are initialized with their reset values
(except IDR, see below)
- input mode : setting a pin in input mode "externally" (using input
irqs) results in an out irq (transmitted to SYSCFG)
- output mo
On Friday 23 of February 2024 12:06:34 Francisco Iglesias wrote:
> On 2024-02-16 12:03, Philippe Mathieu-Daudé wrote:
> > When the QOM parent is available, prefer object_initialize_child()
> > over object_initialize(), since it create the parent relationship.
> >
> > Signed-off-by: Philippe Mathieu
On 7/2/24 14:23, Inès Varhol wrote:
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
include/hw/arm/stm32l4x5_soc.h | 2 +
hw/arm/stm32l4x5_soc.c | 78 --
hw/arm/Kconfig | 3 +-
3 files changed, 68 insertions(+), 15 delet
On 7/2/24 14:23, Inès Varhol wrote:
The testcase contains :
- `test_idr_reset_value()` :
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
- `test_gpio_output_mode()` :
Checks that writing a bit in register ODR results in the corresponding
pin rising or lowering, if this pin is config
Peter Xu writes:
> On Thu, Feb 22, 2024 at 10:49:12AM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Thu, Feb 22, 2024 at 05:40:41PM +0800, Peter Xu wrote:
>> >> On Wed, Feb 21, 2024 at 09:56:36AM -0300, Fabiano Rosas wrote:
>> >> > Peter Xu writes:
>> >> >
>> >> > > On Mon, Feb 1
From: Ankit Agrawal
ACPI spec provides a scheme to associate "Generic Initiators" [1]
(e.g. heterogeneous processors and accelerators, GPUs, and I/O devices with
integrated compute or DMA engines GPUs) with Proximity Domains. This is
achieved using Generic Initiator Affinity Structure in SRAT. Du
From: Ankit Agrawal
There are upcoming devices which allow CPU to cache coherently access
their memory. It is sensible to expose such memory as NUMA nodes separate
from the sysmem node to the OS. The ACPI spec provides a scheme in SRAT
called Generic Initiator Affinity Structure [1] to allow an a
From: Ankit Agrawal
NVIDIA GPU's support MIG (Mult-Instance GPUs) feature [1], which allows
partitioning of the GPU device resources (including device memory) into
several (upto 8) isolated instances. Each of the partitioned memory needs
a dedicated NUMA node to operate. The partitions are not fi
usb_bus_find() is always used with argument -1; it can be replaced with
a search of the single USB bus on the machine.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
hw/ppc/sam460ex.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/sam460e
Once the Kconfig for hw/mips is cleaned up, it will be possible to build a
binary that does not include any USB host controller and therefore that
does not include the code guarded by CONFIG_USB. While the simpler
creation functions such as usb_create_simple can be inlined, this is not
true of usb
usb_bus_find() is always used with argument -1; it can be replaced with
a search of the single USB bus on the machine.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
hw/sh4/r2d.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/sh4/r2d.c b/hw/sh4/
object_resolve_type_unambiguous provides a useful functionality, that
is currently emulated for example by usb_bus_find(). Move it to core
code and add error reporting for increased generality.
Signed-off-by: Paolo Bonzini
---
include/qom/object.h | 13 +
hw/i386/acpi-build.c | 19 +
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
functions such as usb_create_simple can be inlined, this is not true
of usb_bus_find(). Remo
Inline the sole remaining use, which is for the -usbdevice command line.
Signed-off-by: Paolo Bonzini
---
include/hw/usb.h | 1 -
hw/usb/bus.c | 15 +--
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/include/hw/usb.h b/include/hw/usb.h
index cfeead28403..d46d9677
Split the sysbus version to a separate file so that it is not
included in PCI-only machines, and adjust Kconfig for machines
that do need sysbus-ohci. The copyrights are based on the
time and employer of balrog and Paul Brook's contributions.
While adjusting the SM501 dependency, move it to the r
Patches 1 to 3 start the removal of usb_bus_find() by replacing it
with object_resolve_type_unambiguous(), a function that is included
in the ACPI builder but should arguably be part of the core QOM API.
Because the only USB host controller must be the one created by the
machine init function itsel
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
functions such as usb_create_simple can be inlined, this is not true
of usb_bus_find(). Remo
With --without-default-devices it should not be required to have
devices in the binary that are removed by -nodefaults. It should be
therefore possible to build a binary that does not include any USB
host controller or any of the code guarded by CONFIG_USB. While the
simpler creation functions su
Because USB_EHCI_SYSBUS selects USB_EHCI, there is no need to include
hcd-ehci.c explicitly.
Signed-off-by: Paolo Bonzini
---
hw/usb/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
index 94f0e3b034d..aac3bb35f27 100644
--- a
Remove knowledge of specific MMU indexes (other than MMU_NESTED_IDX and
MMU_PHYS_IDX) from mmu_translate(). This will make it possible to split
32-bit and 64-bit MMU indexes.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h| 10 ++
target/i386/tcg/sysemu/excp_helpe
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory a
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory a
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates",
MSR_VM_HSAVE_PA bits 0-11 are reserved, as are the bits above the
maximum physical address width of the processor. Setting them to
1 causes a #GP (see "15.30.4 VM_HSAVE_PA MSR" in the AMD manual).
The same is true of VMCB addresses passed to VMRUN/VMLOAD/VMSAVE,
even though the manual is not clea
Accesses from a 32-bit environment (32-bit code segment for instruction
accesses, EFER.LMA==0 for processor accesses) have to mask away the
upper 32 bits of the address. While a bit wasteful, the easiest way
to do so is to use separate MMU indexes. These days, QEMU anyway is
compiled with a fixed
CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level
paging or PAE paging). Do this in mmu_translate() to remove
the last case where get_physical_address() meaningfully drops
the high bits of the address.
Suggested-by: Richard Henderson
Fixes: 4a1e9d4d11c ("target/i386: Use atomic op
If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already
applied in get_physical_address(), which is called via probe_access_full()
and x86_cpu_tlb_fill().
If ptw_translate() on the other hand does a MMU_NESTED_IDX access,
the A20 mask must not be applied to the address that is looke
On 2024-02-22 오전 3:16, nifan@gmail.com wrote:
From: Fan Ni
Per CXL spec 3.1, two mailbox commands are implemented:
Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 2
On 2024-02-22 오전 3:16, nifan@gmail.com wrote:
From: Fan Ni
Add dynamic capacity extent list representative to the definition of
CXLType3Dev and add get DC extent list mailbox command per
CXL.spec.3.1:.8.2.9.9.9.2.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 71 ++
On 2024-02-22 오전 3:16, nifan@gmail.com wrote:
From: Fan Ni
Since fabric manager emulation is not supported yet, the change implements
the functions to add/release dynamic capacity extents as QMP interfaces.
Note: we skips any FM issued extent release request if the exact extent
does not ex
On Thu, 22 Feb 2024 at 20:49, Richard Henderson
wrote:
>
> The following changes since commit 6630bc04bccadcf868165ad6bca5a964bb69b067:
>
> Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into
> staging (2024-02-22 12:42:52 +)
>
> are available in the Git repository at:
>
On 2/23/2024 1:01 AM, Philippe Mathieu-Daudé wrote:
> On 22/2/24 22:47, Steve Sistare wrote:
>> Generalize hmp_split_at_comma() to take any delimiter string, rename
>> as str_split(), and move it to util/strList.c.
>>
>> No functional change.
>>
>> Signed-off-by: Steve Sistare
>> ---
>> include/
On 2/23/24 03:59, Peter Xu wrote:
> On Tue, Feb 20, 2024 at 07:41:04PM -0300, Fabiano Rosas wrote:
>> Latest numbers
>> ==
>>
>> => guest: 128 GB RAM - 120 GB dirty - 1 vcpu in tight loop dirtying memory
>> => host: 128 CPU AMD EPYC 7543 - 2 NVMe disks in RAID0 (8586 MiB/s) - xfs
>> =>
Peter Xu writes:
> On Fri, Feb 16, 2024 at 02:35:26PM -0300, Fabiano Rosas wrote:
>> Cédric Le Goater writes:
>>
>> > Hello Fabiano
>> >
>> > On 2/14/24 21:35, Fabiano Rosas wrote:
>> >> Cédric Le Goater writes:
>> >>
>> >>> Hello Fabiano
>> >>>
>> >>> On 2/8/24 14:29, Fabiano Rosas wrote:
>>
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and
replace them with newly added public header to allow moving internal.h
into hw/ide to really stop exposing it.
Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files)
Signed-off-by: BALATON Zoltan
---
hw/arm/sbsa-r
Peter Xu writes:
> On Tue, Feb 20, 2024 at 07:41:04PM -0300, Fabiano Rosas wrote:
>> Latest numbers
>> ==
>>
>> => guest: 128 GB RAM - 120 GB dirty - 1 vcpu in tight loop dirtying memory
>> => host: 128 CPU AMD EPYC 7543 - 2 NVMe disks in RAID0 (8586 MiB/s) - xfs
>> => pinned vcpus w
On Mon, 19 Feb 2024 at 20:11, Arnaud Minier
wrote:
>
> Add the necessary files to add a simple RCC implementation with just
> reads from and writes to registers. Also instanciate the RCC in the
"instantiate"
> STM32L4x5_SoC. It is needed for accurate emulation of all the SoC
> clocks and timers.
Hao Xiang writes:
> On Wed, Feb 21, 2024 at 1:06 PM Fabiano Rosas wrote:
>>
>> Hao Xiang writes:
>>
>> > This change adds a dedicated handler for
>> > MigrationOps::ram_save_target_page in
>>
>> nit: Add a dedicated handler...
>>
>> Usually "this patch/change" is used only when necessary to av
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