On 2024/02/19 2:36, Michael S. Tsirkin wrote:
On Sun, Feb 18, 2024 at 01:56:07PM +0900, Akihiko Odaki wrote:
The guest may write NumVFs greater than TotalVFs and that can lead
to buffer overflow in VF implementations.
Cc: qemu-sta...@nongnu.org
Fixes: 7c0fa8dff811 ("pcie: Add support for Single
The following changes since commit da96ad4a6a2ef26c83b15fa95e7fceef5147269c:
Merge tag 'hw-misc-20240215' of https://github.com/philmd/qemu into staging
(2024-02-16 11:05:14 +)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.
Add test for POWER10.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index af104fff1c..a00202df3c 100644
-
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index de4c8805f7..61ba13dda
The powernv and pseries machines both provide hypervisor facilities
that are supported by KVM. This is a large and complicated set of
features that don't get much system-level testing in ppc tests.
Add a new test case for these which runs QEMU KVM inside the target.
This downloads an Alpine VM ima
From: Philippe Mathieu-Daudé
Commit 9fdf0c2995 ("Start implementing pSeries logical partition
machine") added hw/ppc/spapr_hcall.c, then commit 962104f044
("hw/ppc: moved hcalls that depend on softmmu") extracted the
system code to hw/ppc/spapr_softmmu.c. Take the license and
copyrights from the
is_prefix_insn_excp() loads the first word of the instruction address
which caused an exception, to determine whether or not it was prefixed
so the prefix bit can be set in [H]SRR1.
This works if the instruction image can be loaded, but if the exception
was caused by an ifetch, this load could fai
Use the default CPU with the pseries machine unless there is a
specific requirement.
Signed-off-by: Nicholas Piggin
---
tests/avocado/migration.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 09b62f813e..be6234b3c2 100644
--- a/
The expected MTD partition detection output does not always appear on
the console, despite the test reaching the boot loader and the string
appearing in dmesg. Possibly due to an init script that quietens the
console output. Using an earlier log message improves reliability.
Reviewed-by: Cédric Le
FreeBSD project provides qcow2 images that work well for testing QEMU.
Add pseries tests for HPT and Radix, KVM and TCG. This uses a short
term VM image, because FreeBSD has not set up long term builds for
ppc64 at present.
Other architectures could be added so this does not get a ppc_ prefix
but
From: Harsh Prateek Bora
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which can be further
reused as appropriate for correct interpretation.
Suggested-by: Ce
From: Peter Maydell
The raven_io_ops MemoryRegionOps is the only one in the source tree
which sets .valid.unaligned to indicate that it should support
unaligned accesses and which does not also set .impl.unaligned to
indicate that its read and write functions can do the unaligned
handling themsel
From: Glenn Miles
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 24 ++--
1 file changed, 22 insertions(+), 2 dele
From: Philippe Mathieu-Daudé
To reduce the use of the term 'softmmu', rename spapr_softmmu.c
to spapr_vhyp_mmu.c.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
[np: change name]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build
From: Glenn Miles
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6). This is used by hypervisor code to
control PCIe slot power during hotplug events.
Reviewed-by: Cédric Le Goater
Si
From: Saif Abrar
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar
Signed-off-by: Nicholas Piggi
POWER CPUs support hash and radix MMU modes. Linux supports running in
either mode, but defaults to radix. To keep up testing of QEMU's hash
MMU implementation, add some Linux hash boot tests.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_powernv.py | 23 +++
tests/avo
From: Glenn Miles
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Co
From: Glenn Miles
Allow external devices to drive pca9552 input pins by adding
input GPIO's to the model. This allows a device to connect
its output GPIO's to the pca9552 input GPIO's.
In order for an external device to set the state of a pca9552
pin, the pin must first be configured for high i
From: Cédric Le Goater
pseries machines before version 2.11 have undergone many changes to
correct issues, mostly regarding migration compatibility. This is
obfuscating the code uselessly and makes maintenance more difficult.
Remove them and only keep the last version of the 2.x series, 2.12,
sti
From: Glenn Miles
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good" signal asserted
on o
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 10 --
1 file changed, 8 insert
>From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB
and accessed with mftb instruction. The problem is that TB is the name
of the 64-bit register, and 32-bit implementations can only read the
lower half with one instruction, so 268 has also been called TBL and
it does only read T
The move to decodetree flipped the inequality test for the VEC / VSX
MSR facility check.
This caused application crashes under Linux, where these facility
unavailable interrupts are used for lazy-switching of VEC/VSX register
sets. Getting the incorrect interrupt would result in wrong registers
be
POWER10 is the latest IBM Power machine. Although it is not offered in
"OPAL mode" (i.e., powernv configuration), so there is a case that it
should remain at powernv9, most of the development work is going into
powernv10 at the moment.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
From: Philippe Mathieu-Daudé
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU
facilities to use the vhyp_mmu_ prefix rather than softmmu_.
vhyp_mmu_ is chosen because the code that manipulates the hash table
via guest software hypercalls is QEMU's implementation of the PAPR
hy
From: Harsh Prateek Bora
Initialize the machine specific max_cpus limit as per the maximum range
of CPU IPIs available. Keeping between 4096 to 8192 will throw IRQ not
free error due to XIVE/XICS limitation and keeping beyond 8192 will hit
assert in tcg_region_init or spapr_xive_claim_irq.
Logs:
BookE software TLB is implemented by flushing old translations from the
relevant TCG TLB whenever software TLB entries change. This means a new
software TLB entry should not have any corresponding cached TCG TLB
translations, so there is nothing to flush. The exception is multiple
software TLBs tha
From: Chalapathi V
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet mod
From: Glenn Miles
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present.
Reviewed-by: Cédr
From: Glenn Miles
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C
POWER10 is the latest pseries CPU.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0028ce0b67..b442d18317 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 2 +-
1
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.0
From: Chalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 15 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 17 ins
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 31 +++
1 file changed, 23 insertions(+)
From: Glenn Miles
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewed-by: Cédric Le Goate
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the TOD value to a SCOM address.
This implemen
This implements the core timebase state machine, which is the core side
of the time-of-day system in POWER processors. This facility is operated
by control fields in the TFMR register, which also contains status
fields.
The core timebase interacts with the chiptod hardware, primarily to
receive TO
From: Glenn Miles
The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins. A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage
The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER
(powernv) processors that keeps a time of day clock.
In particular for this model are facilities that initialise and start
the time of day clock, and that synchronise that clock to cores on the
chip, and to other chips. In thi
Several registers have names that don't match the ISA (or convention
with other QEMU PPC registers), making them unintuitive to use with
GDB.
Fortunately most of these registers are obscure and/or have not been
correctly implemented in the gdb server (e.g., DEC, TB, CFAR), so risk
of breaking user
Filter TLB flushing by PID and mmuidx.
Zoltan reports that, together with the previous TLB flush changes,
performance of a sam460ex machine running 'lame' to convert a wav to
mp3 is improved nearly 10%:
CPU timeTLB partial flushes TLB elided flushes
Before37s
Wire the ChipTOD model to powernv9 and powernv10 machines.
Suggested-by-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 30 ++
include/hw/ppc/pnv_chip.h | 3 +++
2 files changed, 33 insertions(+)
di
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 24 +---
1 file changed, 13 insertions(+), 11 delet
From: Chalapathi V
A POWER10 chip is divided into logical units called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers.
The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a
per-core register. Add the necessary SMT synchronisation and value
sharing.
The TFMR can only drive the timebase state machine via thread 0 of the
core, which is almost certainly not right, but it is enough for skiboot
and cert
The 440 tlbwe (write entry) instruction misses several cases that must
flush the TCG TLB:
- If the new size is smaller than the existing size, the EA no longer
covered should be flushed. This looks like an inverted inequality
test.
- If the TLB PID changes.
- If the TLB attr bit 0 (translation
From: Philippe Mathieu-Daudé
Check tcg_enabled() before calling softmmu_resize_hpt_prepare()
and softmmu_resize_hpt_commit() to allow the compiler to elide
their calls. The stubs are then unnecessary, remove them.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by
The ppc64 and s390x tests were first marked skipIf GITLAB_CI by commit
c0c8687ef0f ("tests/avocado: disable BootLinuxPPC64 test in CI"), and
commit 0f26d94ec9e ("tests/acceptance: skip s390x_ccw_vrtio_tcg on
GitLab") due to being very heavy-weight for gitlab CI.
Commit 9b45cc99318 ("docs/devel: ra
On 16/2/24 20:54, Philippe Mathieu-Daudé wrote:
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to set another qdev property (a link) for the pl110
and pl111 devices, we can not use sysbus_create_simple() which
only passes sysbus base address a
On 17/2/24 11:46, Bernhard Beschow wrote:
The interrupt handlers need to be populated before the device is realized since
internal devices such as the RTC are wired during realize(). If the interrupt
handlers aren't populated, devices such as the RTC will be wired with a NULL
interrupt handler, i
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
There's generally two modes of operation for IOMMUFD:
* The simple user API which intends to perform relatively simple things
with IOMMUs e.g. DPDK. It generally creates an IOAS and atta
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
Probe hardware dirty tracking support by querying device hw capabilities
via IOMMUFD_GET_HW_INFO.
In preparation to using the dirty tracking UAPI, request dirty tracking in
the HWPT flag
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
ioctl(iommufd, IOMMU_HWPT_SET_DIRTY_TRACKING, arg) is the UAPI that
enables or disables dirty page tracking.
It is called on the whole list of iommu domains it is are tracking,
and on fa
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
ioctl(iommufd, IOMMU_HWPT_GET_DIRTY_BITMAP, arg) is the UAPI
that fetches the bitmap that tells what was dirty in an IOVA
range.
A single bitmap is allocated and used across all the hwpt
Ping.
> Subject: RE: [PATCH] vhost_net: add NOTIFICATION_DATA and IN_ORDER
> feature bits to vdpa_feature_bits
>
> Hi Michael,
>
> Can you review this feature support patch, appreciate your review and
> comments.
>
> Patch considers all feature bits supported by vhost net client type as part of
On Tue, Jan 02, 2024 at 04:44:32PM +0530, Srujana Challa wrote:
> Enables VIRTIO_F_NOTIFICATION_DATA and VIRTIO_F_IN_ORDER feature bits
> for vhost vdpa backend. Also adds code to consider all feature bits
> supported by vhost net client type for feature negotiation, so that
> vhost backend device
Sorry this got tagged for Linux by mistake.
Replied now.
On Mon, Feb 19, 2024 at 09:38:46AM +, Srujana Challa wrote:
> Ping.
>
> > Subject: RE: [PATCH] vhost_net: add NOTIFICATION_DATA and IN_ORDER
> > feature bits to vdpa_feature_bits
> >
> > Hi Michael,
> >
> > Can you review this feature
On Sat, Feb 17, 2024 at 09:21:50AM -1000, Richard Henderson wrote:
> On 2/16/24 23:49, Alexander Monakov wrote:
> >
> > On Fri, 16 Feb 2024, Richard Henderson wrote:
> >
> > > Benchmark each acceleration function vs an aligned buffer of zeros.
> > >
> > > Signed-off-by: Richard Henderson
> > >
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
Allow disabling hugepages to be dirty track at base page
granularity in similar vein to vfio_type1_iommu.disable_hugepages
but per IOAS.
Signed-off-by: Joao Martins
---
backends/iommu
Hi Joao,
On 12/02/2024 15:56, Joao Martins wrote:
External email: Use caution opening links or attachments
By default VFIO migration is set to auto, which will support live
migration if the migration capability is set *and* also dirty page
tracking is supported.
For testing purposes one can f
The UEFI loading mode in loongarch is very different
from that in other architectures:loongarch's UEFI code
is in rom, while other architectures' UEFI code is in flash.
loongarch UEFI can be loaded as follows:
-machine virt,pflash=pflash0-format
-bios ./QEMU_EFI.fd
Other architectures load UEFI u
The UEFI loading mode in loongarch is very different
from that in other architectures:loongarch's UEFI code
is in rom, while other architectures' UEFI code is in flash.
loongarch UEFI can be loaded as follows:
-machine virt,pflash=pflash0-format
-bios ./QEMU_EFI.fd
Other architectures load UEFI u
On Thu, Feb 15, 2024 at 10:45 AM Albert Esteve wrote:
>
>
> On Tue, Feb 6, 2024 at 12:11 AM Alex Bennée
> wrote:
>
>> Albert Esteve writes:
>>
>> > Ensure that we cleanup all virtio shared
>> > resources when the vhost devices is cleaned
>> > up (after a hot unplug, or a crash).
>> >
>> > To do
qdev.c is a mixture between IDE bus specific functions and IDE device
functions. Let's split it up to make it more obvious which part is
related to bus handling and which part is related to device handling.
Signed-off-by: Thomas Huth
---
hw/ide/ide-bus.c | 111 +++
These definitions are required outside of the hw/ide/ code, too,
so lets's move them from internal.h to a new header called ide-dma.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dma.h | 30 ++
include/hw/ide/internal.h | 27 +--
2 files
Let's start to unentangle internal.h by moving public IDE device
related definitions to ide-dev.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dev.h | 145 +-
include/hw/ide/internal.h | 145 +-
hw/ide/ide-dev.c
Let's consolidate the public IDE bus related functions in a separate
header.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-bus.h | 41 +++
include/hw/ide/internal.h | 38 +---
2 files changed, 42 insertions(+), 37 deletions
While trying to make it possible to compile-out the CompactFlash IDE device
in downstream distributions (first patch), we noticed that there are more
things in the IDE code that could use a proper clean up:
First, hw/ide/qdev.c is quite a mix between IDE BUS specific functions
and (disk) device sp
在 2024/2/10 14:34, Dan Williams 写道:
Shiyang Ruan wrote:
The length of Physical Address in General Media Event Record/DRAM Event
Record is 64-bit, so the field mask should be defined as such length.
Can you include this user visible side-effect of this change. Looks like
this could cause usa
For distros like downstream RHEL, it would be helpful to allow to disable
the CompactFlash device. For making this possible, we need a separate
Kconfig switch for this device, and the code should reside in a separate
file. Let's also introduce a new header ide-dev.h which can be used to
collect def
There was only one prototype left in this legacy file. Move it to
ide-dev.h to finally get rid of it.
Signed-off-by: Thomas Huth
---
include/hw/ide.h | 9 -
include/hw/ide/ide-dev.h | 2 ++
include/hw/ide/internal.h | 1 -
3 files changed, 2 insertions(+), 10 deletions(-)
dele
include/hw/ide/internal.h is currently included by include/hw/ide/pci.h
and thus exposed to a lot of files that are not part of the IDE subsystem.
Stop including internal.h there and use the appropriate new headers
ide-bus.h and ide-dma.h instead.
Signed-off-by: Thomas Huth
---
include/hw/ide/pc
The OSPI DMA reads flash data through the OSPI linear address space (the
iomem_dac region), because of this the reentrancy guard introduced in
commit a2e1753b ("memory: prevent dma-reentracy issues") is disabled for
the memory region.
Signed-off-by: Sai Pavan Boddu
---
Changes for V2:
Add
If "configure" has been run with "--without-default-devices", there is
no e1000 device in the binaries, so the boot-serial-test currently fails
in that case since it tries to use the e1000 with the sam460ex machine.
Since we're testing the serial output here, and not the NIC, let's
simply switch t
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 16/2/24 20:54, Philippe Mathieu-Daudé wrote:
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to set another qdev property (a link) for the pl110
and pl111 devices, we can not use sysbus_cre
On 19/2/24 11:49, Thomas Huth wrote:
Let's start to unentangle internal.h by moving public IDE device
related definitions to ide-dev.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dev.h | 145 +-
include/hw/ide/internal.h | 145 +
On 19/2/24 11:49, Thomas Huth wrote:
While trying to make it possible to compile-out the CompactFlash IDE device
in downstream distributions (first patch), we noticed that there are more
things in the IDE code that could use a proper clean up:
First, hw/ide/qdev.c is quite a mix between IDE BUS
On Mon, 19 Feb 2024, Thomas Huth wrote:
If "configure" has been run with "--without-default-devices", there is
no e1000 device in the binaries, so the boot-serial-test currently fails
in that case since it tries to use the e1000 with the sam460ex machine.
Since we're testing the serial output he
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Monday, February 19, 2024 3:15 PM
> To: Srujana Challa
> Cc: qemu-devel@nongnu.org; Vamsi Krishna Attunuru
> ; Jerin Jacob ; Jason Wang
>
> Subject: [EXT] Re: [PATCH] vhost_net: add NOTIFICATION_DATA and
> IN_ORDER feature bits t
On Mon, 19 Feb 2024, Thomas Huth wrote:
qdev.c is a mixture between IDE bus specific functions and IDE device
functions. Let's split it up to make it more obvious which part is
related to bus handling and which part is related to device handling.
Signed-off-by: Thomas Huth
---
hw/ide/ide-bus.c
On 19/2/24 12:27, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 16/2/24 20:54, Philippe Mathieu-Daudé wrote:
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to set another qdev property (a link) for the pl110
and
On Thu, 31 Aug 2023 at 11:32, Ayan Kumar Halder wrote:
> On 31/08/2023 11:03, Peter Maydell wrote:
> > On Thu, 31 Aug 2023 at 10:53, Alex Bennée wrote:
> >> Peter Maydell writes:
> >>> On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini
> >>> wrote:
> As Xen is gaining R52 and R82 support, i
On Mon, 19 Feb 2024, Thomas Huth wrote:
These definitions are required outside of the hw/ide/ code, too,
so lets's move them from internal.h to a new header called ide-dma.h.
Signed-off-by: Thomas Huth
---
include/hw/ide/ide-dma.h | 30 ++
include/hw/ide/internal.h |
On 07/02/2024 01.54, pet...@redhat.com wrote:
From: Peter Xu
Recently we introduced cross-binary migration test. It's always wanted
that migration-test uses stable guest ABI for both QEMU binaries in this
case, so that both QEMU binaries will be compatible on the migration
stream with the cmdl
I apologize for the delayed review.
Sam Li writes:
> To configure the zoned format feature on the qcow2 driver, it
> requires settings as: the device size, zone model, zone size,
> zone capacity, number of conventional zones, limits on zone
> resources (max append bytes, max open zones, and max_
On Fri, Feb 16, 2024 at 12:02:55PM +0100, Philippe Mathieu-Daudé wrote:
> Prefer QDev API for QDev objects, avoid the underlying QOM layer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/tricore/tricore_testdevice.h | 3 ---
> hw/tricore/tricore_testboard.c | 4 +---
> 2 f
On Feb 18 13:56, Akihiko Odaki wrote:
> nvme_sriov_pre_write_ctrl() used to directly inspect SR-IOV
> configurations to know the number of VFs being disabled due to SR-IOV
> configuration writes, but the logic was flawed and resulted in
> out-of-bound memory access.
>
> It assumed PCI_SRIOV_NUM_VF
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 19/2/24 12:27, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 16/2/24 20:54, Philippe Mathieu-Daudé wrote:
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, Philippe Mathieu-Daudé wrote:
We want to
One more thing...
Markus Armbruster writes:
> I apologize for the delayed review.
>
> Sam Li writes:
>
>> To configure the zoned format feature on the qcow2 driver, it
>> requires settings as: the device size, zone model, zone size,
>> zone capacity, number of conventional zones, limits on zone
On Mon, Feb 19, 2024 at 11:45 AM Albert Esteve wrote:
>
>
>
> On Thu, Feb 15, 2024 at 10:45 AM Albert Esteve wrote:
>
>>
>>
>> On Tue, Feb 6, 2024 at 12:11 AM Alex Bennée
>> wrote:
>>
>>> Albert Esteve writes:
>>>
>>> > Ensure that we cleanup all virtio shared
>>> > resources when the vhost de
On Thu, 15 Feb 2024 09:30:27 -1000
Richard Henderson wrote:
> On 2/15/24 05:01, Jonathan Cameron wrote:
> > On i386, after fixing the page walking code to work with pages in
> > MMIO memory (specifically CXL emulated interleaved memory),
> > a crash was seen in an interrupt handling path.
> >
>
Markus Armbruster 于2024年2月19日周一 13:05写道：
>
> One more thing...
>
> Markus Armbruster writes:
>
> > I apologize for the delayed review.
No problems. Thanks for reviewing!
> >
> > Sam Li writes:
> >
> >> To configure the zoned format feature on the qcow2 driver, it
> >> requires settings as: the
On 19/02/2024 12.37, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Thomas Huth wrote:
If "configure" has been run with "--without-default-devices", there is
no e1000 device in the binaries, so the boot-serial-test currently fails
in that case since it tries to use the e1000 with the sam460ex machin
On 19/2/24 13:00, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 19/2/24 12:27, BALATON Zoltan wrote:
On Mon, 19 Feb 2024, Philippe Mathieu-Daudé wrote:
On 16/2/24 20:54, Philippe Mathieu-Daudé wrote:
On 16/2/24 18:14, BALATON Zoltan wrote:
On Fri, 16 Feb 2024, P
Xiaoyao Li writes:
> Introduce tdx-guest object which implements the interface of
> CONFIDENTIAL_GUEST_SUPPORT, and will be used to create TDX VMs (TDs) by
>
> qemu -machine ...,confidential-guest-support=tdx0 \
>-object tdx-guest,id=tdx0
>
> It has only one member 'attributes' with f
When compiling with "configure --without-default-devices", the
dbus-display-test fails since it implicitly assumes that the
machine comes with the standard VGA card. Thus add a check to
meson.build to disable the test if the VGA card is not available.
Signed-off-by: Thomas Huth
---
tests/qtest/m
Hello Volker, thanks for working on this,
On Sun, 18 Feb 2024 at 10:33, Volker Rümelin wrote:
>
> A malicious guest may trigger a segmentation fault in the tx/rx xfer
> handlers. On handler entry the stream variable is initialized with
> NULL. If the first element of the virtio queue has an inval
On Mon, Feb 19, 2024 at 01:34:37PM +0100, Markus Armbruster wrote:
> Xiaoyao Li writes:
>
> > Introduce tdx-guest object which implements the interface of
> > CONFIDENTIAL_GUEST_SUPPORT, and will be used to create TDX VMs (TDs) by
> >
> > qemu -machine ...,confidential-guest-support=tdx0 \
> >
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