From: Helge Deller
For debugging purposes at the early stage of the bootup process,
the SeaBIOS-hppa firmware sometimes needs to output characters to the
serial console. Note that the serial console is the default output
method for parisc machines.
At this stage PCI busses and other devices have
From: Helge Deller
The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into
staging (2024-02-03 13:31:58 +)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git tags
From: Helge Deller
Add disassembly of opcodes for "HALT QEMU", "RESET QEMU" and
"RESTORE SHR" (restore shadow registers).
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
disas/hppa.c | 4
1 file changed, 4 insertions(+)
diff --git a/disas/hppa.c b/disas/hppa.c
index cce4f
From: Helge Deller
The Astro/Elroy chip can work in either Hard-Fail or Soft-Fail mode.
Hard fail means the system bus will send an HPMC (=crash) to the
processor, soft fail means the system bus will ignore timeouts of
MMIO-reads or MMIO-writes and return -1ULL.
The HF mode is controlled by a b
From: Helge Deller
HP-UX 11 and HP ODE tools use the "rsm 0,%reg" instruction in not priviledged
code paths to get the current PSW flags. The constant 0 means that no bits of
the PSW shall be reset, so this is effectively a read-only access to the PSW.
Allow this read-only access even for not pri
From: Helge Deller
Add the do_transaction_failed() handler to tigger a HPMC to the CPU
in case of I/O transaction errors.
This is a preparation commit.
We still lack implementation for some registers, so do not yet enable sending
HPMCs. Having this hunk here now nevertheless helps for the furth
From: Helge Deller
The BTLB helper function stores the BTLB info (four 32-bit ints) into
the memory of the guest. They are only available when emulating a 32-bit
CPU in the guest, so use "uint32_t" instead of "target_ulong" here.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
From: Helge Deller
Linux writes zeroes at bootup into the default ports for LASI audio and
LASI floppy controller to reset those devices. Allow writing to those
registers to avoid HPMCs.
Signed-off-by: Helge Deller
---
hw/misc/lasi.c | 11 +++
include/hw/misc/lasi.h | 2 ++
2
From: Helge Deller
Firmware and qemu reads and writes the MAC address for the LASI LAN via
registers in LASI. Allow those accesses and return zero even if LASI
LAN isn't enabled to avoid HPMCs (=crashes).
Signed-off-by: Helge Deller
---
hw/misc/lasi.c | 2 ++
1 file changed, 2 insertions(+)
d
From: Helge Deller
Instead of stopping the emulation, report a MEMTX_DECODE_ERROR if the OS
tries to access non-existent registers.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
---
hw/pci-host/astro.c | 27 +++
1 file changed, 11 insertions(+), 16 deletio
From: Helge Deller
Load the 64-bit SeaBIOS-hppa firmware by default when running on a 64-bit
machine. This will enable us to later support more than 4GB of RAM and is
required that the OS (or PALO bootloader) will start or install a 64-bit kernel
instead of a 32-bit kernel.
Note that SeaBIOS-hpp
From: Sven Schnelle
Netbsd isn't able to detect a link on the emulated tulip card. That's
because netbsd reads the Chip Status Register of the Phy (address
0x14). The default phy data in the qemu tulip driver is all zero,
which means no link is established and autonegotation isn't complete.
Ther
On 2/11/24 04:41, Richard Henderson wrote:
On 2/6/24 19:59, Pierrick Bouvier wrote:
Why a hash table? All you want is to be able to iterate through all, and
add/remove
easily. Seems like QLIST from would be better, and the
QLIST_ENTRY member
would make struct qemu_plugin_scoreboard useful.
11.02.2024 15:29, del...@kernel.org пишет:
From: Helge Deller
SeaBIOS-hppa version 16 news & enhancements:
- Initial 64-bit firmware release
- Added fault handler to catch and report firmware bugs
- Use Qemu's builtin_console_out() via diag 0x101
- parisc-qemu-install Makefile target to instal
11.02.2024 15:29, del...@kernel.org
From: Helge Deller
SeaBIOS-hppa version 16 news & enhancements:
pc-bios/hppa-firmware.img | Bin 163324 -> 167820 bytes
pc-bios/hppa-firmware64.img | Bin 0 -> 206024 bytes
roms/seabios-hppa | 2 +-
3 files changed, 1 insertion(+), 1 del
On 2/11/24 04:26, Pierrick Bouvier wrote:
On 2/11/24 04:41, Richard Henderson wrote:
On 2/6/24 19:59, Pierrick Bouvier wrote:
Why a hash table? All you want is to be able to iterate through all, and
add/remove
easily. Seems like QLIST from would be better, and the
QLIST_ENTRY member
would
On spapr, the max number of CPU IPIs are 4096 which is accounted during
spapr_irq_init but currently existing macro SPAPR_XIRQ_BASE is being
used to refer to that. Introducing SPAPR_IRQ_NR_IPIS to refer to the
range
of CPU IPIS which is being further used to initialize mc->max_cpus
during spapr_mac
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which can be further
reused as appropriate for correct interpretation.
Suggested-by: Cedric Le Goater
Tested-by:
Initialize the machine specific max_cpus limit as per the maximum range
of CPU IPIs available. Keeping between 4096 to 8192 will throw IRQ not
free error due to XIVE/XICS limitation and keeping beyond 8192 will hit
assert in tcg_region_init or spapr_xive_claim_irq.
Logs:
Without patch fix:
[root
On spapr, the max number of CPU IPIs are 4096 which is accounted during
spapr_irq_init but currently existing macro SPAPR_XIRQ_BASE is being
used to refer to that. Introducing SPAPR_IRQ_NR_IPIS to refer to the
range
of CPU IPIS which is being further used to initialize mc->max_cpus
during spapr_mac
spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to
the range of CPU IPIs during initialization of nr-irqs property.
It is more appropriate to have its own define which can be further
reused as appropriate for correct interpretation.
Suggested-by: Cedric Le Goater
Tested-by:
Initialize the machine specific max_cpus limit as per the maximum range
of CPU IPIs available. Keeping between 4096 to 8192 will throw IRQ not
free error due to XIVE/XICS limitation and keeping beyond 8192 will hit
assert in tcg_region_init or spapr_xive_claim_irq.
Logs:
Without patch fix:
[root
+ Daniel, Cedric, Richard - for review comments, if any.
On 2/9/24 17:05, Chinmay Rath wrote:
This patch moves the below instructions to decodetree specification:
{add, subf}[c,e,me,ze][o][.] : XO-form
addic[.], subfic : D-form
addex
On 2/11/24 23:13, Richard Henderson wrote:
On 2/11/24 04:26, Pierrick Bouvier wrote:
On 2/11/24 04:41, Richard Henderson wrote:
On 2/6/24 19:59, Pierrick Bouvier wrote:
Why a hash table? All you want is to be able to iterate through all, and
add/remove
easily. Seems like QLIST from would b
On 10/2/24 09:54, Michael Tokarev wrote:
09.02.2024 22:01, Philippe Mathieu-Daudé:
Replace '24' -> KVM_IOAPIC_NUM_PINS.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/kvm/ioapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapi
Currently, virtio_pci_queue_mem_mult function returns 4K when
VIRTIO_PCI_FLAG_PAGE_PER_VQ is set. But this is not correct
when host has page size as 64K.
This patch fixes the same.
Signed-off-by: Srujana Challa
---
hw/virtio/virtio-pci.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
> On 31-Jan-2024, at 17:24, Gerd Hoffmann wrote:
>
> On Wed, Jan 31, 2024 at 08:19:06AM +0530, Ani Sinha wrote:
>
>> This error exists only with edk2. Seabios currently can boot a linux guest
>> fine with 4096 vcpus. Since the lowest common denominator for a working VM
>> for
>> both edk2 an
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