On Tue, Feb 06, 2024 at 02:31:51PM +0800, pet...@redhat.com wrote:
> From: Peter Xu
>
> It turns out that we may not be able to enable this test even for the
> upcoming v9.0. Document what we're still missing.
>
> Signed-off-by: Peter Xu
> ---
> .gitlab-ci.d/buildtest.yml | 7 ---
> 1 fil
On Tue, Feb 06, 2024 at 02:31:50PM +0800, pet...@redhat.com wrote:
> From: Peter Xu
>
> The new build-previous-qemu job relies on QEMU release tag being present,
> while that may not be always true for personal git repositories since by
> default tag is not pushed. The job can fail on those CI k
On Tue, Feb 06, 2024 at 02:31:49PM +0800, pet...@redhat.com wrote:
> From: Peter Xu
>
> Recently we introduced cross-binary migration test. It's always wanted
> that migration-test uses stable guest ABI for both QEMU binaries in this
> case, so that both QEMU binaries will be compatible on the m
This series is inspired and suggested by Daniel:
https://lore.kernel.org/qemu-devel/zbfoqseuv6_zw...@redhat.com/
Currently, different confidential VMs in different architectures have
their own specific *_kvm_init() (and some have *_kvm_reset()) exposed
for KVM stuff when it's a confidential VM. e.
Use confidential_guest_kvm_init() instead of calling SEV specific
sev_kvm_init(). As a bouns, it fits to future TDX when TDX implements
its own confidential_guest_support and .kvm_init().
Move the "TypeInfo sev_guest_info" definition and related functions to
the end of the file, to avoid declaring
Use the unified interface to call confidential guest related kvm_init()
and kvm_reset(), to avoid exposing pef specific functions.
remove perf.h since it is now blank..
Signed-off-by: Xiaoyao Li
---
hw/ppc/pef.c | 9 ++---
hw/ppc/spapr.c | 6 +++---
include/hw/ppc/pef.h | 17
Use unified confidential_guest_kvm_init(), to avoid exposing specific
functions.
Signed-off-by: Xiaoyao Li
---
hw/s390x/s390-virtio-ccw.c | 3 ++-
target/s390x/kvm/pv.c | 8
target/s390x/kvm/pv.h | 14 --
3 files changed, 10 insertions(+), 15 deletions(-)
diff -
Different confidential VMs in different architectures all have the same
needs to do their specific initialization (and maybe resetting) stuffs
with KVM. Currently each of them exposes individual *_kvm_init()
functions and let machine code or kvm code to call it.
To make it more object oriented, ad
On Tue, Feb 06, 2024 at 08:11:58AM +, Daniel P. Berrangé wrote:
> On Tue, Feb 06, 2024 at 02:31:50PM +0800, pet...@redhat.com wrote:
> > From: Peter Xu
> >
> > The new build-previous-qemu job relies on QEMU release tag being present,
> > while that may not be always true for personal git repo
On Tue, Feb 06, 2024 at 10:47:40AM +0800, Jason Wang wrote:
On Mon, Feb 5, 2024 at 6:51 PM Stefano Garzarella wrote:
On Fri, Feb 02, 2024 at 02:25:21PM +0100, Kevin Wolf wrote:
>VDUSE requires that virtqueues are first enabled before the DRIVER_OK
>status flag is set; with the current API of t
On 2024/02/05 18:31, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/03 22:58, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/03 20:08, Alex Bennée wrote:
Akihiko Odaki writes:
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/
On 05/02/2024 21.54, Ilya Leoshkevich wrote:
Convert to Binary - counterparts of the already implemented Convert
to Decimal (CVD*) instructions.
Example from the Principles of Operation: 25594C becomes 63FA.
Co-developed-by: Pavel Zbitskiy
Signed-off-by: Ilya Leoshkevich
---
target/s390x/hel
On Mon, Feb 05, 2024 at 04:49:24PM -0300, Fabiano Rosas wrote:
> We're currently leaking the resources of the TLS thread by not joining
> it and also overwriting the p->thread pointer altogether.
AFAICS, it is not ovewriting 'p->thread' because at the time when the
TLS thread is created, the main
On 06/02/2024 01.22, Ilya Leoshkevich wrote:
make vm-build-freebsd fails with:
ld: error: undefined symbol: inotify_init1
>>> referenced by filemonitor-inotify.c:183
(../src/util/filemonitor-inotify.c:183)
>>> util_filemonitor-inotify.c.o:(qemu_file_monitor_new) in
On Tue, Feb 06, 2024 at 08:53:45AM +, Daniel P. Berrangé wrote:
> AFAICS, it is not ovewriting 'p->thread' because at the time when the
> TLS thread is created, the main 'send thread' has not yet been
> created. The TLS thread and send thread execution times are mutually
> exclusive.
IIUC it'l
On 06/02/2024 03.29, maobibo wrote:
Hi Philippe,
On 2024/2/5 下午8:58, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 5/2/24 03:13, Bibo Mao wrote:
The cdrom test skips to execute on LoongArch system with command
"make check", this patch enables cdrom test for LoongArch virt
machine platform.
With
This ensures we run during a cpu_exec, which allows to call start/end
exclusive from this init hook (needed for new scoreboard API introduced
later).
async work is run before any tb is translated/executed, so we can
guarantee plugin init will be called before any other hook.
The previous change m
We found that vcpu_init_hook was called *after* idle callback.
vcpu_init is called from cpu_realize_fn, while idle/resume cb are called
from qemu_wait_io_event (in vcpu thread).
This change ensures we only call idle and resume cb only once a plugin
was init for a given vcpu.
Next change in the se
This series adds a new thread-safe API to declare inline operation
inside plugins. As well, it removes the existing non thread-safe API,
and migrates all existing plugins to use it.
Tested on Linux (user, system) for i386, x86_64 and aarch64.
To give some context, this a long term series of work
Instead of working on a fixed memory location, allow to address it based
on cpu_index, an element size and a given offset.
Result address: ptr + offset + cpu_index * element_size.
With this, we can target a member in a struct array from a base pointer.
Current semantic is not modified, thus inlin
We now keep track of how many vcpus were started. This way, a plugin can
easily query number of any vcpus at any point of execution, which
unifies user and system mode workflows.
Signed-off-by: Pierrick Bouvier
---
include/qemu/qemu-plugin.h | 3 +++
plugins/plugin.h | 4
plug
Extends API with three new functions:
qemu_plugin_register_vcpu_{tb, insn, mem}_exec_inline_per_vcpu().
Those functions takes a qemu_plugin_u64_t as input.
This allows to have a thread-safe and type-safe version of inline
operations.
Reviewed-by: Alex Bennée
Signed-off-by: Pierrick Bouvier
---
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/hotblocks.c | 50 ++---
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/hotblocks.c
index 4de1b134944..02bc5078bdd 100644
--- a/contrib/plugins/hotbloc
We introduce a cpu local storage, automatically managed (and extended)
by QEMU itself. Plugin allocate a scoreboard, and don't have to deal
with how many cpus are launched.
This API will be used by new inline functions but callbacks can benefit
from this as well. This way, they can operate without
Signed-off-by: Pierrick Bouvier
---
tests/plugin/bb.c | 63 +++
1 file changed, 26 insertions(+), 37 deletions(-)
diff --git a/tests/plugin/bb.c b/tests/plugin/bb.c
index df50d1fd3bc..36776dee1e1 100644
--- a/tests/plugin/bb.c
+++ b/tests/plugin/bb.c
@
When scoreboards need to be reallocated.
Signed-off-by: Pierrick Bouvier
---
docs/devel/multi-thread-tcg.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
index 7302c3bf534..1420789fff3 100644
--- a/docs/devel/multi-thread-t
Signed-off-by: Pierrick Bouvier
---
contrib/plugins/howvec.c | 53
1 file changed, 38 insertions(+), 15 deletions(-)
diff --git a/contrib/plugins/howvec.c b/contrib/plugins/howvec.c
index 644a7856bb2..2d10c87e0fb 100644
--- a/contrib/plugins/howvec.c
+++
Signed-off-by: Pierrick Bouvier
---
plugins/plugin.h | 5 -
accel/tcg/plugin-gen.c | 13 -
plugins/core.c | 29 -
3 files changed, 8 insertions(+), 39 deletions(-)
diff --git a/plugins/plugin.h b/plugins/plugin.h
index 8e485cfbd58..ba52a
Signed-off-by: Pierrick Bouvier
---
tests/plugin/insn.c | 106 +---
1 file changed, 50 insertions(+), 56 deletions(-)
diff --git a/tests/plugin/insn.c b/tests/plugin/insn.c
index 5fd3017c2b3..0d0a4cd1c34 100644
--- a/tests/plugin/insn.c
+++ b/tests/plugin/
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Pierrick Bouvier
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dfaca8323e9..80528d3dc63 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3676,6 +3676,7 @@ TCG Plugins
Signed-off-by: Pierrick Bouvier
---
tests/plugin/mem.c | 40 +---
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/tests/plugin/mem.c b/tests/plugin/mem.c
index 44e91065ba7..d4729f5e015 100644
--- a/tests/plugin/mem.c
+++ b/tests/plugin/mem.c
@@
For now, it simply performs instruction, bb and mem count, and ensure
that inline vs callback versions have the same result. Later, we'll
extend it when new inline operations are added.
Use existing plugins to test everything works is a bit cumbersome, as
different events are treated in different
Now we have a thread-safe equivalent of inline operation, and that all
plugins were changed to use it, there is no point to keep the old API.
In more, it will help when we implement more functionality (conditional
callbacks), as we can assume that we operate on a scoreboard.
Bump API version as i
This information is already accessible using qemu_info_t during plugin
install.
We will introduce another function (qemu_plugin_num_vcpus) which
represent how many cpus were enabled, by tracking new cpu indexes.
It's a breaking change, so we bump API version.
Signed-off-by: Pierrick Bouvier
---
Hi Daniel,
On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote:
>
> Hi Daniel,
>
> On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 2/5/24 04:00, Alexandre Ghiti wrote:
> > > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > > when it
On Thu, Jan 25, 2024 at 06:25:11PM +0200, Avihai Horon wrote:
> Hello,
>
> Today there are several types of migration channels that can be used
> during migration: main migration channel, multifd channels and postcopy
> preempt channel. Each channel type has its own code to connect and to
> TLS up
On Tue, Feb 06, 2024 at 05:15:07PM +0800, Peter Xu wrote:
> On Tue, Feb 06, 2024 at 08:53:45AM +, Daniel P. Berrangé wrote:
> > AFAICS, it is not ovewriting 'p->thread' because at the time when the
> > TLS thread is created, the main 'send thread' has not yet been
> > created. The TLS thread an
On Tue, Jan 30, 2024 at 08:44:19PM +0200, Avihai Horon wrote:
>
> On 30/01/2024 7:57, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, Jan 29, 2024 at 02:20:35PM +0200, Avihai Horon wrote:
> > > On 29/01/2024 6:17, Peter Xu wrote:
> > > > External
From: Ilya Leoshkevich
make vm-build-freebsd sometimes fails with "Connection timed out during
banner exchange". The client strace shows:
13:59:30 write(3, "SSH-2.0-OpenSSH_9.3\r\n", 21) = 21
13:59:30 getpid() = 252655
13:59:30 poll([{fd=3, events=POLLIN}], 1, 5
From: Sven Schnelle
When the maximum count of SCRIPTS instructions is reached, the code
stops execution and returns, but fails to decrement the reentrancy
counter. This effectively renders the SCSI controller unusable
because on next entry the reentrancy counter is still above the limit.
This bu
From: Ilya Leoshkevich
Unlike on Linux, on FreeBSD renaming a file when the destination
already exists results in an IN_DELETE event for that existing file:
$ FILEMONITOR_DEBUG=1 build/tests/unit/test-util-filemonitor
Rename /tmp/test-util-filemonitor-K13LI2/fish/one.txt ->
/tmp/test-ut
From: Ilya Leoshkevich
Check the CVD's, CVDY's, and CVDG's corner cases.
Reviewed-by: Thomas Huth
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240205205830.6425-4-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/cvd.c | 63 +
tests
From: Ilya Leoshkevich
Convert to Binary - counterparts of the already implemented Convert
to Decimal (CVD*) instructions.
Example from the Principles of Operation: 25594C becomes 63FA.
Co-developed-by: Pavel Zbitskiy
Signed-off-by: Ilya Leoshkevich
Reviewed-by: Thomas Huth
Message-ID: <20240
From: Philippe Mathieu-Daudé
Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Thomas Huth
Message-ID: <20240129164514.73104-25-phi...@linaro.org>
Sign
From: Ilya Leoshkevich
Check the CVB's, CVBY's, and CVBG's corner cases.
Co-developed-by: Pavel Zbitskiy
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240205205830.6425-5-...@linux.ibm.com>
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/cvb.
From: Ilya Leoshkevich
CVDG is the same as CVD, except that it converts 64 bits into 128,
rather than 32 into 64. Create a new helper, which uses Int128
wrappers.
Reported-by: Ido Plat
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240205205830.6425-2-...@linux.
The character "+" is now forbidden in QOM device names (see commit
b447378e1217 - "Limit type names to alphanumerical and some few special
characters"). For the "power5+" and "power7+" CPU names, there is
currently a hack in type_name_is_valid() to still allow them for
compatibility reasons. Howeve
From: Ilya Leoshkevich
After console_sshd_config(), the SSH server needs to be nudged to pick
up the new configs. The scripts for the other BSD flavors already do
this with a reboot, but a simple reload is sufficient.
Reviewed-by: Thomas Huth
Signed-off-by: Ilya Leoshkevich
Message-ID: <202402
The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into
staging (2024-02-03 13:31:58 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2024-02-06
fo
For consistency we should drop the names with a "+" in it in the
long run.
Message-ID: <20240117141054.73841-3-th...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Thomas Huth
---
docs/about/deprecated.rst | 9 +
From: Ilya Leoshkevich
make vm-build-freebsd fails with:
ld: error: undefined symbol: inotify_init1
>>> referenced by filemonitor-inotify.c:183
(../src/util/filemonitor-inotify.c:183)
>>> util_filemonitor-inotify.c.o:(qemu_file_monitor_new) in
archive libqemuutil.a
O
Hi Michael
On Sat, Feb 3, 2024 at 5:41 PM Michael Tokarev wrote:
>
> Doing a build of just a single target with --enable modules results in build
> error:
>
>
> rm -rf b; cd b
> ../configure --enable-modules --target-list=x86_64-softmmu
> ninja qemu-system-x86_64
>
>In file included fro
On 5/2/24 20:47, Sven Schnelle wrote:
Netbsd isn't able to detect a link on the emulated tulip card. That's
because netbsd reads the Chip Status Register of the Phy (address
0x14). The default phy data in the qemu tulip driver is all zero,
which means no link is established and autonegotation isn
On 2/6/24 06:41, Alexandre Ghiti wrote:
Hi Daniel,
On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote:
Hi Daniel,
On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
wrote:
On 2/5/24 04:00, Alexandre Ghiti wrote:
Currently, the initrd is placed at 128MB, which overlaps with the
On 05/02/2024 21:49, Fabiano Rosas wrote:
External email: Use caution opening links or attachments
During multifd channel creation (multifd_send_new_channel_async) when
TLS is enabled, the multifd_channel_connect function is called twice,
once to create the TLS handshake thread and another ti
On 06/02/2024 12:04, Peter Xu wrote:
External email: Use caution opening links or attachments
On Thu, Jan 25, 2024 at 06:25:11PM +0200, Avihai Horon wrote:
Hello,
Today there are several types of migration channels that can be used
during migration: main migration channel, multifd channels
The original implementation sets $pc to the address read from the jump
vector table first and links $ra with the address of the next instruction
after the updated $pc. After jumping to the updated $pc and executing the
next ret instruction, the program jumps to $ra, which is in the same
function cu
This changes the ohci validation to not assert if invalid
data is fed to the ohci controller. The poc suggested in
https://bugs.launchpad.net/qemu/+bug/1907042
migrated to #303 does the following to feed it a
SETUP pid and EndPt of 1:
uint32_t MaxPacket = 64;
uint32_t TDFormat = 0;
This changes the ohci validation to not assert if invalid
data is fed to the ohci controller. The poc suggested in
https://bugs.launchpad.net/qemu/+bug/1907042
and then migrated to bug #303 does the following to
feed it a SETUP pid and EndPt of 1:
uint32_t MaxPacket = 64;
uint32_t
Attempting to resend with both files in the patch this time:
This changes the ohci validation to not assert if invalid
data is fed to the ohci controller. The poc suggested in
https://bugs.launchpad.net/qemu/+bug/1907042
migrated to #303 does the following to feed it a
SETUP pid and EndPt of 1:
Add the Cortex-R52 IMPDEF sysregs, by defining them here and
also by enabling the AUXCR feature which defines the ACTLR
and HACTLR registers. As is our usual practice, we make these
simple reads-as-zero stubs for now.
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu32.c | 108
We currently guard the CFG3 register read with
(scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
which is clearly wrong as it is never true.
This register is present on all board types except AN524
and AN527; correct the condition.
Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes f
The AN536 is another FPGA image for the MPS3 development board. Unlike
the existing FPGA images we already model, this board uses a Cortex-R
family CPU, and it does not use any equivalent to the M-profile
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
It's therefore more
Add documentation for the mps3-an536 board type.
Signed-off-by: Peter Maydell
---
docs/system/arm/mps2.rst | 37 ++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index 8a75beb3a08..a305935cc49
Architecturally, the AArch32 MSR/MRS to/from banked register
instructions are UNPREDICTABLE for attempts to access a banked
register that the guest could access in a more direct way (e.g.
using this insn to access r8_fiq when already in FIQ mode). QEMU has
chosen to UNDEF on all of these.
However
The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.
Signed-off-by: Peter Maydell
---
target/arm/tcg/cpu32.c | 1 +
1 file c
The MPS2 SCC device is broadly the same for all FPGA images, but has
minor differences in the behaviour of the CFG registers depending on
the image. In many cases we don't really care about the functionality
controlled by these registers and a reads-as-written or similar
behaviour is sufficient for
Create the CPUs, the GIC, and the per-CPU RAM block for
the mps3-an536 board.
Signed-off-by: Peter Maydell
---
Some parts of this might need to end up parameterisable if/when
we add another machine type to this source file, but rather than
trying to guess which parts, I stuck with the simple code
The MPS SCC device has a lot of different flavours for the various
different MPS FPGA images, which look mostly similar but have
differences in how particular registers are handled. Currently we
deal with this with a lot of open-coded checks on scc_partno(), but
as we add more board types this is
Add the remaining devices (or unimplemented-device stubs) for
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
QSPI write-config block, and ethernet.
Signed-off-by: Peter Maydell
---
hw/arm/mps3r.c | 74 ++
1 file changed, 74 insertions(+)
We support two different encodings for the AArch32 IMPDEF
CBAR register -- older cores like the Cortex A9, A7, A15
have this at 4, c15, c0, 0; newer cores like the
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
When we implemented this we picked which encoding to
use based on whether the CPU
Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
board. These are all simple devices that just need to be created and
wired up.
Signed-off-by: Peter Maydell
---
hw/arm/mps3r.c | 59 ++
1 file changed, 59 insertions(+)
diff --g
This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines. Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.
Connect and
This patchset implements a new machine type, mps3-an536. This is
similar to our existing mps2-* and mps3-* machine types in that it is
a model of an FPGA image for the Arm MPS3 development board. It
differs from our current machine types in being based around an
R-profile CPU, the Cortex-R52, rat
On Tue, Feb 06, 2024 at 10:10:02AM +0800, Xianglai Li wrote:
> The UEFI loading mode in loongarch is very different
> from that in other architectures:loongarch's UEFI code
> is in rom, while other architectures' UEFI code is in flash.
>
> loongarch UEFI can be loaded as follows:
> -machine virt,pf
On Tue, 30 Jan 2024 at 15:25, Philippe Mathieu-Daudé wrote:
>
> Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
> connect FIQ output of the GIC CPU interfaces to the CPU.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/xilinx_zynq.c | 2 ++
> 1 file changed, 2 insertio
On Mon, 5 Feb 2024 at 12:19, Stefan Hajnoczi wrote:
>
> C99 mixed declarations support interleaving of local variable
> declarations and code.
>
> The coding style "generally" forbids C99 mixed declarations with some
> exceptions to the rule. This rule is not checked by checkpatch.pl and
> natural
Synchronizing the list of cpu features and models with qemu is a recurring
task in libvirt. For x86, this is done by reading qom-list-properties for
max-x86_64-cpu and manually filtering out everthing that does not look like
a feature name, as well as parsing target/i386/cpu.c for cpu models.
This
The comments are preserved in the yaml file.
Signed-off-by: Tim Wiederhake
---
target/i386/feature_word_info.c.inc | 56 -
1 file changed, 15 insertions(+), 41 deletions(-)
diff --git a/target/i386/feature_word_info.c.inc
b/target/i386/feature_word_info.c.inc
index
Signed-off-by: Tim Wiederhake
---
target/i386/feature_word_info.c.inc | 30 ++--
target/i386/feature_word_info.py| 71 +
target/i386/feature_word_info.yaml | 2 +
3 files changed, 99 insertions(+), 4 deletions(-)
create mode 100755 target/i386/feature_wo
This is the data file that will be used to generate the C code.
All information, including the comments, is preserved.
Signed-off-by: Tim Wiederhake
---
target/i386/feature_word_info.yaml | 699 +
1 file changed, 699 insertions(+)
create mode 100644 target/i386/featu
Make the formatting of the file more regular. This reduces the
diff to the generated version.
Signed-off-by: Tim Wiederhake
---
target/i386/feature_word_info.c.inc | 136 ++--
1 file changed, 86 insertions(+), 50 deletions(-)
diff --git a/target/i386/feature_word_info.c.
The isolated part will be generated by a script.
Signed-off-by: Tim Wiederhake
---
target/i386/cpu.c | 679 +---
target/i386/feature_word_info.c.inc | 678 +++
2 files changed, 679 insertions(+), 678 deletions(-)
create mode 1006
This is the first very rough version of what is supposed to be support for
multiboot2. This is a continuation of work that was started years ago but
never saw fruition for reasons unknown.
This is submitted as an RFC only for now. It would be nice if someone would
be willing to guide me into furth
From: Marc-André Lureau
Fixes:
rm -rf b; cd b
../configure --enable-modules --target-list=x86_64-softmmu
ninja qemu-system-x86_64
In file included from ../ui/dbus-chardev.c:34:
../ui/dbus.h:34:10: fatal error: ui/dbus-display1.h: No such file or directory
34 | #include "ui/dbus-
QEMU's coding style generally forbids C99 mixed declarations.
Signed-off-by: Stefan Hajnoczi
---
hw/block/virtio-blk.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
index 227d83569f..f6009cd9b3 100644
On Tue, Feb 06, 2024 at 03:28:49AM -0500, Xiaoyao Li wrote:
> Different confidential VMs in different architectures all have the same
> needs to do their specific initialization (and maybe resetting) stuffs
> with KVM. Currently each of them exposes individual *_kvm_init()
> functions and let machi
On Tue, Feb 06, 2024 at 03:28:50AM -0500, Xiaoyao Li wrote:
> Use confidential_guest_kvm_init() instead of calling SEV specific
> sev_kvm_init(). As a bouns, it fits to future TDX when TDX implements
> its own confidential_guest_support and .kvm_init().
>
> Move the "TypeInfo sev_guest_info" defin
On Tue, Feb 06, 2024 at 03:28:48AM -0500, Xiaoyao Li wrote:
> This series is inspired and suggested by Daniel:
> https://lore.kernel.org/qemu-devel/zbfoqseuv6_zw...@redhat.com/
>
> Currently, different confidential VMs in different architectures have
> their own specific *_kvm_init() (and some hav
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> When MTE3 is supported, the kernel maps
> PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
> to
> MTE_CTRL_TCF_ASYMM
> and from there to
> SCTLR_EL1.TCF0 = 3
This depends on the setting of
/sys/devices/system/cpu/cpu/mte_tcf_preferred :
I think yo
Avihai Horon writes:
> On 05/02/2024 21:49, Fabiano Rosas wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> During multifd channel creation (multifd_send_new_channel_async) when
>> TLS is enabled, the multifd_channel_connect function is called twice,
>> once to create th
On 06/02/2024 16:30, Fabiano Rosas wrote:
External email: Use caution opening links or attachments
Avihai Horon writes:
On 05/02/2024 21:49, Fabiano Rosas wrote:
External email: Use caution opening links or attachments
During multifd channel creation (multifd_send_new_channel_async) whe
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> The field is encoded as [0-3], which is convenient for
> indexing our array of function pointers, but the true
> value is [1-4]. Adjust before calling do_mem_zpa.
>
> Add an assert, and move the comment re passing ZT to
> the helper back n
On Tue, 6 Feb 2024 at 03:07, Richard Henderson
wrote:
>
> When we added SVE_MTEDESC_SHIFT, we effectively limited the
> maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining
> bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored
> fits within the field (expecting 8 * 4 - 1 =
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> Share code that creates mtedesc and embeds within simd_desc.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-a64.h | 2 ++
> target/arm/tcg/translate-sme.c | 15 +++
> target/arm/tcg/translate-sve.c | 47 +++
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> These functions "use the standard load helpers", but
> fail to clean_data_tbi or populate mtedesc.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> The TBI and TCMA bits are located within mtedesc, not desc.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 6 Feb 2024 at 03:07, Richard Henderson
wrote:
>
> The first patch is unchanged from
>
> Supercedes: <20240131003557.176486-1-richard.hender...@linaro.org>
>
> while the remaining patches replace
>
> Supercedes: <20240205023948.25476-1-richard.hender...@linaro.org>
>
> While digging through
On Tue, Feb 6, 2024 at 9:31 AM Stefano Garzarella wrote:
>
> On Tue, Feb 06, 2024 at 10:47:40AM +0800, Jason Wang wrote:
> >On Mon, Feb 5, 2024 at 6:51 PM Stefano Garzarella
> >wrote:
> >>
> >> On Fri, Feb 02, 2024 at 02:25:21PM +0100, Kevin Wolf wrote:
> >> >VDUSE requires that virtqueues are f
On 05.02.24 18:26, Stefan Hajnoczi wrote:
Hanna Czenczek noticed that the safety of
`vq_aio_context[vq->value] = ctx;` with user-defined vq->value inputs is
not obvious.
The code is structured in validate() + apply() steps so input validation
is there, but it happens way earlier and there is no
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