On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This is a series of patches for adding support for the Branch History
> Rolling Buffer (BHRB) facility. This was added to the Power ISA
> starting with version 2.07. Changes were subsequently made in version
> 3.1 to limit BHRB recording t
On 2024/2/5 下午3:47, Thomas Huth wrote:
On 05/02/2024 03.13, Bibo Mao wrote:
The cdrom test skips to execute on LoongArch system with command
"make check"
Are you sure the test is marked with "skip"? ... it should at least test
with the "none" machine...?
With the latest code, cdrom testcas
Hi,
On 2/2/24 11:51, Peter Maydell wrote:
> On Thu, 1 Feb 2024 at 23:50, Peter Xu wrote:
>> Fabiano, I think you forgot to reply-to-all.. adding back the list and
>> people in the loop.
>>
>> On Thu, Feb 01, 2024 at 10:12:44AM -0300, Fabiano Rosas wrote:
>>> Peter Xu writes:
>>>
On Wed, Jan
On Mon, Feb 5, 2024 at 3:42 AM Alistair Francis wrote:
>
> On Sun, Feb 4, 2024 at 3:44 PM LIU Zhiwei
> wrote:
> >
> > This patch set fix the regression on kernel pointed by Björn Töpel in
> > https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.
> >
> > thead-c906 uses some flags i
On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This commit continues adding support for the Branch History
> Rolling Buffer (BHRB) as is provided starting with the P8
> processor and continuing with its successors. This commit
> is limited to the recording and filtering of taken branche
Commit aa09b3d5f8e (stats: Move QMP commands from monitor/ to stats/)
created section Stats, but neglected to add qapi/stats.json to it.
Fix that.
Signed-off-by: Markus Armbruster
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 00ada764a7..9103
Markus Armbruster (2):
MAINTAINERS: Cover qapi/cxl.json
MAINTAINERS: Cover qapi/stats.json
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
--
2.43.0
Commit 415442a1b4a (hw/mem/cxl_type3: Add CXL RAS Error Injection
Support.) created qapi/cxl.json without adding it to MAINTAINERS. Fix
that.
Cc: Ben Widawsky
Cc: Jonathan Cameron
Cc: Fan Ni
Signed-off-by: Markus Armbruster
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/
On 2/1/24 17:32, Eric Auger wrote:
aw-bits is a new option that allows to set the bit width of
the input address range. This value will be used as a default for
the device config input_range.end. By default it is set to 64 bits
which is the current value.
Signed-off-by: Eric Auger
---
v1 -> v
On 2/1/24 17:32, Eric Auger wrote:
Use %u format to trace domain_range limits.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/virtio/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-e
v0:
1. support uart controller both 0 and 1 base
2. fix hardcode boot address 0
Jamin Lin (2):
aspeed: support uart controller both 0 and 1 base
aspeed: fix hardcode boot address 0
hw/arm/aspeed.c | 12
hw/arm/aspeed_ast10x0.c | 1 +
hw/arm/aspeed_ast2400.c
In the previous design of QEMU model for ASPEED SOCs, it set the boot
address at 0 which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has bootmcu which is used for
executing SPL and initialize DRAM, then, CPUs(cortex-a35)
execute u-boot
According to the design of ASPEED SOCS, the uart controller
is 1 base for ast10x0, ast2600, ast2500 and ast2400.
However, the uart controller is 0 base for ast2700.
To support uart controller both 0 and 1 base,
adds uasrt_bases parameter in AspeedSoCClass
and set the default uart controller 1 base
Akihiko Odaki writes:
> On 2024/02/03 22:58, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> On 2024/02/03 20:08, Alex Bennée wrote:
Akihiko Odaki writes:
> This series extracts fixes and refactorings that can be applied
> independently from "[PATCH v9 00/23] plugins: Allo
On 2/1/24 17:32, Eric Auger wrote:
Currently the default input range can extend to 64 bits. On x86,
when the virtio-iommu protects vfio devices, the physical iommu
may support only 39 bits. Let's set the default to 39, as done
for the intel-iommu. On ARM we set 48b as a default (matching
SMMUv3 S
On a Saturday in 2024, Markus Armbruster wrote:
It's an alias for "ringbuf" we kept for backward compatibility; see
commit 3a1da42eb35 (qapi: Rename ChardevBackend member "memory" to
"ringbuf"). Deprecation is long overdue.
Signed-off-by: Markus Armbruster
---
docs/about/deprecated.rst | 8 +++
> -Original Message-
> From: Jamin Lin
> Sent: Monday, February 5, 2024 4:18 PM
> To: Cédric Le Goater ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; open list:ASPEED BMCs
> ; open list:All patches CC here
>
> Cc: Troy Lee ; Jamin Lin
>
> Subject: [PATCH v0] aspeed: support uart c
Friendly reminder & bump
Is this series waiting to be picked up, or is there anything left to do?
BR,
Albert
On Tue, Jan 9, 2024 at 1:56 PM Albert Esteve wrote:
> v1: https://www.mail-archive.com/qemu-devel@nongnu.org/msg1005257.html
> v2: https://www.mail-archive.com/qemu-devel@nongnu.org/
On Sat, Feb 03, 2024 at 11:48:44PM +0300, Michael Tokarev wrote:
> 01.02.2024 01:02, Ilya Leoshkevich wrote:
> > The `if not probe_proc_self_mem` check never passes, because
> > probe_proc_self_mem is a function object, which is a truthy value.
> > Add parentheses in order to perform a function cal
On 2/5/24 13:31, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/03 22:58, Alex Bennée wrote:
Akihiko Odaki writes:
On 2024/02/03 20:08, Alex Bennée wrote:
Akihiko Odaki writes:
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plu
On 05/02/2024 07.56, Thomas Huth wrote:
On 02/02/2024 16.40, Peter Maydell wrote:
On Fri, 2 Feb 2024 at 15:36, David Woodhouse wrote:
On Fri, 2024-02-02 at 15:32 +, Peter Maydell wrote:
This fails "make check' because some of the qom-test and
test-hmp checks fail when the QEMU binary se
Hi Eric,
On Thu, Feb 01, 2024 at 05:32:22PM +0100, Eric Auger wrote:
> aw-bits is a new option that allows to set the bit width of
> the input address range. This value will be used as a default for
> the device config input_range.end. By default it is set to 64 bits
> which is the current value.
Hi,
turning pages back in time,
noticed that in recent qemu-img binaries we include an ELF dependency on
libnuma.so that seems unused.
I think it stems from this commit:
commit 10218ae6d006f76410804cc4dc690085b3d008b5
Author: David Hildenbrand
Date: Fri Oct 14 15:47:17 2022 +0200
util:
On 2/5/24 04:37, Peter Xu wrote:
On Fri, Feb 02, 2024 at 12:11:09PM -0300, Fabiano Rosas wrote:
Cédric Le Goater writes:
On 2/2/24 15:42, Fabiano Rosas wrote:
Cédric Le Goater writes:
In case of error, close_return_path_on_source() can perform a shutdown
to exit the return-path thread. H
On 2/5/24 10:14, Cédric Le Goater wrote:
On 2/1/24 17:32, Eric Auger wrote:
aw-bits is a new option that allows to set the bit width of
the input address range. This value will be used as a default for
the device config input_range.end. By default it is set to 64 bits
which is the current value.
On Mon, Feb 05, 2024 at 11:25:13AM +0800, Peter Xu wrote:
> On Fri, Feb 02, 2024 at 10:47:05AM -0300, Fabiano Rosas wrote:
> > Peter Maydell writes:
> >
> > > On Mon, 29 Jan 2024 at 03:04, wrote:
> > >>
> > >> From: Fabiano Rosas
> > >>
> > >> The migration tests have support for being passed t
On Fri, Feb 02, 2024 at 09:35:19AM +0100, Fiona Ebner wrote:
> Am 18.12.23 um 11:13 schrieb Fiona Ebner:
> > In many configurations, e.g. multiple vNICs with multiple queues or
> > with many Ceph OSDs, the default soft limit of 1024 is not enough.
> > QEMU is supposed to work fine with file descrip
On Fri, Feb 02, 2024 at 05:53:39PM +0800, Peter Xu wrote:
> On Thu, Feb 01, 2024 at 07:48:51PM +0100, Cédric Le Goater wrote:
> > Hello,
>
> Hi, Cédric,
>
> Thanks for the patches.
>
> >
> > Today, close_return_path_on_source() can perform a shutdown to exit
> > the return-path thread if an err
On Mon, Feb 05, 2024 at 10:22:35AM +, Daniel P. Berrangé wrote:
> On Mon, Feb 05, 2024 at 11:25:13AM +0800, Peter Xu wrote:
> > On Fri, Feb 02, 2024 at 10:47:05AM -0300, Fabiano Rosas wrote:
> > > Peter Maydell writes:
> > >
> > > > On Mon, 29 Jan 2024 at 03:04, wrote:
> > > >>
> > > >> From
Hello Jamin,
On 2/5/24 10:14, Jamin Lin wrote:
According to the design of ASPEED SOCS, the uart controller
is 1 base for ast10x0, ast2600, ast2500 and ast2400.
However, the uart controller is 0 base for ast2700.
To support uart controller both 0 and 1 base,
adds uasrt_bases parameter in AspeedS
On Mon, Feb 05, 2024 at 06:45:23PM +0800, Peter Xu wrote:
> On Mon, Feb 05, 2024 at 10:22:35AM +, Daniel P. Berrangé wrote:
> > On Mon, Feb 05, 2024 at 11:25:13AM +0800, Peter Xu wrote:
> > > On Fri, Feb 02, 2024 at 10:47:05AM -0300, Fabiano Rosas wrote:
> > > > Peter Maydell writes:
> > > >
On Fri, Feb 02, 2024 at 02:25:21PM +0100, Kevin Wolf wrote:
VDUSE requires that virtqueues are first enabled before the DRIVER_OK
status flag is set; with the current API of the kernel module, it is
impossible to enable the opposite order in our block export code because
userspace is not notified
On Mon, 5 Feb 2024 at 10:11, Thomas Huth wrote:
>
> On 05/02/2024 07.56, Thomas Huth wrote:
> > On 02/02/2024 16.40, Peter Maydell wrote:
> >> On Fri, 2 Feb 2024 at 15:36, David Woodhouse wrote:
> >>>
> >>> On Fri, 2024-02-02 at 15:32 +, Peter Maydell wrote:
>
> This fails "make che
On Mon, 2024-02-05 at 13:05 +1000, Richard Henderson wrote:
> On 1/26/24 23:52, Richard Purdie wrote:
> > On Fri, 2024-01-26 at 16:33 +0300, Michael Tokarev wrote:
> > > 26.01.2024 16:03, Richard Purdie wrote:
> > > > I've run into a problem with this change.
> > > >
> > > > We (Yocto Project) upg
On 05/02/2024 8:20, Peter Xu wrote:
External email: Use caution opening links or attachments
On Fri, Feb 02, 2024 at 04:11:28PM -0300, Fabiano Rosas wrote:
It is possible that one of the multifd channels fails to be created at
multifd_new_send_channel_async() while the rest of the channel
cr
Pierrick Bouvier writes:
> On 2/5/24 13:31, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> On 2024/02/03 22:58, Alex Bennée wrote:
Akihiko Odaki writes:
> On 2024/02/03 20:08, Alex Bennée wrote:
>> Akihiko Odaki writes:
>>
>>> This series extracts fixes and refac
The upcoming follow-fork-mode child support will require disabling
gdbstub in the parent process, which may have multiple threads (which
are represented as CPUs).
Loop over all CPUs in order to remove watchpoints and disable
single-step. Move the respective code into a separate function.
Signed-o
The upcoming follow-fork-mode child support requires advertising the
fork-events feature, which is user-specific. Introduce a user-specific
hook for this.
Signed-off-by: Ilya Leoshkevich
---
gdbstub/gdbstub.c | 12 +---
gdbstub/internals.h | 1 +
gdbstub/user.c | 4
3 files
The upcoming follow-fork-mode child support requires post-fork message
exchange between the parent and the child. Prepare gdbserver_fork() for
this purpose. Rename it to gdbserver_fork_end() to better reflect its
purpose.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/main.c| 3 ++-
gdbstu
Based-on: <20240202152506.279476-1-...@linux.ibm.com>
("[PATCH v3 0/5] gdbstub: Implement catching syscalls")
v1: https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg06646.html
v1 -> v2: Factor out a number of prep patches;
Add a state transition diagram comment (Alex).
Im
Add follow-fork-mode child and and follow-fork-mode parent tests.
Check for the obvious pitfalls, such as lingering breakpoints,
catchpoints, and single-step mode.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/Makefile.target | 17 +-
tests/tcg/multiarch/follow-fork-mode.
Currently it's not possible to use gdbstub for debugging linux-user
code that runs in a forked child, which is normally done using the `set
follow-fork-mode child` GDB command. Purely on the protocol level, the
missing piece is the fork-events feature.
However, a deeper problem is supporting $Hg s
The upcoming follow-fork-mode child support requires knowing the child
pid. Pass it down.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/main.c| 2 +-
gdbstub/user.c | 2 +-
include/gdbstub/user.h | 2 +-
linux-user/main.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(
Currently ts_tid contains the parent tid after fork(), which is not
correct. So far it has not affected anything, but the upcoming
follow-fork-mode child support relies on the correct value, so fix it.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/main.c | 1 +
linux-user/main.c | 1 +
2 files
The upcoming follow-fork-mode child support requires knowing when
fork() is about to happen in order to initialize its state. Add a hook
for that.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/main.c| 1 +
gdbstub/user.c | 4
include/gdbstub/user.h | 5 +
linux-user/main.
The upcoming follow-fork-mode child support requires knowing the child
pid. Pass it down.
Signed-off-by: Ilya Leoshkevich
---
bsd-user/freebsd/os-proc.h | 6 +++---
bsd-user/main.c | 4 +++-
bsd-user/qemu.h | 2 +-
linux-user/main.c | 4 +++-
linux-user/syscall
The upcoming follow-fork-mode child support needs to perform certain
actions when GDB switches between the stopped parent and the stopped
child. Introduce a user-specific hook for this.
Signed-off-by: Ilya Leoshkevich
---
gdbstub/gdbstub.c | 11 +--
gdbstub/internals.h | 1 +
gdbstub/
The upcoming follow-fork-mode child support needs to perform certain
actions when GDB detaches from the stopped parent or the stopped child.
Introduce a user-specific hook for this.
Signed-off-by: Ilya Leoshkevich
---
gdbstub/gdbstub.c | 6 ++
gdbstub/internals.h | 1 +
gdbstub/user.c
On 2/5/24 04:00, Alexandre Ghiti wrote:
Currently, the initrd is placed at 128MB, which overlaps with the kernel
when it is large (for example syzbot kernels are). From the kernel side,
there is no reason we could not push the initrd further away in memory
to accomodate large kernels, so move
On Fri, Feb 2, 2024 at 2:25 PM Kevin Wolf wrote:
>
> VDUSE requires that virtqueues are first enabled before the DRIVER_OK
> status flag is set; with the current API of the kernel module, it is
> impossible to enable the opposite order in our block export code because
> userspace is not notified w
Raphael Norwitz writes:
> I'd prefer to use my new work email so this change updates MAINTAINERS
> with it.
>
> Signed-off-by: Raphael Norwitz
Reviewed-by: Alex Bennée
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> ind
On 02/02/2024 15.11, Ilya Leoshkevich wrote:
Check the CVD's, CVDY's, and CVDG's corner cases.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/cvd.c | 63 +
2 files changed, 64 insertions(+)
create mode
On Wed, Jan 31, 2024 at 09:14:21PM +0100, Markus Armbruster wrote:
> == What users want for initial configuration ==
>
> 1. QMP only
>
>Management applications need to use QMP for monitoring anyway. They
>may want to use it for initial configuration, too. Libvirt does.
>
>They stil
On Mon, Feb 05, 2024 at 01:10:14PM +0200, Avihai Horon wrote:
>
> On 05/02/2024 8:20, Peter Xu wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Fri, Feb 02, 2024 at 04:11:28PM -0300, Fabiano Rosas wrote:
> > > It is possible that one of the multifd channels fail
Albert Esteve writes:
> Shared objects lack spoofing protection.
> For VHOST_USER_BACKEND_SHARED_OBJECT_REMOVE messages
> received by the vhost-user interface, any backend was
> allowed to remove entries from the shared table just
> by knowing the UUID. Only the owner of the entry
> shall be allo
Hi Bibo,
On 5/2/24 03:13, Bibo Mao wrote:
The cdrom test skips to execute on LoongArch system with command
"make check", this patch enables cdrom test for LoongArch virt
machine platform.
With this patch, cdrom test passes to run on LoongArch virt
machine type.
Signed-off-by: Bibo Mao
---
t
ilable in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205
>
> for you to fetch changes up to 867db6870a6f5d4e0915822d6a84e665bec1f22e:
>
> tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-03 23:53:49 +)
>
> --
Am 02.02.2024 um 14:25 hat Kevin Wolf geschrieben:
> VDUSE requires that virtqueues are first enabled before the DRIVER_OK
> status flag is set; with the current API of the kernel module, it is
> impossible to enable the opposite order in our block export code because
> userspace is not notified wh
On 5/2/24 11:46, Cédric Le Goater wrote:
Hello Jamin,
On 2/5/24 10:14, Jamin Lin wrote:
According to the design of ASPEED SOCS, the uart controller
is 1 base for ast10x0, ast2600, ast2500 and ast2400.
However, the uart controller is 0 base for ast2700.
To support uart controller both 0 and 1 b
Hi Jamin,
On 5/2/24 10:14, Jamin Lin via wrote:
In the previous design of QEMU model for ASPEED SOCs, it set the boot
address at 0 which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has bootmcu which is used for
executing SPL and ini
On 1/29/24 16:35, Hannes Reinecke wrote:
On 1/29/24 14:13, Damien Hedde wrote:
On 1/24/24 08:47, Hannes Reinecke wrote:
On 1/24/24 07:52, Philippe Mathieu-Daudé wrote:
Hi Hannes,
[+Markus as QOM/QDev rubber duck]
On 23/1/24 13:40, Hannes Reinecke wrote:
On 1/23/24 11:59, Damien Hedde wr
On 2/5/24 10:14, Jamin Lin wrote:
In the previous design of QEMU model for ASPEED SOCs, it set the boot
address at 0 which was the hardcode setting for ast10x0, ast2600,
ast2500 and ast2400.
According to the design of ast2700, it has bootmcu which is used for
executing SPL and initialize DRAM, t
Hi Daniel,
On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 2/5/24 04:00, Alexandre Ghiti wrote:
> > Currently, the initrd is placed at 128MB, which overlaps with the kernel
> > when it is large (for example syzbot kernels are). From the kernel side,
> > there is no reason
Hi Inès,
On 26/1/24 20:31, Inès Varhol wrote:
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 55 +-
include/hw/arm/stm32l4x5_soc.h | 3 ++
3 files changed, 58 insertions(+
Am 05.02.2024 um 13:22 hat Eugenio Perez Martin geschrieben:
> On Fri, Feb 2, 2024 at 2:25 PM Kevin Wolf wrote:
> >
> > VDUSE requires that virtqueues are first enabled before the DRIVER_OK
> > status flag is set; with the current API of the kernel module, it is
> > impossible to enable the opposi
Hi Inès,
On 26/1/24 20:31, Inès Varhol wrote:
`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).
`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are
On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
> The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> until now, we were implying that they were available.
>
> We can't do this anymore since named features also has a riscv,isa
> entry. Let's add them to
Hi Inès,
On 26/1/24 20:31, Inès Varhol wrote:
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix.
This color shield can be plugged on the Arduino board (or the
B-L475E
On 5/2/24 09:47, Markus Armbruster wrote:
Markus Armbruster (2):
MAINTAINERS: Cover qapi/cxl.json
MAINTAINERS: Cover qapi/stats.json
Series:
Reviewed-by: Philippe Mathieu-Daudé
On 02/02/2024 15.12, Ilya Leoshkevich wrote:
Check the CVB's, CVBY's, and CVBG's corner cases.
Co-developed-by: Pavel Zbitskiy
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/cvb.c | 102
2 files change
Peter Xu writes:
> On Fri, Feb 02, 2024 at 06:34:08PM -0300, Fabiano Rosas wrote:
>> pet...@redhat.com writes:
>>
>> > From: Peter Xu
>> >
>> > When reviewing my attempt to refactor send_prepare(), Fabiano suggested we
>> > try out with dropping the mutex in multifd code [1].
>> >
>> > I though
On 05.02.24 11:14, Claudio Fontana wrote:
Hi,
Hi Claudio,
turning pages back in time,
noticed that in recent qemu-img binaries we include an ELF dependency on
libnuma.so that seems unused.
I think it stems from this commit:
commit 10218ae6d006f76410804cc4dc690085b3d008b5
Author: David Hi
I've had a version of this code for many years (and occasionally mention it
as test platform for kernel patches) and it keeps coming in handy, so time
to share the CXL version.
What is this?
- ACPI + UEFI specs define a means of notifying the OS of errors that
firmware has handled (gathered up d
Simple search code used to find first instance of a PCIe
Designated Vendor-Specific Extended Capability.
Signed-off-by: Jonathan Cameron
---
include/hw/pci/pcie.h | 1 +
hw/pci/pcie.c | 24
2 files changed, 25 insertions(+)
diff --git a/include/hw/pci/pcie.h b/
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/cxl.h | 2 +-
include/hw/pci-host/gpex.h | 1 +
hw/acpi/cxl-stub.c | 2 +-
hw/acpi/cxl.c | 31 +++
hw/i386/acpi-build.c | 2 +-
hw/pci-host/gpex-acpi.c| 17 +++--
hw
Provide a machine parameter to request firmware first RAS handling
and no hand over to the OS via _OSC.
Includes a bug fix as register access is not in CDW5 but only
in CXW4 (OS support field).
Signed-off-by: Jonathan Cameron
---
include/hw/arm/virt.h| 1 +
hw/acpi/cxl.c| 3 --
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/ghes.h | 1 +
hw/acpi/ghes.c | 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h
index 674f6958e9..4f1ab1a73a 100644
--- a/include/hw/acpi/ghes.h
+++ b/include/hw/a
Includes creation of a GED - Generic Event Device
Signed-off-by: Jonathan Cameron
---
include/hw/boards.h | 1 +
hw/arm/virt-acpi-build.c | 29 +
hw/arm/virt.c| 12 +++-
3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/include/
Allow QEMU to know what was successfully requested by the OS
via _OSC. Note this handling is very minimal and assumes last
written Control parameters were accepted (which they should be
if the OS is obeying the rules for negotiating this stuff).
Signed-off-by: Jonathan Cameron
---
include/hw/ac
If the machine supports firmware first error injection
enable those flows.
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/ghes.h | 3 +
hw/acpi/ghes-stub.c| 4 +
hw/acpi/ghes.c | 250 +++--
hw/pci/pcie_aer.c | 35 --
4 files chan
This should be dependent on the platform supporting FW first.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 9f1ca718b5..4f04a1702a 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -304,6 +304,12 @@
Even if we are doing native RAS, until the point where the OS
requests it via an _OSC the firmware may well be handling any
errors from CXL devices. As such configure them as if a firmware
has been doing so.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 4 ++--
1 file chang
Note this is only hooked up to type 3 device so far.
Injection via the same interface as for native errors.
e.g.
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem2",
"errors": [
{
"type": "cache-address-parity",
Initial code for Firmware First injection of general media events.
PoC level only - issue to be solved include:
* Mapping to CPER error types (recoverable etc).
* Some record details are tricky to establish so for now are not
provided.
Signed-off-by: Jonathan Cameron
---
include/hw/acpi/ghes.h
On Mon, Feb 05, 2024 at 11:10:34AM -0300, Fabiano Rosas wrote:
> > (maybe I can repost this single patch in-place to avoid another round of
> > mail bombs..)
>
> Sure.
I've got the final version attached here. Feel free to have a look, thanks.
>From 6ba337320430feae4ce9d3d906ea19f68430642
On 2/5/24 11:46, Cédric Le Goater wrote:
Hello Jamin,
On 2/5/24 10:14, Jamin Lin wrote:
According to the design of ASPEED SOCS, the uart controller
is 1 base for ast10x0, ast2600, ast2500 and ast2400.
However, the uart controller is 0 base for ast2700.
To support uart controller both 0 and 1 b
On Wed, Jan 31, 2024 at 9:42 AM Daniel P. Berrangé
wrote:
> On Wed, Jan 31, 2024 at 05:24:10PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > Warner, do you remember what this is about?
> >
> > (
> https://cgit.freebsd.org/ports/commit/emulators/qemu-devel/files/patch-util_meson.build?id=2a
On Mon, Feb 05, 2024 at 08:23:41AM -0700, Warner Losh wrote:
> On Wed, Jan 31, 2024 at 9:42 AM Daniel P. Berrangé
> wrote:
>
> > On Wed, Jan 31, 2024 at 05:24:10PM +0100, Philippe Mathieu-Daudé wrote:
> > > Hi,
> > >
> > > Warner, do you remember what this is about?
> > >
> > > (
> > https://cgit
Creating an instance of the 'TestEnv' class will create a temporary
directory. This dir is only deleted, however, in the __exit__ handler
invoked by a context manager.
In dry-run mode, we don't use the TestEnv via a context manager, so
were leaking the temporary directory. Since meson invokes 'che
Peter Xu writes:
> On Mon, Feb 05, 2024 at 01:10:14PM +0200, Avihai Horon wrote:
>>
>> On 05/02/2024 8:20, Peter Xu wrote:
>> > External email: Use caution opening links or attachments
>> >
>> >
>> > On Fri, Feb 02, 2024 at 04:11:28PM -0300, Fabiano Rosas wrote:
>> > > It is possible that one
On Mon, 5 Feb 2024 at 15:41, Daniel P. Berrangé wrote:
>
> Creating an instance of the 'TestEnv' class will create a temporary
> directory. This dir is only deleted, however, in the __exit__ handler
> invoked by a context manager.
>
> In dry-run mode, we don't use the TestEnv via a context manager
If something goes wrong causing the iotests not to cleanup their
temporary directory, it is useful if the dir had an identifying
name to show what is to blame.
Signed-off-by: Daniel P. Berrangé
---
tests/qemu-iotests/testenv.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
05.02.2024 18:40, Daniel P. Berrangé :
Creating an instance of the 'TestEnv' class will create a temporary
directory. This dir is only deleted, however, in the __exit__ handler
invoked by a context manager.
In dry-run mode, we don't use the TestEnv via a context manager, so
were leaking the temp
On Mon, 2024-02-05 at 15:31 +, Daniel P. Berrangé wrote:
> On Mon, Feb 05, 2024 at 08:23:41AM -0700, Warner Losh wrote:
> > On Wed, Jan 31, 2024 at 9:42 AM Daniel P. Berrangé
> >
> > wrote:
> >
> > > On Wed, Jan 31, 2024 at 05:24:10PM +0100, Philippe Mathieu-Daudé
> > > wrote:
> > > > Hi,
> >
On 2/5/24 09:31, Daniel P. Berrangé wrote:
On Mon, Feb 05, 2024 at 08:23:41AM -0700, Warner Losh wrote:
On Wed, Jan 31, 2024 at 9:42 AM Daniel P. Berrangé
wrote:
On Wed, Jan 31, 2024 at 05:24:10PM +0100, Philippe Mathieu-Daudé wrote:
> [... snip ...]
On 25/1/24 20:48, Ilya Leoshkevich wrote
Hello David,
It would seem to me that a lot of the calling code like qemu_prealloc_mem for
example
should be sysemu-only, not used for tools, or user mode either right?
And the thread_context.c itself should also be sysemu-only, correct?
Thanks,
Claudio
On 2/5/24 15:15, David Hildenbrand wrot
Hi Jean,
On 2/5/24 11:13, Jean-Philippe Brucker wrote:
> Hi Eric,
>
> On Thu, Feb 01, 2024 at 05:32:22PM +0100, Eric Auger wrote:
>> aw-bits is a new option that allows to set the bit width of
>> the input address range. This value will be used as a default for
>> the device config input_range.end
On 2/5/24 10:33, Cédric Le Goater wrote:
> On 2/1/24 17:32, Eric Auger wrote:
>> Currently the default input range can extend to 64 bits. On x86,
>> when the virtio-iommu protects vfio devices, the physical iommu
>> may support only 39 bits. Let's set the default to 39, as done
>> for the intel-
05.02.2024 18:51, Daniel P. Berrangé wrote:
If something goes wrong causing the iotests not to cleanup their
temporary directory, it is useful if the dir had an identifying
name to show what is to blame.
Signed-off-by: Daniel P. Berrangé
Revieved-by: Michael Tokarev
Thank you again for the
Hi all,
I'll revert the license changes and leave SPDX ids only for new files.
On Tue, Jan 30, 2024 at 12:38 PM Daniel P. Berrangé wrote:
>
> On Thu, Jan 25, 2024 at 03:06:50PM +0200, Andrew Melnychenko wrote:
> > Changed eBPF map updates through mmaped array.
> > Mmaped arrays provide direct acc
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