Re: [PATCH v2 0/3] VIRTIO-IOMMU: Introduce an aw-bits option

There is no VFIO_MAP_DMA error when hotplug 2 E810 PFs into a VM which has a virtio-iommu device. In addition, 21 regression tests of Tier1 level were run and all got PASS. Tested-by: Yanghang Liu On Fri, Feb 2, 2024 at 12:33 AM Eric Auger wrote: > > In [1] and [2] we attempted to fix a case w

Re: [PATCH 0/2] Fix pointer arithmetic in indirect read for libvhost-user and libvduse

Hello, I am very sorry for bothering community on a such minor problem again, but I got no response for a few weeks, so maybe I have started thread on a wrong mailing list, so I made an issue in gitlab issue tracker: https://gitlab.com/qemu-project/qemu/-/issues/2149 referencing this thread. Maybe

GPL 3.0 in TCG test code

Dear all, some QEMU code under tests/tcg uses GPL 3.0 or later: tests/tcg/aarch64/semicall.h: * SPDX-License-Identifier: GPL-3.0-or-later tests/tcg/arm/semicall.h: * SPDX-License-Identifier: GPL-3.0-or-later tests/tcg/i386/system/boot.S: * SPDX-License-Identifier: GPL-3.0-or-later tests/tcg/mult

Help understanding allocation and mapping flow of virtio-gpu 3D resource blobs

Hi, I'm trying to get an understanding of the blob allocation and mapping flow for virtio-gpu for Vulkan and Rutabaga. Having gotten all the various libraries setup I'm still seeing failures when running a TCG guest (buildroot + latest glm, mesa, vkmark) with: ./qemu-system-aarch64 \

Re: Help understanding allocation and mapping flow of virtio-gpu 3D resource blobs

Good morning Alex, Just one observation, On Sun, 04 Feb 2024 13:06, Alex Bennée wrote: Hi, I'm trying to get an understanding of the blob allocation and mapping flow for virtio-gpu for Vulkan and Rutabaga. Having gotten all the various libraries setup I'm still seeing failures when running a

Re: [PATCH v2 0/2] hw/smbios: Fix option validation

On Sun, Feb 04, 2024 at 07:57:48AM +0300, Michael Tokarev wrote: > 29.01.2024 11:03, Akihiko Odaki: > > This fixes qemu_smbios_type8_opts and qemu_smbios_type11_opts to have > > list terminators and elements for the type option. > > > Akihiko Odaki (2): > >hw/smbios: Fix OEM strings table

Re: [PATCH v1 01/15] libvhost-user: Fix msg_region->userspace_addr computation

On 04.02.24 02:35, Raphael Norwitz wrote: As a heads up, I've left Nutanix and updated it in MAINTAINERS. Will be updating it again shortly so tagging these with my new work email. Thanks for the fast review! The mail server already complained to me :) Maybe consider adding yourself as review

Re: Help understanding allocation and mapping flow of virtio-gpu 3D resource blobs

Alex Bennée writes: (doh, replying to virglrender-devel thanks to autocomplete failure) > Hi, > > I'm trying to get an understanding of the blob allocation and mapping > flow for virtio-gpu for Vulkan and Rutabaga. Having gotten all the > various libraries setup I'm still seeing failures when ru

Re: [PATCH v1 11/15] libvhost-user: Speedup gpa_to_mem_region() and vu_gpa_to_va()

On 04.02.24 03:10, Raphael Norwitz wrote: One comment on this one. On Fri, Feb 2, 2024 at 4:56 PM David Hildenbrand wrote: Let's speed up GPA to memory region / virtual address lookup. Store the memory regions ordered by guest physical addresses, and use binary search for address translation,

Re: [PATCH v1 14/15] libvhost-user: Dynamically remap rings after (temporarily?) removing memory regions

On 04.02.24 03:15, Raphael Norwitz wrote: Someone else with more knowledge of the VQ mapping code should also review. On Fri, Feb 2, 2024 at 4:55 PM David Hildenbrand wrote: Currently, we try to remap all rings whenever we add a single new memory region. That doesn't quite make sense, because

Re: [PATCH v4 1/1] oslib-posix: initialize backend memory objects in parallel

On 03.02.24 23:43, Dongli Zhang wrote: On 1/31/24 08:53, Mark Kanda wrote: QEMU initializes preallocated backend memory as the objects are parsed from the command line. This is not optimal in some cases (e.g. memory spanning multiple NUMA nodes) because the memory objects are initialized in se

Re: [PULL 02/10] hw/hppa/machine: Disable default devices with --nodefaults option

Hi Helge, On Thu, Feb 01, 2024 at 08:22:58PM -0800, Guenter Roeck wrote: > Hi, > > On Sat, Jan 13, 2024 at 06:57:20AM +0100, del...@kernel.org wrote: > > From: Helge Deller > > > > Recognize the qemu --nodefaults option, which will disable the > > following default devices on hppa: > > - lsi53c

Re: [PATCH 2/4] isa: extract FDC37M81X to a separate file

Am 29. Januar 2024 13:37:46 UTC schrieb Paolo Bonzini : >isa-superio.c currently defines a SuperIO chip that depends on >CONFIG_IDE_ISA, but not all users of isa-superio.c depend on that >symbol. Extract the chip to a separate file so that there is an >obvious place to select IDE_ISA. > >Signed

Re: [PATCH rfcv1 23/23] intel_iommu: modify x-scalable-mode to be string option

On Wed, Jan 31, 2024 at 11:24:18PM +0800, Yi Liu wrote: > On 2024/1/31 22:40, Joel Granados wrote: > > On Mon, Jan 15, 2024 at 06:37:35PM +0800, Zhenzhong Duan wrote: > >> From: Yi Liu > >> > >> Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities > >> related to scalable mo

[PULL 00/39] tcg patch queue

The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440: Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205 for yo

[PULL 01/39] tcg: Introduce TCG_COND_TST{EQ,NE}

Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-cond.h | 74 ++ tcg/tcg.c | 4 ++- docs/devel/tcg-ops.

[PULL 20/39] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX

... and the inverse, CBZ for TSTEQ. Suggested-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 36fc

[PULL 25/39] tcg/i386: Support TCG_COND_TST{EQ,NE}

Merge tcg_out_testi into tcg_out_cmp and adjust the two uses. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.c.inc | 95 --- 2 files changed, 60 insertions(+), 37 deletions(-) d

[PULL 07/39] tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported

After having performed other simplifications, lower any remaining test comparisons with AND. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 2 ++ tcg/optimize.c | 60 +++--- tcg/tcg.c | 2 +- 3

[PULL 02/39] tcg: Introduce TCG_TARGET_HAS_tst

Define as 0 for all tcg backends. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h| 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h| 2 ++ tcg

[PULL 17/39] tcg/aarch64: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 5 +-- tcg/aarch64/tcg-target-con-str.h | 1 + tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 56 ++-- 4 files changed, 44 inser

[PULL 11/39] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 49 +++- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 220eda2137..882cf6cea0 100644

[PULL 03/39] tcg/optimize: Split out arg_is_const_val

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 +++--- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f2d01654c5..73019b9996 100644 --- a/tcg/optimize.c +++ b/tcg/

[PULL 35/39] tcg/ppc: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 122 --- 2 files changed, 115 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 6

[PULL 28/39] tcg/sparc64: Hoist read of tcg_cond_to_rcond

Use a non-zero value here (an illegal encoding) as a better condition than is_unsigned_cond for when MOVR/BPR is usable. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++--- 1 file changed, 14 insertions(+), 11 del

[PULL 14/39] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}

These are all test-and-compare type instructions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/transla

[PULL 34/39] tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h |

[PULL 22/39] tcg/arm: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108145244.72421-2-phi...@linaro.org> --- tcg/arm/tcg-target.h

[PULL 08/39] target/alpha: Pass immediate value to gen_bcond_internal()

Simplify gen_bcond() by passing an immediate value. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247

[PULL 12/39] target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/translate.c | 74 ++--- 1 file changed, 33 insertions(+), 41 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f886190f88..d7d5ff4300 100644 -

[PULL 31/39] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc

Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 28 +--- 1 file changed, 17 insertions(+), 1

[PULL 37/39] tcg/s390x: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 6 +-- tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.c.inc | 72 +- 3 files ch

[PULL 29/39] tcg/sparc64: Pass TCGCond to tcg_out_cmp

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e16b25e309..10fb8a1a0d 100644 --- a/

[PULL 09/39] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247.83234-2-phi...@linaro.org> --- target/alpha/transla

[PULL 13/39] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7df6f83b13..d9304a5bc4 100644 --- a/target/sparc/translate.c +++ b/t

[PULL 24/39] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp

Return the x86 condition codes to use after the compare. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-tar

[PULL 36/39] tcg/s390x: Split constraint A into J+U

Signed 33-bit == signed 32-bit + unsigned 32-bit. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 8 tcg/s390x/tcg-target-con-str.h | 2 +- tcg/s390x/tcg-target.c.inc | 36 +- 3 files change

[PULL 30/39] tcg/sparc64: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.h | 2 +- tcg/sparc64/tcg-target.c.inc | 16 ++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index ae2910c4ee.

[PULL 27/39] tcg/i386: Use TEST r,r to test 8/16/32 bits

From: Paolo Bonzini Just like when testing against the sign bits, TEST r,r can be used when the immediate is 0xff, 0xff00, 0x, 0x. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/i386/tcg-ta

[PULL 26/39] tcg/i386: Improve TSTNE/TESTEQ vs powers of two

Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 6 ++-- tcg/i386/tcg-target-con-str.h | 1 + tcg/i386/tcg-target.c.inc | 54 +++ 3 files changed, 53 inserti

[PULL 39/39] tcg/tci: Support TCG_COND_TST{EQ,NE}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 2 +- tcg/tci.c| 14 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 609b2f4e4a..a076f401d2 100644 --- a/tc

[PULL 15/39] target/s390x: Improve general case of disas_jcc

Avoid code duplication by handling 7 of the 14 cases by inverting the test for the other 7 cases. Use TCG_COND_TSTNE for cc in {1,3}. Use (cc - 1) <= 1 for cc in {1,2}. Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/transla

[PULL 32/39] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel

Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 68 1 file changed, 34 insertions

[PULL 04/39] tcg/optimize: Split out do_constant_folding_cond1

Handle modifications to the arguments and condition in a single place. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 57 -- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c

[PULL 06/39] tcg/optimize: Handle TCG_COND_TST{EQ,NE}

Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimi

[PULL 16/39] tcg: Add TCGConst argument to tcg_target_const_match

Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 34 ++-- tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/arm/tcg-ta

[PULL 10/39] target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 566adc4cd6..220eda2137 100644 --- a/target/alpha/translate.c +++

[PULL 23/39] tcg/i386: Pass x86 condition codes to tcg_out_cmov

Hoist the tcg_cond_to_jcc index outside the function. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc ind

[PULL 21/39] tcg/arm: Split out tcg_out_cmp()

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108145244.72421-1-phi...@linaro.org> --- tcg/arm/tcg-target.c

[PULL 33/39] tcg/ppc: Tidy up tcg_target_const_match

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b9323baa86..26e0bc31d7 100644 --- a/tcg/pp

[PULL 05/39] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2

Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 107 ++--- 1 file changed, 57 insertions(+), 50 deleti

[PULL 38/39] tcg/s390x: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 139 + 2 files changed, 97 insertions(+), 44 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 53bed8c8d2..ae448c3a3a 100644 --

[PULL 19/39] tcg/aarch64: Generate TBZ, TBNZ

Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240119224737.48943-2-phi...@linaro.org> Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 74 ++-- 1 file changed, 62 insertions

[PULL 18/39] tcg/aarch64: Massage tcg_out_brcond()

From: Philippe Mathieu-Daudé In order to ease next commit review, modify tcg_out_brcond() to switch over TCGCond. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240119224737.48943-1-phi...@linaro.org> Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-targe

Re: [PATCH v1 01/15] libvhost-user: Fix msg_region->userspace_addr computation

On Sun, Feb 4, 2024 at 9:36 AM David Hildenbrand wrote: > > On 04.02.24 02:35, Raphael Norwitz wrote: > > As a heads up, I've left Nutanix and updated it in MAINTAINERS. Will > > be updating it again shortly so tagging these with my new work email. > > > > Thanks for the fast review! The mail serv

Re: [PATCH v1 11/15] libvhost-user: Speedup gpa_to_mem_region() and vu_gpa_to_va()

On Sun, Feb 4, 2024 at 9:51 AM David Hildenbrand wrote: > > On 04.02.24 03:10, Raphael Norwitz wrote: > > One comment on this one. > > > > On Fri, Feb 2, 2024 at 4:56 PM David Hildenbrand wrote: > >> > >> Let's speed up GPA to memory region / virtual address lookup. Store the > >> memory regions

Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements

On Sat, Feb 3, 2024 at 8:12 PM Akihiko Odaki wrote: > > This series extracts fixes and refactorings that can be applied > independently from "[PATCH v9 00/23] plugins: Allow to read registers". > > The patch "target/riscv: Move MISA limits to class" was replaced with > patch "target/riscv: Move mi

Re: [PATCH 1/3] hw/display : Add device DM163

On Sat, Jan 27, 2024 at 5:38 AM Inès Varhol wrote: > > This device implements the IM120417002 colors shield v1.1 for Arduino > (which relies on the DM163 8x3-channel led driving logic) and features > a simple display of an 8x8 RGB matrix. The columns of the matrix are > driven by the DM163 and the

Re: [PATCH 2/3] hw/arm : Connect DM163 to STM32L4x5

On Sat, Jan 27, 2024 at 7:09 AM Inès Varhol wrote: > > Signed-off-by: Arnaud Minier > Signed-off-by: Inès Varhol Acked-by: Alistair Francis Alistair > --- > hw/arm/Kconfig | 1 + > hw/arm/stm32l4x5_soc.c | 55 +- > include/hw/arm/stm3

Re: [PATCH] target/riscv: FCSR doesn't contain vxrm and vxsat

On Tue, Jan 30, 2024 at 9:10 PM LIU Zhiwei wrote: > > vxrm and vxsat have been moved into a special register vcsr since > RVV v1.0. So remove them from FCSR for vector 1.0. > > Signed-off-by: LIU Zhiwei Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_bits.h | 8 -

Re: [PATCH] target/riscv: Use RISCVException as return type for all csr ops

On Tue, Jan 30, 2024 at 10:49 PM LIU Zhiwei wrote: > > The real return value type has been converted to RISCVException, > but some function declarations still not. This patch makes all > csr operation declarations use RISCVExcetion. > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis A

[PATCH] tests/cdrom-test: Add cdrom test for LoongArch virt machine

The cdrom test skips to execute on LoongArch system with command "make check", this patch enables cdrom test for LoongArch virt machine platform. With this patch, cdrom test passes to run on LoongArch virt machine type. Signed-off-by: Bibo Mao --- tests/qtest/cdrom-test.c | 3 +++ 1 file change

Re: [PATCH] target/riscv: Use RISCVException as return type for all csr ops

On Tue, Jan 30, 2024 at 10:49 PM LIU Zhiwei wrote: > > The real return value type has been converted to RISCVException, > but some function declarations still not. This patch makes all > csr operation declarations use RISCVExcetion. > > Signed-off-by: LIU Zhiwei Thanks! Applied to riscv-to-appl

[PATCH 0/3] target/arm: Split mtedesc from vector desc

This aims to solve an assertion failure in simd_desc() that is triggered by overflowing the 22-bit simd data field, when SVE vectors are configured to be long and MTE is enabled. Gustavo, can you please run this through your test case? I looked back through the irc log and only see the memory-tagg

[PATCH 2/3] target/arm: Move SVE/SME MTE disable checks inward

Signed-off-by: Richard Henderson --- target/arm/tcg/sme_helper.c | 32 +--- target/arm/tcg/sve_helper.c | 76 + 2 files changed, 20 insertions(+), 88 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 904bfdac

[PATCH 1/3] target/arm: Fix SVE/SME gross MTE suppression checks

The TBI and TCMA bits are located within mtedesc, not desc. Signed-off-by: Richard Henderson --- target/arm/tcg/sme_helper.c | 8 target/arm/tcg/sve_helper.c | 12 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg

Re: [PATCH v2 2/2] target/riscv: Support xtheadmaee for thead-c906

On Sun, Feb 4, 2024 at 3:44 PM LIU Zhiwei wrote: > > This patch set fix the regression on kernel pointed by Björn Töpel in > https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html. > > thead-c906 uses some flags in pte [60-63] bits. It has history reasons that > SVPBMT didn't exist whe

Re: [PULL 06/15] tests/qtest/migration: Don't use -cpu max for aarch64

On Fri, Feb 02, 2024 at 10:51:36AM +, Peter Maydell wrote: > On Thu, 1 Feb 2024 at 23:50, Peter Xu wrote: > > > > Fabiano, I think you forgot to reply-to-all.. adding back the list and > > people in the loop. > > > > On Thu, Feb 01, 2024 at 10:12:44AM -0300, Fabiano Rosas wrote: > > > Peter Xu

Re: [PATCH 1/7] hw/riscv/virt-acpi-build.c: fix leak in build_rhct()

On Tue, Jan 23, 2024 at 8:16 AM Daniel Henrique Barboza wrote: > > The 'isa' char pointer isn't being freed after use. > > Issue detected by Valgrind: > > ==38752== 128 bytes in 1 blocks are definitely lost in loss record 3,190 of > 3,884 > ==38752==at 0x484280F: malloc (vg_replace_malloc.c:4

Re: [PATCH 2/7] hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()

On Tue, Jan 23, 2024 at 8:17 AM Daniel Henrique Barboza wrote: > > Use g_autofree in 'dist_matrix' to avoid the manual g_free(). > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/numa.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(

Re: [PATCH 3/7] hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()

On Tue, Jan 23, 2024 at 8:16 AM Daniel Henrique Barboza wrote: > > Move all char pointers to the loop. Use g_autofree in all of them to > avoid the g_free() calls. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 12 +--- > 1

Re: [PATCH 4/7] hw/riscv/virt.c: use g_autofree in create_fdt_sockets()

On Tue, Jan 23, 2024 at 8:16 AM Daniel Henrique Barboza wrote: > > Move 'clust_name' inside the loop, and g_autofree, to avoid having to > g_free() manually in each loop iteration. > > 'intc_phandles' is also g_autofreed to avoid another manual g_free(). > > Signed-off-by: Daniel Henrique Barboza

Re: [PATCH 5/7] hw/riscv/virt.c: use g_autofree in create_fdt_virtio()

On Tue, Jan 23, 2024 at 9:38 AM Daniel Henrique Barboza wrote: > > Put 'name' declaration inside the loop, with g_autofree, to avoid > manually doing g_free() in each iteration. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 5 ++--

Re: [PATCH 6/7] hw/riscv/virt.c: use g_autofree in virt_machine_init()

On Tue, Jan 23, 2024 at 9:38 AM Daniel Henrique Barboza wrote: > > Move 'soc_name' to the loop, and give it g_autofree, to avoid the manual > g_free(). > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 5 ++--- > 1 file changed, 2 ins

Re: [PATCH 7/7] hw/riscv/virt.c: use g_autofree in create_fdt_*

On Tue, Jan 23, 2024 at 8:18 AM Daniel Henrique Barboza wrote: > > We have a lot of cases where a char or an uint32_t pointer is used once > to alloc a string/array, read/written during the function, and then > g_free() at the end. There's no pointer re-use - a single alloc, a > single g_free(). >

Re: [PULL 05/13] linux-user: Use walk_memory_regions for open_self_maps

On 1/26/24 23:52, Richard Purdie wrote: Hi Michael, On Fri, 2024-01-26 at 16:33 +0300, Michael Tokarev wrote: 26.01.2024 16:03, Richard Purdie wrote: I've run into a problem with this change. We (Yocto Project) upgraded to qemu 8.2.0 recently and after that we started seeing errors cross comp

Re: [PATCH 0/7] hw/riscv: fix leak, add more g_autofree

On Tue, Jan 23, 2024 at 9:39 AM Daniel Henrique Barboza wrote: > > Hi, > > First patch fixes a leak found when using Valgrind. The root cause is a > missing g_free() in a string. > > In fact, I found while doing reviews that we keep repeating the same > pattern: > > > char *name; > name = g_s

Re: [PULL 06/14] ci: Add a migration compatibility test job

On Fri, Feb 02, 2024 at 10:47:05AM -0300, Fabiano Rosas wrote: > Peter Maydell writes: > > > On Mon, 29 Jan 2024 at 03:04, wrote: > >> > >> From: Fabiano Rosas > >> > >> The migration tests have support for being passed two QEMU binaries to > >> test migration compatibility. > >> > >> Add a CI

Re: [PATCH 2/2] migration: Fix return-path thread exit

On Fri, Feb 02, 2024 at 12:11:09PM -0300, Fabiano Rosas wrote: > Cédric Le Goater writes: > > > On 2/2/24 15:42, Fabiano Rosas wrote: > >> Cédric Le Goater writes: > >> > >>> In case of error, close_return_path_on_source() can perform a shutdown > >>> to exit the return-path thread. However, i

Re: [PATCH v4 1/2] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS

On Thu, Jan 25, 2024 at 12:04 AM Conor Dooley wrote: > > From: Conor Dooley > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > The conversion from misa_mxl_max to xlen already has one user, so > introduce a he

Re: [PATCH v4 0/2] riscv: support new isa extension detection devicetree properties

On Wed, Jan 24, 2024 at 10:57 PM Conor Dooley wrote: > > From: Conor Dooley > > Making it a series to keep the standalone change to riscv_isa_string() > that Drew reported separate. > > Changes in v4: > - Other than a rebase, add a helper for the mxl_max to xlen conversion > > Changes in v3: > -

Re: [PATCH v2 18/23] migration/multifd: Rewrite multifd_queue_page()

On Fri, Feb 02, 2024 at 05:47:05PM -0300, Fabiano Rosas wrote: > pet...@redhat.com writes: > > > From: Peter Xu > > > > The current multifd_queue_page() is not easy to read and follow. It is not > > good with a few reasons: > > > > - No helper at all to show what exactly does a condition mean;

Re: [PATCH v2 22/23] migration/multifd: Fix MultiFDSendParams.packet_num race

On Fri, Feb 02, 2024 at 06:08:22PM -0300, Fabiano Rosas wrote: > pet...@redhat.com writes: > > > From: Peter Xu > > > > As reported correctly by Fabiano [1], MultiFDSendParams.packet_num is buggy > > to be assigned and stored. Consider two consequent operations of: (1) > > queue a job into multi

Re: Re: [PATCH 0/2] Export debug triggers as an extension

On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones wrote: > > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote: > > > > From memory the "debug" property is for the original debug spec: > > > > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote > > > > > > > > That was

Re: [PATCH v2 19/23] migration/multifd: Cleanup multifd_save_cleanup()

On Fri, Feb 02, 2024 at 05:54:23PM -0300, Fabiano Rosas wrote: > pet...@redhat.com writes: > > > From: Peter Xu > > > > Shrink the function by moving relevant works into helpers: move the thread > > join()s into multifd_send_terminate_threads(), then create two more helpers > > to cover channel/s

Re: [PATCH] linux-user/riscv: Fix sizeof_reg typo in vdso unwind info

On Sat, Jan 13, 2024 at 8:04 AM Richard Henderson wrote: > > Reported-by: Vineet Gupta > Signed-off-by: Richard Henderson Is there a branch with this so I can pull in the binary changes? Alistair > --- > linux-user/riscv/vdso-32.so | Bin 2900 -> 2900 bytes > linux-user/riscv/vdso-64.so | Bi

Re: [PATCH v2 23/23] migration/multifd: Optimize sender side to be lockless

On Fri, Feb 02, 2024 at 06:34:08PM -0300, Fabiano Rosas wrote: > pet...@redhat.com writes: > > > From: Peter Xu > > > > When reviewing my attempt to refactor send_prepare(), Fabiano suggested we > > try out with dropping the mutex in multifd code [1]. > > > > I thought about that before but I nev

Re: Re: [PATCH 0/2] Export debug triggers as an extension

On Mon, Feb 5, 2024 at 9:36 AM Alistair Francis wrote: > > On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones wrote: > > > > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote: > > > > > From memory the "debug" property is for the original debug spec: > > > > > https://github.com/riscv/ri

Re: [PATCH] linux-user/riscv: Fix sizeof_reg typo in vdso unwind info

On 2/5/24 14:33, Alistair Francis wrote: On Sat, Jan 13, 2024 at 8:04 AM Richard Henderson wrote: Reported-by: Vineet Gupta Signed-off-by: Richard Henderson Is there a branch with this so I can pull in the binary changes? Already merged as commit 1b21fe27e75a59bfe2513f5abcc6a18cfc35cfc8

Re: [PATCH 1/5] migration/multifd: Join the TLS thread

On Fri, Feb 02, 2024 at 04:11:24PM -0300, Fabiano Rosas wrote: > We're currently leaking the resources of the TLS thread by not joining > it and also overwriting the p->thread pointer altogether. > > Signed-off-by: Fabiano Rosas Reviewed-by: Peter Xu Does this deserve below? Fixes: a1af605bd5

Re: [PATCH 2/5] migration/multifd: Remove p->running

On Fri, Feb 02, 2024 at 04:11:25PM -0300, Fabiano Rosas wrote: > We currently only need p->running to avoid calling qemu_thread_join() > on a non existent thread if the thread has never been created. > > However, there are at least two bugs in this logic: > > 1) On the sending side, p->running is

Re: [PATCH] ppc/pnv: Add PowerPC Special Purpose Registers

On Thu, 18 Jan 2024 12:27:12 +1000, Nicholas Piggin wrote: > On Thu Jan 18, 2024 at 8:34 AM AEST, dan tan wrote: >>The handling of the following two registers are added - >>DAWR1 (0x0bd, 189) - Data Address Watchpoint 1 >>DAWRX1 (0x0b5, 181) - Data Address Watchpoin

Re: [PATCH 3/5] migration/multifd: Move multifd_save_setup error handling in to the function

On Fri, Feb 02, 2024 at 04:11:26PM -0300, Fabiano Rosas wrote: > Hide the error handling inside multifd_save_setup to make it cleaner > for the next patch to move the function around. > > Signed-off-by: Fabiano Rosas Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH 4/5] migration/multifd: Move multifd_save_setup into migration thread

On Fri, Feb 02, 2024 at 04:11:27PM -0300, Fabiano Rosas wrote: > We currently have an unfavorable situation around multifd channels > creation and the migration thread execution. > > We create the multifd channels with qio_channel_socket_connect_async > -> qio_task_run_in_thread, but only connect

Re: Re: [PATCH 0/2] Export debug triggers as an extension

On Mon, Feb 5, 2024 at 2:50 PM Anup Patel wrote: > > On Mon, Feb 5, 2024 at 9:36 AM Alistair Francis wrote: > > > > On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones > > wrote: > > > > > > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote: > > > > > > From memory the "debug" property

Re: [PATCH v4 0/4] target/riscv: SMBIOS support for RISC-V virt machine

On Wed, Jan 24, 2024 at 4:44 AM Heinrich Schuchardt wrote: > > Generate SMBIOS tables for the RISC-V mach-virt. > Add CONFIG_SMBIOS=y to the RISC-V default config. > > With the series the following firmware tables are provided: > > etc/smbios/smbios-anchor > etc/smbios/smbios-tables > > Ad

Re: [PATCH 3/6] target/riscv: add remaining named features

On Fri, Feb 2, 2024 at 7:44 PM Daniel Henrique Barboza wrote: > > > > On 2/1/24 23:14, Alistair Francis wrote: > > On Thu, Feb 1, 2024 at 5:15 AM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 1/29/24 22:10, Alistair Francis wrote: > >>> On Fri, Jan 26, 2024 at 5:54 AM Daniel Henrique

Re: [PATCH] target/riscv: Enable xtheadsync under user mode

On Sun, Feb 4, 2024 at 3:53 PM LIU Zhiwei wrote: > > According to xtheadsync[1][2] documentation, it can be used in user mode and > the behavior is same with other priviledges. > > [1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsync/sync.adoc > [2]:https://github.com/T-h

Re: [PATCH 5/5] migration/multifd: Add a synchronization point for channel creation

On Fri, Feb 02, 2024 at 04:11:28PM -0300, Fabiano Rosas wrote: > It is possible that one of the multifd channels fails to be created at > multifd_new_send_channel_async() while the rest of the channel > creation tasks are still in flight. > > This could lead to multifd_save_cleanup() executing the

Re: [PATCH] target/riscv: Enable xtheadsync under user mode

On Sun, Feb 4, 2024 at 3:53 PM LIU Zhiwei wrote: > > According to xtheadsync[1][2] documentation, it can be used in user mode and > the behavior is same with other priviledges. > > [1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsync/sync.adoc > [2]:https://github.com/T-h

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