On Mon, 22 Jan 2024 at 12:27, Stefan Hajnoczi wrote:
>
> Requests that complete in an IOThread use irqfd to notify the guest
> while requests that complete in the main loop thread use the traditional
> qdev irq code path. The reason for this conditional is that the irq code
> path requires the BQL
On Tue, Jan 30, 2024 at 10:39:51PM +0530, Ani Sinha wrote:
>
>
> > On 30-Jan-2024, at 22:17, Daniel P. Berrangé wrote:
> >
> > On Tue, Jan 30, 2024 at 10:14:28PM +0530, Ani Sinha wrote:
> >> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to
> >> allow up to 4096 vCPUs")
> >
From: Dongwon Kim
UI size is set to 0 when the VC is invisible, which will prevent
the further scanout update by notifying the guest that the display
is not in active state. Then it is restored to the original size
whenever the VC becomes visible again.
Cc: Marc-André Lureau
Cc: Gerd Hoffmann
From: Dongwon Kim
Adding a callback for window-state-event that resets the flag, 'visible'
when associated window is minimized or restored. When minimizing, it cancels
any of queued draw events associated with the VC.
Cc: Marc-André Lureau
Cc: Gerd Hoffmann
Cc: Vivek Kasireddy
Signed-off-by:
From: Dongwon Kim
A new flag "visible" is added to show visibility status of the gfx console.
The flag is set to 'true' when the VC is visible but set to 'false' when
it is hidden or closed. When the VC is invisible, drawing guest frames
should be skipped as it will never be completed and it woul
From: Dongwon Kim
Drawing guest display frames can't be completed while the VC is not in
visible state, which could result in timeout in both the host and the
guest especially when using blob scanout. Therefore it is needed to
update and track the visiblity status of the VC and unblock the pipeli
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the
calling thread, and not the entire process. Therefore, implement it
using a syscall, and not a libc call.
Cc: qemu-sta...@nongnu.org
Fixes: 19b84f3c35d7 ("added setgroups and getgroups syscalls")
Signed-off-by: Ilya Leoshkevich
---
From: Hao Wu
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Squashed IRQ Implementation patch into this one for compliation.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Br
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest/
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 37 +++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 37 insertions(+), 2 deletio
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP N
From: Nabih Estefan Diaz
[Changes since v15]
Dropped PCI MBox patches. They were presenting a lot of problems with
endianness and are not directly related to the GMAC. Breaking them apart to
debug separately and let the GMAC itself be upstreamed faster.
[Changes since v14]
Expanded comment on
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff -
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest/
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 37 +++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 37 insertions(+), 2 deletio
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
Added relevant trace-events
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff -
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP N
From: Nabih Estefan Diaz
[Changes since v15]
Dropped PCI MBox patches. They were presenting a lot of problems with
endianness and are not directly related to the GMAC. Breaking them apart to
debug separately and let the GMAC itself be upstreamed faster.
[Changes since v14]
Expanded comment on
From: Hao Wu
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Squashed IRQ Implementation patch into this one for compliation.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Br
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> Dear QEMU and KVM communities,
> QEMU will apply for the Google Summer of Code and Outreachy internship
When MTE3 is supported, the kernel maps
PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
to
MTE_CTRL_TCF_ASYMM
and from there to
SCTLR_EL1.TCF0 = 3
There is no error reported for setting ASYNC | SYNC
when MTE3 is not supported; the kernel simply selects
the ASYNC behavior of TCG0=2.
Signed-off-by: Richar
On Wed, Jan 31, 2024 at 10:30 AM Palmer Dabbelt wrote:
>
> On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
> > On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
> >>
> >> On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> >> > Dear QEMU and KVM communities
On Tue, Jan 30, 2024 at 07:06:40PM +, “William Roche wrote:
> From: William Roche
>
> A memory page poisoned from the hypervisor level is no longer readable.
> The migration of a VM will crash Qemu when it tries to read the
> memory address space and stumbles on the poisoned page with a simil
On Tue, 30 Jan 2024 17:26:11 PST (-0800), alistai...@gmail.com wrote:
On Wed, Jan 31, 2024 at 10:30 AM Palmer Dabbelt wrote:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
> On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
>>
>> On Mon, 15 Jan 2024 08:32:59 PST (-0800)
> -Original Message-
> From: Peter Xu
> Sent: Tuesday, January 30, 2024 6:32 PM
> To: Liu, Yuan1
> Cc: faro...@suse.de; leob...@redhat.com; qemu-devel@nongnu.org; Zou,
> Nanhai
> Subject: Re: [PATCH v3 0/4] Live Migration Acceleration with IAA
> Compression
>
> On Tue, Jan 30, 2024 at 0
Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allow up
to 4096 vCPUs")
Linux kernel can support upto a maximum number of 4096 vCPUS when MAXSMP is
enabled in the kernel. At present, QEMU has been tested to correctly boot a
linux guest with 1856 vcpus and no more both with e
On Tue, Jan 30, 2024 at 10:58:24AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Jan 29, 2024 at 10:44:46AM -0300, Fabiano Rosas wrote:
> >> > Since we're at it, I would also like to know how you think about whether
> >> > we
> >> > should still suggest people using VMSD versionin
On Tue, Jan 30, 2024 at 7:00 AM Manos Pitsidianakis <
manos.pitsidiana...@linaro.org> wrote:
> When the Rutabaga GPU device frees resources, it calls
> rutabaga_resource_unref for that resource_id. However, when the generic
> VirtIOGPU functions destroys resources, it only removes the
> virtio_gpu
On Fri, Jan 26, 2024 at 6:23 AM Alyssa Ross wrote:
> Gurchetan Singh writes:
>
> > On Sat, Jan 20, 2024 at 4:19 AM Alyssa Ross wrote:
> >
> >> Gurchetan Singh writes:
> >>
> >> > On Fri, Jan 19, 2024 at 1:13 PM Alyssa Ross wrote:
> >> >>
> >> >> Hi Gurchetan,
> >> >>
> >> >> > Thanks for the
Hi Philippe:
When developing libvirt on loongarch, we encountered some problems
related to pflash.
libvirt and qemu met some difficulties in the coordination of UEFI loading.
I think we need your suggestions and opinions on the solution.
Anyway, I fetched and installed this. The firmwa
On Fri, Jan 19, 2024 at 04:35:08PM +, Peter Maydell wrote:
> Date: Fri, 19 Jan 2024 16:35:08 +
> From: Peter Maydell
> Subject: [PATCH 1/5] pci: Switch bus reset to 3-phase-reset
> X-Mailer: git-send-email 2.34.1
>
> Switch the PCI bus from using BusClass::reset to the Resettable
> interf
On Fri, Jan 19, 2024 at 04:35:10PM +, Peter Maydell wrote:
> Date: Fri, 19 Jan 2024 16:35:10 +
> From: Peter Maydell
> Subject: [PATCH 3/5] adb: Switch bus reset to 3-phase-reset
> X-Mailer: git-send-email 2.34.1
>
> Switch the ADB bus from using BusClass::reset to the Resettable
> interf
On Fri, Jan 19, 2024 at 04:35:09PM +, Peter Maydell wrote:
> Date: Fri, 19 Jan 2024 16:35:09 +
> From: Peter Maydell
> Subject: [PATCH 2/5] vmbus: Switch bus reset to 3-phase-reset
> X-Mailer: git-send-email 2.34.1
>
> Switch vmbus from using BusClass::reset to the Resettable interface.
>
On Fri, Jan 19, 2024 at 04:35:11PM +, Peter Maydell wrote:
> Date: Fri, 19 Jan 2024 16:35:11 +
> From: Peter Maydell
> Subject: [PATCH 4/5] hw/s390x/css-bridge: switch virtual-css bus to
> 3-phase-reset
> X-Mailer: git-send-email 2.34.1
>
> Switch the s390x virtual-css bus from using Bus
On Fri, Jan 19, 2024 at 04:35:12PM +, Peter Maydell wrote:
> Date: Fri, 19 Jan 2024 16:35:12 +
> From: Peter Maydell
> Subject: [PATCH 5/5] hw/core: Remove transitional infrastructure from
> BusClass
> X-Mailer: git-send-email 2.34.1
>
> BusClass currently has transitional infrastructure
Hi Ani,
On Wed, Jan 31, 2024 at 08:19:06AM +0530, Ani Sinha wrote:
> Date: Wed, 31 Jan 2024 08:19:06 +0530
> From: Ani Sinha
> Subject: [PATCH v2] pc: q35: Bump max_cpus to 1856 vcpus
> X-Mailer: git-send-email 2.42.0
>
> Since commit f10a570b093e6 ("KVM: x86: Add CONFIG_KVM_MAX_NR_VCPUS to allo
On Tue, Jan 30, 2024 at 06:23:10PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Tue, Jan 30, 2024 at 10:18:07AM +, Peter Maydell wrote:
> >> On Mon, 29 Jan 2024 at 23:31, Fabiano Rosas wrote:
> >> >
> >> > Fabiano Rosas writes:
> >> >
> >> > > Peter Xu writes:
> >> > >
> >> > >>
On Tue, Jan 30, 2024 at 06:32:21PM -0300, Fabiano Rosas wrote:
> Avihai Horon writes:
>
> > On 29/01/2024 16:34, Fabiano Rosas wrote:
> >> External email: Use caution opening links or attachments
> >>
> >>
> >> Avihai Horon writes:
> >>
> >>> Currently, multifd channels are created asynchronousl
On 1/30/24 21:11, LIU Zhiwei wrote:
+/* This stub just works for making vendors array not empty */
+riscv_csr_operations stub_csr_ops[CSR_TABLE_SIZE];
+static inline bool never_p(const RISCVCPUConfig *cfg)
+{
+return false;
+}
+
+void riscv_tcg_cpu_register_vendor_csr(RISCVCPU *cpu)
+{
+s
On 1/30/24 21:11, LIU Zhiwei wrote:
+riscv_csr_operations th_csr_ops[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+[CSR_TH_MXSTATUS] = { "th_mxstatus", th_maee_check, read_th_mxstatus,
+write_th_mxstatus},
+#endif /* !CONF
On Wed, Jan 31, 2024 at 9:27 AM Zhao Liu wrote:
>
> Hi Ani,
>
> On Wed, Jan 31, 2024 at 08:19:06AM +0530, Ani Sinha wrote:
> > Date: Wed, 31 Jan 2024 08:19:06 +0530
> > From: Ani Sinha
> > Subject: [PATCH v2] pc: q35: Bump max_cpus to 1856 vcpus
> > X-Mailer: git-send-email 2.42.0
> >
> > Since c
On 30/01/2024 17.13, Arnaud Minier wrote:
Tests:
- the ability to change the sysclk of the device
- the ability to enable/disable/configure the PLLs
- if the clock multiplexers work
- the register flags and the generation of irqs
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
te
On 2024/1/31 13:06, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+/* This stub just works for making vendors array not empty */
+riscv_csr_operations stub_csr_ops[CSR_TABLE_SIZE];
+static inline bool never_p(const RISCVCPUConfig *cfg)
+{
+ return false;
+}
+
+void riscv_tcg_
On 29/01/2024 17.44, Philippe Mathieu-Daudé wrote:
Do not accept any Object for CPUArchId::cpu field,
restrict it to CPUState type.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/boards.h| 2 +-
hw/core/machine.c | 4 ++--
hw/i386/x86.c | 2 +-
hw/loonga
On 2024/1/31 13:07, Richard Henderson wrote:
On 1/30/24 21:11, LIU Zhiwei wrote:
+riscv_csr_operations th_csr_ops[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+ [CSR_TH_MXSTATUS] = { "th_mxstatus", th_maee_check,
read_th_mxstatus,
+ write_th_mxstatus},
+#endif /* !CONFIG_USER_O
On Wed, Jan 31, 2024 at 10:47:29AM +0530, Ani Sinha wrote:
> Date: Wed, 31 Jan 2024 10:47:29 +0530
> From: Ani Sinha
> Subject: Re: [PATCH v2] pc: q35: Bump max_cpus to 1856 vcpus
>
> On Wed, Jan 31, 2024 at 9:27 AM Zhao Liu wrote:
> >
> > Hi Ani,
> >
> > On Wed, Jan 31, 2024 at 08:19:06AM +0530
On 26/01/2024 18.25, David Woodhouse wrote:
From: David Woodhouse
Some callers instantiate the device unconditionally, others will do so only
if there is a NICInfo to go with it. This appears to be fairly random, but
preseve the existing behaviour for now.
Signed-off-by: David Woodhouse
---
On 26/01/2024 18.25, David Woodhouse wrote:
From: David Woodhouse
Also update the test to specify which device to attach the test socket
to, and remove the comment lamenting the fact that we can't do so.
Signed-off-by: David Woodhouse
---
hw/arm/npcm7xx.c | 16 +---
Hi Dongwon
On Wed, Jan 31, 2024 at 3:50 AM wrote:
>
> From: Dongwon Kim
>
> A new flag "visible" is added to show visibility status of the gfx console.
> The flag is set to 'true' when the VC is visible but set to 'false' when
> it is hidden or closed. When the VC is invisible, drawing guest fra
Hi
On Wed, Jan 31, 2024 at 3:50 AM wrote:
>
> From: Dongwon Kim
>
> UI size is set to 0 when the VC is invisible, which will prevent
> the further scanout update by notifying the guest that the display
> is not in active state. Then it is restored to the original size
> whenever the VC becomes v
On Tue, Jan 30, 2024 at 12:11:47PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Jan 29, 2024 at 09:42:24AM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Fri, Jan 26, 2024 at 07:19:39PM -0300, Fabiano Rosas wrote:
> >> >> +static MultiFDMethods multifd_socket_o
It seems that tcg_reg_alloc_op() set const_args[i] wrong value
when instructions imm is 0. The LoongArch tcg_out_vec_op() cmp_vec
use the wrong const_args[2].
e.g
The wrong const_args[2] is 0.
IN: vslti.w v5, v4, 0x0 OUT: vslt.w v1, v1, v0
The right const_args[2] is 1.
IN: vslti.w v
On 1/26/24 19:14, Alex Bennée wrote:
+need_realloc = TRUE;
+}
+plugin.scoreboard_size = cpu->cpu_index + 1;
+g_assert(plugin.scoreboard_size <= plugin.scoreboard_alloc_size);
+
+if (g_hash_table_size(plugin.scoreboards) == 0) {
+/* nothing to do, we just updated si
On 1/31/24 01:18, Ilya Leoshkevich wrote:
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the
calling thread, and not the entire process. Therefore, implement it
using a syscall, and not a libc call.
Cc: qemu-sta...@nongnu.org
Fixes: 19b84f3c35d7 ("added setgroups and getgroups sys
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