[PATCH 0/2] hw/block/block.c: improve confusing error

In cases where a device tries to read more bytes than the block device contains with the blk_check_size_and_read_all() function, the error is vague: "device requires X bytes, block backend provides Y bytes". This patch changes the errors of this function to include the block backend name, the de

[PATCH 1/2] hw/core/qdev.c: add qdev_get_human_name()

Add a simple method to return some kind of human readable identifier for use in error messages. Signed-off-by: Manos Pitsidianakis --- hw/core/qdev.c | 10 ++ include/hw/qdev-core.h | 15 +++ 2 files changed, 25 insertions(+) diff --git a/hw/core/qdev.c b/hw/core/qde

Re: [PATCH v2 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Hi Inès, On 22/1/24 22:02, Inès Varhol wrote: Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 79 -- include/hw/arm/stm32l4x5_soc.h | 2 + 3 files changed, 69 insertions(+

[PATCH 2/2] hw/block/block.c: improve confusing blk_check_size_and_read_all() error

In cases where a device tries to read more bytes than the block device contains, the error is vague: "device requires X bytes, block backend provides Y bytes". This patch changes the errors of this function to include the block backend name, the device id and device type name where appropriate. S

Re: [PATCH 2/2] hw/block/block.c: improve confusing blk_check_size_and_read_all() error

On 23/1/24 09:09, Manos Pitsidianakis wrote: In cases where a device tries to read more bytes than the block device contains, the error is vague: "device requires X bytes, block backend provides Y bytes". This patch changes the errors of this function to include the block backend name, the devic

Re: [PATCH 1/2] hw/core/qdev.c: add qdev_get_human_name()

Hi Manos, On 23/1/24 09:09, Manos Pitsidianakis wrote: Add a simple method to return some kind of human readable identifier for use in error messages. Signed-off-by: Manos Pitsidianakis --- hw/core/qdev.c | 10 ++ include/hw/qdev-core.h | 15 +++ 2 files changed

Re: [PATCH 1/2] hw/core/qdev.c: add qdev_get_human_name()

On Tue, 23 Jan 2024 10:13, Philippe Mathieu-Daudé wrote: Hi Manos, On 23/1/24 09:09, Manos Pitsidianakis wrote: Add a simple method to return some kind of human readable identifier for use in error messages. Signed-off-by: Manos Pitsidianakis --- hw/core/qdev.c | 10 ++ in

Re: [PATCH v3 01/21] hw/riscv: Use misa_mxl instead of misa_mxl_max

On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote: > From: Akihiko Odaki > > The effective MXL value matters when booting. I'd prefer this commit message get some elaboration. riscv_is_32bit() is used in a variety of contexts, some where it should be reporting the max misa.mxl. However

[PATCH v2] mailmap: Fix Stefan Weil email

Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email") corrected authorship for patch received at qemu-devel@nongnu.org, correct now for patch received at qemu-triv...@nongnu.org. Update other authorship email for Stefan's commits. Suggested-by: Stefan Weil Fixes: d819fc9516 ("virtio-blk: F

Re: [PATCH] Make 'uri' optional for migrate QAPI

On Tue, Jan 23, 2024 at 06:42:19AM +, Het Gala wrote: > 'uri' argument should be optional, as 'uri' and 'channels' > arguments are mutally exclusive in nature. > > Fixes: 074dbce5fcce (migration: New migrate and > migrate-incoming argument 'channels') > Signed-off-by: Het Gala > --- > qapi/m

Re: [PATCH 1/2] hw/core/qdev.c: add qdev_get_human_name()

On 23/1/24 09:15, Manos Pitsidianakis wrote: On Tue, 23 Jan 2024 10:13, Philippe Mathieu-Daudé wrote: Hi Manos, On 23/1/24 09:09, Manos Pitsidianakis wrote: Add a simple method to return some kind of human readable identifier for use in error messages. Signed-off-by: Manos Pitsidianakis ---

Re: [PATCH v3 3/4] target/riscv: SMBIOS support for RISC-V virt machine

On Mon, Jan 22, 2024 at 02:07:57PM +0100, Heinrich Schuchardt wrote: > Generate SMBIOS tables for the RISC-V mach-virt. > Add CONFIG_SMBIOS=y to the RISC-V default config. > Set the default processor family in the type 4 table. > > The implementation is based on the corresponding ARM and Loongson

Re: [PATCH rfcv1 6/6] intel_iommu: add a framework to check and sync host IOMMU cap/ecap

On 1/15/24 11:13, Zhenzhong Duan wrote: From: Yi Liu Add a framework to check and synchronize host IOMMU cap/ecap with vIOMMU cap/ecap. Currently only stage-2 translation is supported which is backed by shadow page table on host side. So we don't need exact matching of each bit of cap/ecap bet

[Stable-7.2.9 16/20] hw/pflash: implement update buffer for block writes

From: Gerd Hoffmann Add an update buffer where all block updates are staged. Flush or discard updates properly, so we should never see half-completed block writes in pflash storage. Drop a bunch of FIXME comments ;) Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID:

[Stable-7.2.9 14/20] hw/pflash: refactor pflash_data_write()

From: Gerd Hoffmann Move the offset calculation, do it once at the start of the function and let the 'p' variable point directly to the memory location which should be updated. This makes it simpler to update other buffers than pfl->storage in an upcoming patch. No functional change. Signed-of

[Stable-7.2.9 20/20] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued

From: Mark Cave-Ayland Even though the BLAST command isn't fully implemented in QEMU, the DMA_STAT_BCMBLT bit should be set after the command has been issued to indicate that the command has completed. This fixes an issue with the DC390 DOS driver which issues the BLAST command as part of its n

[Stable-7.2.9 11/20] target/i386: Do not re-compute new pc with CF_PCREL

From: Richard Henderson With PCREL, we have a page-relative view of EIP, and an approximation of PC = EIP+CSBASE that is good enough to detect page crossings. If we try to recompute PC after masking EIP, we will mess up that approximation and write a corrupt value to EIP. We already handled mas

[Stable-7.2.9 13/20] target/i386: pcrel: store low bits of physical address in data[0]

From: Paolo Bonzini For PC-relative translation blocks, env->eip changes during the execution of a translation block, Therefore, QEMU must be able to recover an instruction's PC just from the TranslationBlock struct and the instruction data with. Because a TB will not span two pages, QEMU stores

[Stable-7.2.9 12/20] target/i386: fix incorrect EIP in PC-relative translation blocks

From: guoguangyao The PCREL patches introduced a bug when updating EIP in the !CF_PCREL case. Using s->pc in func gen_update_eip_next() solves the problem. Cc: qemu-sta...@nongnu.org Fixes: b5e0d5d22fbf ("target/i386: Fix 32-bit wrapping of pc/eip computation") Signed-off-by: guoguangyao Review

[Stable-7.2.9 00/20] Patch Round-up for stable 7.2.9, freeze on 2024-01-27

The following patches are queued for QEMU stable v7.2.9: https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2 Patch freeze is 2024-01-27, and the release is planned for 2024-01-29: https://wiki.qemu.org/Planning/7.2 Please respond here or CC qemu-sta...@nongnu.org on any additional pa

[Stable-7.2.9 15/20] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p

From: Gerd Hoffmann Use the helper functions we have to read/write multi-byte values in correct byte order. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240108160900.104835-3-kra...@redhat.com> Signed-off-by: Philippe Mat

[Stable-7.2.9 10/20] target/i386: Fix 32-bit wrapping of pc/eip computation

From: Richard Henderson In 32-bit mode, pc = eip + cs_base is also 32-bit, and must wrap. Failure to do so results in incorrect memory exceptions to the guest. Before 732d548732ed, this was implicitly done via truncation to target_ulong but only in qemu-system-i386, not qemu-system-x86_64. To fi

[Stable-7.2.9 09/20] load_elf: fix iterator's type for elf file processing

From: Anastasia Belova j is used while loading an ELF file to byteswap segments' data. If data is larger than 2GB an overflow may happen. So j should be elf_word. This commit fixes a minor bug: it's unlikely anybody is trying to load ELF files with 2GB+ segments for wrong-endianness targets, but

[Stable-7.2.9 18/20] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources

From: Mark Cave-Ayland The am53c974/dc390 PCI interrupt has two separate sources: the first is from the internal ESP device, and the second is from the PCI DMA transfer logic. Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather than driving the PCI IRQ directly, and introduc

[Stable-7.2.9 19/20] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt

From: Mark Cave-Ayland The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to generate an interrupt, however the Linux driver manually checks for DMA_STAT_DONE being set and if it is, considers that a DMA transfer has completed. If DMA_STAT_DONE is set but the ESP device

[Stable-7.2.9 17/20] hw/scsi/esp-pci: use correct address register for PCI DMA transfers

From: Mark Cave-Ayland The current code in esp_pci_dma_memory_rw() sets the DMA address to the value of the DMA_SPA (Starting Physical Address) register which is incorrect: this means that for each callback from the SCSI layer the DMA address is set back to the starting address. In the case wher

Re: [PATCH 4/8] hw/arm/aspeed/2400: Check for CPU types in machine_run_board_init()

On 1/23/24 07:38, Philippe Mathieu-Daudé wrote: Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/ar

Re: [PATCH 5/8] hw/arm/aspeed/2500: Check for CPU types in machine_run_board_init()

On 1/23/24 07:38, Philippe Mathieu-Daudé wrote: Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed.c | 14 ++ 1 file changed, 14 insertions(+) diff --git

RE: [PATCH rfcv1 2/6] hw/pci: introduce pci_device_set/unset_iommu_device()

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH rfcv1 2/6] hw/pci: introduce >pci_device_set/unset_iommu_device() > >On 1/23/24 07:37, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Cédric Le Goater >>> Subject: Re: [PATCH rfcv1 2/6] hw/pci: intro

Re: [PATCH 6/8] hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()

On 1/23/24 07:38, Philippe Mathieu-Daudé wrote: Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index df627096d

Re: [PATCH 6/8] hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()

On 1/23/24 10:27, Cédric Le Goater wrote: On 1/23/24 07:38, Philippe Mathieu-Daudé wrote: Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Signed-off-by: Philippe Mathieu-Daudé ---   hw/arm/aspeed.c | 12   1 file changed, 12 insertions(+) diff --git a/hw/arm

Re: [PATCH 1/3] virtio_iommu: Clear IOMMUPciBus pointer cache when system reset

On 1/22/24 07:40, Zhenzhong Duan wrote: IOMMUPciBus pointer cache is indexed by bus number, bus number may not always be a fixed value, i.e., guest reboot to different kernel which set bus number with different algorithm. This could lead to endpoint binding to wrong iommu MR in virtio_iommu_get_

Re: [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level

Hi Xiaoyao, On Thu, Jan 11, 2024 at 11:19:34AM +0800, Xiaoyao Li wrote: > Date: Thu, 11 Jan 2024 11:19:34 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with > specific topology level > > On 1/8/2024 4:27 PM, Zhao Liu wrote: > > From: Zhao Liu > >

RE: [PATCH rfcv1 3/6] intel_iommu: add set/unset_iommu_device callback

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH rfcv1 3/6] intel_iommu: add set/unset_iommu_device >callback > >On 1/15/24 11:13, Zhenzhong Duan wrote: >> From: Yi Liu >> >> This adds set/unset_iommu_device() implementation in Intel vIOMMU. >> In set call, IOMMUFDDevice

RE: [PATCH rfcv1 4/6] vfio: initialize IOMMUFDDevice and pass to vIOMMU

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH rfcv1 4/6] vfio: initialize IOMMUFDDevice and pass to >vIOMMU > >On 1/15/24 11:13, Zhenzhong Duan wrote: >> Initialize IOMMUFDDevice in vfio and pass to vIOMMU, so that vIOMMU >> could get hw IOMMU information. >> >> In VFI

[PATCH v4] Handle wrap around in limit calculation

Hanlde wrap around when calculating the viewport size caused by the fact that perior to version 460A the limit variable was 32bit quantity and not 64 bits quantity. In the i.MX 6Dual/6Quad Applications Processor Reference Manual document on which the original code was based upon

RE: [PATCH rfcv1 6/6] intel_iommu: add a framework to check and sync host IOMMU cap/ecap

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH rfcv1 6/6] intel_iommu: add a framework to check and >sync host IOMMU cap/ecap > >On 1/15/24 11:13, Zhenzhong Duan wrote: >> From: Yi Liu >> >> Add a framework to check and synchronize host IOMMU cap/ecap with >> vIOMMU ca

RE: [PATCH 1/3] virtio_iommu: Clear IOMMUPciBus pointer cache when system reset

>-Original Message- >From: Cédric Le Goater >Subject: Re: [PATCH 1/3] virtio_iommu: Clear IOMMUPciBus pointer cache >when system reset > >On 1/22/24 07:40, Zhenzhong Duan wrote: >> IOMMUPciBus pointer cache is indexed by bus number, bus number >> may not always be a fixed value, i.e., gu

[PATCH] util/cutil: Allow relocatable install with prefix /

When configuring QEMU with --prefix=/, the generated QEMU executables can't be relocated to other directories. Add an additional test logic in starts_with_prefix() to handle this. Signed-off-by: Bin Meng --- util/cutils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/ut

Re: [PATCH rfcv1 1/6] backends/iommufd_device: introduce IOMMUFDDevice

On 1/19/24 08:31, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Eric Auger >> Subject: Re: [PATCH rfcv1 1/6] backends/iommufd_device: introduce >> IOMMUFDDevice >> >> >> >> On 1/15/24 11:13, Zhenzhong Duan wrote: >>> IOMMUFDDevice represents a device in iommufd and can be used

Re: [PATCH rfcv1 2/6] hw/pci: introduce pci_device_set/unset_iommu_device()

On 1/23/24 10:25, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Cédric Le Goater >> Subject: Re: [PATCH rfcv1 2/6] hw/pci: introduce >> pci_device_set/unset_iommu_device() >> >> On 1/23/24 07:37, Duan, Zhenzhong wrote: >>> -Original Message- From: Cédric Le G

[PULL v2 3/8] linux-user: Fixed cpu restore with pc 0 on SIGBUS

From: Robbin Ehn Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler) introduced a bug, when returning from host_sigbus_handler the PC is never set. Thus cpu_loop_exit_restore is called with a zero PC and we immediate get a SIGSEGV. Signed-off-by: Robbin Ehn Fixes: f4e1168198 ("

[PULL v2 0/8] tcg pach queue

2:16 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240123 for you to fetch changes up to 9f6523e8e4689cafdbed7c10b7cf7c775b5a607b: tcg/arm: Fix SIGILL in tcg_out_qemu_st_direct (2024-01-23 13:3

[PULL v2 1/8] tcg: Remove unreachable code

From: Samuel Tardieu The `fail_rx`/`fail` block is only entered while `buf_rx` is equal to its initial value `MAP_FAILED`. The `munmap(buf_rx, size);` was never executed. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2030 Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Messa

[PULL v2 5/8] linux-user/riscv: Adjust vdso signal frame cfa offsets

A typo in sizeof_reg put the registers at the wrong offset. Simplify the expressions to use positive addresses from the start of uc_mcontext instead of negative addresses from the end of uc_mcontext. Reported-by: Vineet Gupta Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Si

[PULL v2 6/8] linux-user/elfload: test return value of getrlimit

From: Thomas Weißschuh Should getrlimit() fail the value of dumpsize.rlimit_cur may not be initialized. Avoid reading garbage data by checking the return value of getrlimit. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Thomas Weißschuh Message-Id: <2024012

[PULL v2 2/8] tcg: Make the cleanup-on-error path unique

From: Samuel Tardieu By calling `error_setg_errno()` before jumping to the cleanup-on-error path at the `fail` label, the cleanup path is clearer. Signed-off-by: Samuel Tardieu Reviewed-by: Peter Maydell Message-Id: <20231219182212.455952-3-...@rfc1149.net> Signed-off-by: Richard Henderson --

[PULL v2 4/8] tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns

While the format names the second vector register 'v3', it is still in the second position (bits 12-15) and the argument to RXB must match. Example error: - e7 00 00 10 2a 33 verllf %v16,%v0,16 + e7 00 00 10 2c 33 verllf %v16,%v16,16 Cc: qemu-sta...@nongnu.org Reported-by: Mic

[PULL v2 7/8] linux-user/elfload: check PR_GET_DUMPABLE before creating coredump

From: Thomas Weißschuh A process can opt-out of coredump creation by calling prctl(PR_SET_DUMPABLE, 0). linux-user passes this call from the guest through to the operating system. >From there it can be read back again to avoid creating coredumps from qemu-user itself if the guest chose so. Revie

[PULL v2 8/8] tcg/arm: Fix SIGILL in tcg_out_qemu_st_direct

From: Joseph Burt When tcg_out_qemu_st_{index,direct} were merged, the direct case for MO_64 was omitted, causing qemu_st_i64 to be encoded as 0x due to underflow when adding h.base and h.index. Fixes: 1df6d611bdc2 ("tcg/arm: Introduce HostAddress") Signed-off-by: Joseph Burt Message-Id

Re: [PATCH 2/5] util/uri: Simplify uri_string_unescape()

Il lun 22 gen 2024, 20:18 Thomas Huth ha scritto: > uri_string_unescape() basically does the same as the glib function > g_uri_unescape_string(), with just an additional length parameter. > You can replace it altogether with g_uri_unescape_segment. Paolo So we can simplify this function a lot

[Stable-8.1.5 18/24] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p

From: Gerd Hoffmann Use the helper functions we have to read/write multi-byte values in correct byte order. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240108160900.104835-3-kra...@redhat.com> Signed-off-by: Philippe Mat

[Stable-8.1.5 13/24] target/i386: Do not re-compute new pc with CF_PCREL

From: Richard Henderson With PCREL, we have a page-relative view of EIP, and an approximation of PC = EIP+CSBASE that is good enough to detect page crossings. If we try to recompute PC after masking EIP, we will mess up that approximation and write a corrupt value to EIP. We already handled mas

[Stable-8.1.5 15/24] target/i386: pcrel: store low bits of physical address in data[0]

From: Paolo Bonzini For PC-relative translation blocks, env->eip changes during the execution of a translation block, Therefore, QEMU must be able to recover an instruction's PC just from the TranslationBlock struct and the instruction data with. Because a TB will not span two pages, QEMU stores

[Stable-8.1.5 19/24] hw/pflash: implement update buffer for block writes

From: Gerd Hoffmann Add an update buffer where all block updates are staged. Flush or discard updates properly, so we should never see half-completed block writes in pflash storage. Drop a bunch of FIXME comments ;) Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID:

[Stable-8.1.5 v2 00/24] Patch Round-up for stable 8.1.5, freeze on 2024-01-27

The following patches are queued for QEMU stable v8.1.5: https://gitlab.com/qemu-project/qemu/-/commits/staging-8.1 Patch freeze is 2024-01-27, and the release is planned for 2024-01-29: https://wiki.qemu.org/Planning/8.1 Please respond here or CC qemu-sta...@nongnu.org on any additional pa

[Stable-8.1.5 24/24] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued

From: Mark Cave-Ayland Even though the BLAST command isn't fully implemented in QEMU, the DMA_STAT_BCMBLT bit should be set after the command has been issued to indicate that the command has completed. This fixes an issue with the DC390 DOS driver which issues the BLAST command as part of its n

[Stable-8.1.5 23/24] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt

From: Mark Cave-Ayland The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to generate an interrupt, however the Linux driver manually checks for DMA_STAT_DONE being set and if it is, considers that a DMA transfer has completed. If DMA_STAT_DONE is set but the ESP device

[Stable-8.1.5 12/24] load_elf: fix iterator's type for elf file processing

From: Anastasia Belova j is used while loading an ELF file to byteswap segments' data. If data is larger than 2GB an overflow may happen. So j should be elf_word. This commit fixes a minor bug: it's unlikely anybody is trying to load ELF files with 2GB+ segments for wrong-endianness targets, but

[Stable-8.1.5 21/24] hw/scsi/esp-pci: use correct address register for PCI DMA transfers

From: Mark Cave-Ayland The current code in esp_pci_dma_memory_rw() sets the DMA address to the value of the DMA_SPA (Starting Physical Address) register which is incorrect: this means that for each callback from the SCSI layer the DMA address is set back to the starting address. In the case wher

[Stable-8.1.5 20/24] migration/rdma: define htonll/ntohll only if not predefined

From: Nick Briggs Solaris has #defines for htonll and ntohll which cause syntax errors when compiling code that attempts to (re)define these functions.. Signed-off-by: Nick Briggs Link: https://lore.kernel.org/r/65a04a7d.497ab3.3e7be...@gateway.sonic.net Signed-off-by: Peter Xu (cherry picked

[Stable-8.1.5 22/24] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources

From: Mark Cave-Ayland The am53c974/dc390 PCI interrupt has two separate sources: the first is from the internal ESP device, and the second is from the PCI DMA transfer logic. Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather than driving the PCI IRQ directly, and introduc

[Stable-8.1.5 14/24] target/i386: fix incorrect EIP in PC-relative translation blocks

From: guoguangyao The PCREL patches introduced a bug when updating EIP in the !CF_PCREL case. Using s->pc in func gen_update_eip_next() solves the problem. Cc: qemu-sta...@nongnu.org Fixes: b5e0d5d22fbf ("target/i386: Fix 32-bit wrapping of pc/eip computation") Fixes: 5b2fd6cf3735 (b5e0d5d22fbf

[Stable-8.1.5 16/24] backends/cryptodev: Do not ignore throttle/backends Errors

From: Philippe Mathieu-Daudé Both cryptodev_backend_set_throttle() and CryptoDevBackendClass::init() can set their Error** argument. Do not ignore them, return early on failure. Without that, running into another failure trips error_setv()'s assertion. Use the ERRP_GUARD() macro as suggested in c

[Stable-8.1.5 17/24] hw/pflash: refactor pflash_data_write()

From: Gerd Hoffmann Move the offset calculation, do it once at the start of the function and let the 'p' variable point directly to the memory location which should be updated. This makes it simpler to update other buffers than pfl->storage in an upcoming patch. No functional change. Signed-of

Re: [PATCH] target/ppc: Fix crash on machine check caused by ifetch

On 1/7/24 18:05, Nicholas Piggin wrote: is_prefix_insn_excp() loads the first word of the instruction address which caused an exception, to determine whether or not it was prefixed so the prefix bit can be set in [H]SRR1. In case it was the instruction fetch itself that caused the exception, the

NVME hotplug support ?

Hi all, We are currently looking into hotplugging nvme devices and it is currently not possible: When nvme was introduced 2 years ago, the feature was disabled. > commit cc6fb6bc506e6c47ed604fcb7b7413dff0b7d845 > Author: Klaus Jensen > Date: Tue Jul 6 10:48:40 2021 +0200 > >hw/nvme: mark n

Re: [PATCH] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses

On 1/12/24 14:46, Peter Maydell wrote: The raven_io_ops MemoryRegionOps is the only one in the source tree which sets .valid.unaligned to indicate that it should support unaligned accesses and which does not also set .impl.unaligned to indicate that its read and write functions can do the unalign

[PATCH] tests/qtest: Bump timeout of the boot-serial-test to 360 seconds

On the slow k8s CI runner, the test sometimes takes more than 240 seconds. See for example this run here where it took ~ 267 seconds: https://gitlab.com/qemu-project/qemu/-/jobs/5806087027#L4769 Thus we have to bump the timeout here even further to be on the safe side. Let's use 360 seconds whic

Re: [PATCH] tests/qtest: Bump timeout of the boot-serial-test to 360 seconds

On Tue, Jan 23, 2024 at 12:03:53PM +0100, Thomas Huth wrote: > On the slow k8s CI runner, the test sometimes takes more than 240 > seconds. See for example this run here where it took ~ 267 seconds: > > https://gitlab.com/qemu-project/qemu/-/jobs/5806087027#L4769 > > Thus we have to bump the tim

[PATCH v3 0/3] target/riscv: Add support for Zaamo & Zalrsc

Introduce support for the proposed new (fast-track) Zaamo and Zalrsc extensions [1] which represent the AMO and LR/SC subsets of the A extension. The motivation for the subsets being available separately is that certain classes of CPUs may choose to only implement a subset for architectural conve

[PATCH v3 1/3] target/riscv: Add Zaamo and Zalrsc extension infrastructure

These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_cfg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_c

[PATCH v3 2/3] target/riscv: Check 'A' and split extensions for atomic instructions

Following the pattern for 'M' and Zmmul check if either the 'A' extension is enabled or the appropriate split extension for the instruction. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 56 +++-- 1 file changed, 34 insertions(+), 22 deletions(-)

[PATCH v3 3/3] target/riscv: Expose Zaamo and Zalrsc extensions

Expose the newly added extensions to the guest and allow their control through the CPU properties. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d3ec74a1c..604baf53c8 100644 --- a/target/

Re: [PATCH 1/5] target/i386: mask high bits of CR3 in 32-bit mode

On Thu, Jan 18, 2024 at 9:04 AM Michael Tokarev wrote: > > 22.12.2023 20:59, Paolo Bonzini: > > CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level > > paging or PAE paging). Do this in mmu_translate() to remove > > the last where get_physical_address() meaningfully drops the high >

Re: [RFC 0/3] aio-posix: call ->poll_end() when removing AioHandler

Am 22.01.24 um 18:52 schrieb Hanna Czenczek: > On 22.01.24 18:41, Hanna Czenczek wrote: >> On 05.01.24 15:30, Fiona Ebner wrote: >>> Am 05.01.24 um 14:43 schrieb Fiona Ebner: Am 03.01.24 um 14:35 schrieb Paolo Bonzini: > On 1/3/24 12:40, Fiona Ebner wrote: >> I'm happy to report that I

Re: NVME hotplug support ?

On Jan 23 10:59, Damien Hedde wrote: > Hi all, > > We are currently looking into hotplugging nvme devices and it is currently > not possible: > When nvme was introduced 2 years ago, the feature was disabled. > > commit cc6fb6bc506e6c47ed604fcb7b7413dff0b7d845 > > Author: Klaus Jensen > > Date:

Re: [RFC 0/3] aio-posix: call ->poll_end() when removing AioHandler

On 22.01.24 18:52, Hanna Czenczek wrote: On 22.01.24 18:41, Hanna Czenczek wrote: On 05.01.24 15:30, Fiona Ebner wrote: Am 05.01.24 um 14:43 schrieb Fiona Ebner: Am 03.01.24 um 14:35 schrieb Paolo Bonzini: On 1/3/24 12:40, Fiona Ebner wrote: I'm happy to report that I cannot reproduce the CPU

[PATCH 7.2] accel/tcg: Revert mapping of PCREL translation block to multiple virtual addresses

This is causing regressions that have not been analyzed yet. Revert the change on stable branches. Cc: qemu-sta...@nongnu.org Cc: Michael Tokarev Related: https://gitlab.com/qemu-project/qemu/-/issues/2092 Signed-off-by: Paolo Bonzini --- include/exec/exec-all.h | 6 -- accel/tcg/cpu-exe

[PATCH] accel/tcg: Revert mapping of PCREL translation block to multiple virtual addresses

This is causing regressions that have not been analyzed yet. Revert the change on stable branches. Related: https://gitlab.com/qemu-project/qemu/-/issues/2092 Signed-off-by: Paolo Bonzini --- include/exec/exec-all.h | 6 -- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/tb-maint.c | 6

Re: [PATCH 2/5] util/uri: Simplify uri_string_unescape()

On 23/01/2024 11.25, Paolo Bonzini wrote: Il lun 22 gen 2024, 20:18 Thomas Huth > ha scritto: uri_string_unescape() basically does the same as the glib function g_uri_unescape_string(), with just an additional length parameter. You can replace it altogether

Re: [RFC 0/3] aio-posix: call ->poll_end() when removing AioHandler

On 23.01.24 12:12, Fiona Ebner wrote: [...] I noticed poll_set_started() is not called, because ctx->fdmon_ops->need_wait(ctx) was true, i.e. ctx->poll_disable_cnt was positive (I'm using fdmon_poll). I then found this is because of the notifier for the event vq, being attached with virtio_qu

[PATCH 1/2] igb: fix link state on resume

On resume igb_vm_state_change() always calls igb_autoneg_resume() that sets link_down to false, and thus activates the link even if we have disabled it. The problem can be reproduced starting qemu in paused state (-S) and then set the link to down. When we resume the machine the link appears to be

[PATCH 2/2] e1000e: fix link state on resume

On resume e1000e_vm_state_change() always calls e1000e_autoneg_resume() that sets link_down to false, and thus activates the link even if we have disabled it. The problem can be reproduced starting qemu in paused state (-S) and then set the link to down. When we resume the machine the link appears

[PATCH 8.1] accel/tcg: Revert mapping of PCREL translation block to multiple virtual addresses

This is causing regressions that have not been analyzed yet. Revert the change on stable branches. Cc: qemu-sta...@nongnu.org Cc: Michael Tokarev Related: https://gitlab.com/qemu-project/qemu/-/issues/2092 Signed-off-by: Paolo Bonzini --- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/tb-maint.

Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent

Hi Anton, On 19/1/24 15:40, Anton Johansson wrote: Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into runtime branches. Signed-off-by: Anton Johansson --- accel/tcg/tcg-all.c | 25 + 1 file changed, 9 insertions(+), 16 deletions(-) static v

Re: [PATCH v2 3/3] s390x/pci: drive ISM reset from subsystem reset

On Mon, 22 Jan 2024 10:06:38 -0500 Matthew Rosato wrote: > On 1/19/24 4:07 PM, Halil Pasic wrote: > > On Thu, 18 Jan 2024 13:51:51 -0500 > > Matthew Rosato wrote: > > > >> diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c > >> index eaf61d3640..c99682b07d 100644 > >> --- a/

Re: [RFC PATCH 26/34] Wrap target macros in functions

Hi Anton, On 19/1/24 15:40, Anton Johansson wrote: Adds wrapper functions around common target specific macros required by accel/tcg. Signed-off-by: Anton Johansson --- include/hw/core/cpu.h | 9 +++ cpu-target.c | 62 +++ 2 files chang

Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent

On 23/01/24, Philippe Mathieu-Daudé wrote: > Hi Anton, > > On 19/1/24 15:40, Anton Johansson wrote: > > Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into > > runtime branches. > > > > Signed-off-by: Anton Johansson > > --- > > accel/tcg/tcg-all.c | 25 +---

Re: [RFC PATCH v7] ppc: Enable 2nd DAWR support on p10

On Wed Nov 22, 2023 at 5:32 PM AEST, Shivaprasad G Bhat wrote: > Extend the existing watchpoint facility from TCG DAWR0 emulation > to DAWR1 on POWER10. > > As per the PAPR, bit 0 of byte 64 in pa-features property > indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd > DAWR

Re: [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets

On 19/01/24, Philippe Mathieu-Daudé wrote: > On 19/1/24 15:39, Anton Johansson wrote: > > Allows for future commits to use TargetPageBits to access page bits and > > mask, thus making TARGET_PAGE_* independent of softmmu target. > > > > In the future, this will also be important fo allowing hetero

Re: [RFC PATCH 26/34] Wrap target macros in functions

On 23/01/24, Philippe Mathieu-Daudé wrote: > Hi Anton, > > On 19/1/24 15:40, Anton Johansson wrote: > > Adds wrapper functions around common target specific macros required by > > accel/tcg. > > > > Signed-off-by: Anton Johansson > > --- > > include/hw/core/cpu.h | 9 +++ > > cpu-target.

Re: KVM/QEMU Community Call 23rd Jan Agenda Items

Alex Bennée writes: > Hi, > > The KVM/QEMU community call is at: > > https://meet.jit.si/kvmcallmeeting > @ > 23/1/2024 14:00 UTC > > If anyone has any agenda items please reply to this thread. Reminder the call is this afternoon but currently I have no items for the agenda. -- Alex Benn

[PATCH v3 0/3] Add device STM32L4x5 GPIO

This patch adds a new device STM32L4x5 GPIO device and is part of a series implementing the STM32L4x5 with a few peripherals. Changes from v2 : - correct memory leaks caused by re-assigning a `g_autofree` pointer without freeing it - gpio-test : test that reset values (and not just initialization

[PATCH v3 3/3] tests/qtest: Add STM32L4x5 GPIO QTest testcase

The testcase contains : - `test_idr_reset_value()` : Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR. - `test_gpio_output_mode()` : Checks that writing a bit in register ODR results in the corresponding pin rising or lowering, if this pin is configured in output mode. - `test_gpio_inpu

[PATCH v3 1/3] hw/gpio: Implement STM32L4x5 GPIO

Features supported : - the 8 STM32L4x5 GPIOs are initialized with their reset values (except IDR, see below) - input mode : setting a pin in input mode "externally" (using input irqs) results in an out irq (transmitted to SYSCFG) - output mode : setting a bit in ODR sets the corresponding o

[PATCH v3 2/3] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC

Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 78 -- include/hw/arm/stm32l4x5_soc.h | 2 + 3 files changed, 68 insertions(+), 15 deletions(-) diff --git a/hw/arm/Kconfig b/hw/

Re: [PATCH rfcv1 4/6] vfio: initialize IOMMUFDDevice and pass to vIOMMU

On 1/23/24 10:46, Duan, Zhenzhong wrote: -Original Message- From: Cédric Le Goater Subject: Re: [PATCH rfcv1 4/6] vfio: initialize IOMMUFDDevice and pass to vIOMMU On 1/15/24 11:13, Zhenzhong Duan wrote: Initialize IOMMUFDDevice in vfio and pass to vIOMMU, so that vIOMMU could get h

Re: [PATCH rfcv1 6/6] intel_iommu: add a framework to check and sync host IOMMU cap/ecap

On 1/19/24 12:55, Duan, Zhenzhong wrote: > >> -Original Message- >> From: Eric Auger >> Subject: Re: [PATCH rfcv1 6/6] intel_iommu: add a framework to check and >> sync host IOMMU cap/ecap >> >> >> >> On 1/18/24 10:30, Duan, Zhenzhong wrote: >>> Hi Eric, >>> -Original Message--

Re: [PATCH] target/ppc: Fix crash on machine check caused by ifetch

On 1/7/24 18:05, Nicholas Piggin wrote: is_prefix_insn_excp() loads the first word of the instruction address which caused an exception, to determine whether or not it was prefixed so the prefix bit can be set in [H]SRR1. In case it was the instruction fetch itself that caused the exception, the

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