On Mon, Nov 27, 2023 at 05:26:00PM -0300, Fabiano Rosas wrote:
> Currently multifd does not need to have knowledge of pages on the
> receiving side because all the information needed is within the
> packets that come in the stream.
>
> We're about to add support to fixed-ram migration, which canno
On Mon, Nov 27, 2023 at 05:26:01PM -0300, Fabiano Rosas wrote:
> Some functionalities of multifd are incompatible with the 'fixed-ram'
> migration format.
>
> The MULTIFD_FLUSH flag in particular is not used because in fixed-ram
> there is no sinchronicity between migration source and destination
Hi
On Mon, Jan 15, 2024 at 10:49 PM Stefan Hajnoczi wrote:
>
> On Fri, Jan 12, 2024 at 07:36:19PM +0900, Akihiko Odaki wrote:
> > Coroutine may be pooled even after COROUTINE_TERMINATE if
> > CONFIG_COROUTINE_POOL is enabled and fake stack should be saved in
> > such a case to keep AddressSanitiz
Hi,
I want to improve the startup speed of Windows VM. On the x86
architecture, QEMU's Windows11 VM can enable the Fast startup function,
but it cannot work on the ARM architecture. By the way, the Fast startup
function of Windows on ARM physical machines can work normally.
Is there anything
As I'm the addressee of the ping for some reason ... :-)
the fix looks good to me but I'm not sure about all the consequences of
moving kvm_put_vcpu_events() to an earlier stage. Max, Paolo, please
take a look!
Eiichi Tsukata writes:
> Ping.
>
>> On Nov 8, 2023, at 10:12, Eiichi Tsukata wrote:
Based-on: <20240116003551.75168-1-...@linux.ibm.com>
([PATCH v3 0/3] linux-user: Allow gdbstub to ignore page protection)
v1: https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02911.html
v1 -> v2: Avoid touching the system gdbstub.
Advertise QCatchSyscalls+ only on Linux.
Hi,
I
GDB supports stopping on syscall entry and exit using the "catch
syscall" command. It relies on 3 packets, which are currently not
supported by QEMU:
* qSupported:QCatchSyscalls+ [1]
* QCatchSyscalls: [2]
* T05syscall_entry: and T05syscall_return: [3]
Implement generation and handling of these pa
Check that adding/removing syscall catchpoints works.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/multiarch/Makefile.target | 10 +++-
tests/tcg/multiarch/catch-syscalls.c | 51 ++
tests/tcg/multiarch/gdbstub/catch-syscalls.py | 52 +++
3 file
On 16/1/24 07:27, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Mon, Jan 15, 2024 at 05:39:19PM +, Peter Maydell wrote:
On Mon, 15 Jan 2024 at 13:54, Thomas Huth wrote:
On 12/01/2024 16.39, Philippe Mathieu-Daudé wrote:
Hi Thomas
+Laurent & Peter
On 12/1/24 11:00, Thomas Hu
On 16/1/24 02:39, Bibo Mao wrote:
When compiling qemu with system KVM mode for LoongArch, header files
in directory linux-headers/asm-loongarch should be used firstly.
Otherwise it fails to find kvm.h on system with old glibc, since
latest kernel header files are not installed.
This patch adds l
On 16/01/2024 10.46, Philippe Mathieu-Daudé wrote:
On 16/1/24 07:27, Markus Armbruster wrote:
Daniel P. Berrangé writes:
On Mon, Jan 15, 2024 at 05:39:19PM +, Peter Maydell wrote:
On Mon, 15 Jan 2024 at 13:54, Thomas Huth wrote:
On 12/01/2024 16.39, Philippe Mathieu-Daudé wrote:
Hi T
On 15/1/24 19:27, Guenter Roeck wrote:
Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.
If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid
Hi,
(Cc'ing Li, Strahinja and Niek)
On 15/1/24 19:27, Guenter Roeck wrote:
Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.
I'm confused by these registers from TYPE_AW_A10_PIT
and the TYPE_AW_WDT implementatio
Queued, thanks.
Paolo
On Mon, Jan 15, 2024 at 08:12:29AM -0800, Guenter Roeck wrote:
> On 1/15/24 03:02, Philippe Mathieu-Daudé wrote:
> > On 13/1/24 20:16, Guenter Roeck wrote:
> > > If machine USB support is not enabled, create unimplemented devices
> > > for the USB memory ranges to avoid crashes when booting Linux.
Hi Gurchetan,
Gurchetan Singh writes:
> - As mentioned in v14:
> * AEMU: d6e6b99 "Delete VpxFrameParser.cpp"
> * gfxstream: 2131f78d Merge "gfxstream: add egl & gles deps.."
>
> are the proposed v.0.1.2 release points. If those commits are sufficient
> for packaging AEMU + gfxstream, le
From: Akihiko Odaki
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by: A
From: Akihiko Odaki
The effective MXL value matters when booting.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-23-alex.ben...@linaro.org>
Message-Id: <20231213-riscv-v7-1-a760156a3...@daynix.com>
Signed-off-by: Alex Bennée
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
inde
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Acked-by: Richard Henderson
Message-Id: <20240103173349.398526-27-al
From: Akihiko Odaki
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-25-alex.ben...@linaro.org>
Message-Id: <20231213-riscv-v7-3-a760156a3...@daynix.com>
[AJB: fixed merge conflicts]
While we attempt to hide implementation details from the plugin we
shouldn't be totally obtuse. Let the user know what they can and can't
expect with the various instrumentation options.
Message-Id: <20240103173349.398526-44-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed-off-by: Ale
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
Message-Id: <20240103173349.398526-28
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested
From: Akihiko Odaki
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
Acked-by: LIU Zhiwei
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Message-Id: <20240103173349.39852
This adds an additional flag which attempts to optimise the register
tracking by only instrumenting instructions which are likely to change
its value. This relies on the disassembler showing up the register
names in disassembly so is only enabled when asked for.
Message-Id: <20240103173349.398526-
From: Akihiko Odaki
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20240103173349.398526-31-alex.ben...@linaro.org>
Message-Id: <2
From: Akihiko Odaki
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-26-alex.ben...@lina
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-29-alex.ben...@linaro.org>
Message
The following changes since commit 977542ded7e6b28d2bc077bcda24568c716e393c:
Merge tag 'pull-testing-updates-120124-2' of https://gitlab.com/stsquad/qemu
into staging (2024-01-12 14:02:53 +)
are available in the Git repository at:
https://gitlab.com/stsquad/qemu.git tags/pull-registers-
Expose an internal API to QEMU to return all the registers for a vCPU.
The list containing the details required to called gdb_read_register().
Based-on: <20231025093128.33116-15-akihiko.od...@daynix.com>
Cc: Akihiko Odaki
Message-Id: <20240103173349.398526-38-alex.ben...@linaro.org>
Signed-off-by
From: Akihiko Odaki
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-36-alex.ben...@linaro.org>
Message-Id
From: Akihiko Odaki
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Message-Id: <20240103173349.398526-43-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
diff --git a/docs/devel/tcg
From: Akihiko Odaki
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20240103173349.398526-33-alex.ben..
From: Akihiko Odaki
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-34-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-8-777047380...@daynix.com>
Signed-off-by: Alex Bennée
diff --git
From: Akihiko Odaki
This function is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
Message-Id: <20240103173349.398526-35-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-9-777047380...@daynix.com>
Signed-off-by: Alex Bennée
diff --git a/include/hw/core/cpu.h b/in
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Message-Id: <20240103173349.398526-40-alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
diff --git a/contrib/plugins/execlog.c b/cont
We can only request a list of registers once the vCPU has been
initialised so the user needs to use either call the get function on
vCPU initialisation or during the translation phase.
We don't expose the reg number to the plugin instead hiding it behind
an opaque handle. This allows for a bit of
From: Akihiko Odaki
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
Reviewed-by: Pierrick Bouvier
Message-Id: <20240103173349.398526-37-alex.ben...@linaro.org>
Message-Id: <20231213-gdb-v17-12-777047380...@daynix.com>
Signed-off-by: Alex Bennée
Revi
John Snow writes:
> allow resolve_type to be used for both built-in and user-specified
> type definitions. In the event that the type cannot be resolved, assert
> that 'info' and 'what' were both provided in order to create a usable
> QAPISemError.
>
> In practice, 'info' will only be None for bu
On Mon, 15 Jan 2024, marcandre.lur...@redhat.com wrote:
+scanout->ds = qemu_create_displaysurface_pixman(res->image);
+if (!scanout->ds) {
+return -EINVAL;
+}
"qemu_create_displaysurface_pixman() never returns NULL." ;-)
Am 15.01.24 um 13:00 schrieb Marc-André Lureau:
>>>
>>> The trouble is when qemu_clipboard_update() is called without data &
>>> without a request callback set. We shouldn't allow that as we have no
>>> means to get the clipboard data then.
>>>
>>
>> In the above scenario, I'm pretty sure ther
John Snow writes:
> Adjust the expression at the callsite to eliminate weak type
> introspection that believes this value can resolve to QAPISourceInfo; it
> cannot.
What do you mean by "weak type introspection"? mypy being underpowered?
> Signed-off-by: John Snow
> ---
> scripts/qapi/schema
On Thu, Dec 21, 2023 at 08:45:05AM -0500, Eric Auger wrote:
> We used to set default page_size_mask to qemu_target_page_mask() but
> with VFIO assignment it makes more sense to use the actual host page mask
> instead.
>
> So from now on qemu_real_host_page_mask() will be used as a default.
> To be
... and move them in their right hardware directory.
Update Copyright and add SPDX-License-Identifier at the same time.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
---
hw/char/grlib_apbuart.c | 6 ++--
hw/intc/grlib_irqmp.c | 6
V2 modifications
- Patch1: Add SPDX copyright tags.
- Patch3: Add defines for MP_STATUS fields. Improve comments.
- Patch4: Improve a comment.
- Patch6: Dropped as already merged.
---
This series allows leon3 emulations to record up 4 CPUs.
It requires some enhancements in the grlib_irqmp de
Now there is an ncpus property, use it in order to deliver the IRQ to
multiple CPU.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
---
hw/intc/grlib_irqmp.c | 43 ++-
hw/sparc/leon3.c | 3 ++-
include/hw/intc/grlib_irqmp.h |
This adds a "ncpus" property to the "grlib-irqmp" device to be used later,
this required a little refactoring of how we initialize the device (ie: use
realize instead of init).
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Philippe Mathieu-Daudé
---
hw/intc/grlib_
This implements the multiprocessor status register in grlib-irqmp and bind
it to a start signal, which will be later wired in leon3-generic to
start a cpu.
The EIRQ and BA bits are not implemented.
Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5.
Co-developed-by: Frederic Konrad
This allows to register more than one CPU on the leon3_generic machine.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
---
hw/sparc/leon3.c | 106 +--
1 file changed, 74 insertions(+), 32 deletions(-)
diff --git a/hw/sparc/leon3.c b/h
Now that SMP is possible, the asr17 must be checked in the little boot code
or the secondary CPU will reinitialize the Timer and the Uart.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
---
hw/sparc/leon3.c | 22 --
1 file changed, 20 insertions(+), 2 deletio
CC: Fabien Chouteau
Signed-off-by: Clément Chigot
Reviewed-by: Fabien Chouteau
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b406fb20c0..b4e78e7748 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1708,7 +1708,7 @@ F: hw/rtc/su
This allows the guest program to know its cpu id.
Co-developed-by: Frederic Konrad
Signed-off-by: Clément Chigot
Reviewed-by: Richard Henderson
---
target/sparc/helper.c| 16
target/sparc/helper.h| 1 +
target/sparc/translate.c | 13 +++--
3 files changed, 20
On Mon, 18 Dec 2023 11:32:57 +
Peter Maydell wrote:
> If FEAT_NV2 redirects a system register access to a memory offset
> from VNCR_EL2, that access might fault. In this case we need to
> report the correct syndrome information:
> * Data Abort, from same-EL
> * no ISS information
> * the
On Tue, 16 Jan 2024 at 13:09, Jonathan Cameron
wrote:
>
> On Mon, 18 Dec 2023 11:32:57 +
> Peter Maydell wrote:
>
> > If FEAT_NV2 redirects a system register access to a memory offset
> > from VNCR_EL2, that access might fault. In this case we need to
> > report the correct syndrome informat
On 08/01/2024 21.27, David Woodhouse wrote:
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/s390x/s390-virtio-ccw.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 1169e20b94..202c37813
On 1/8/24 21:26, David Woodhouse wrote:
From: David Woodhouse
Signed-off-by: David Woodhouse
---
hw/arm/aspeed.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc59176563..bed5e4f40b 100644
--- a/hw/arm/aspeed.c
+++ b/hw/
John Snow writes:
> QAPISchemaInfo instances are sometimes defined as an Optional
> field/argument because built-in definitions don't *have* a source
> definition. As a consequence, there are a few places where we need to
> assert that it's present because the root entity definition can only
> en
Peter Xu writes:
> On Mon, Nov 27, 2023 at 05:25:55PM -0300, Fabiano Rosas wrote:
>> Allow multifd to open file-backed channels. This will be used when
>> enabling the fixed-ram migration stream format which expects a
>> seekable transport.
>>
>> The QIOChannel read and write methods will use th
On 12/28/23 11:12, Alexander Ivanov wrote:
There is no necessity to search to the end of the bitmap. Limit the search
area as cluster_index + count.
Add cluster_end variable to avoid its calculation in a few places.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 9 +
1 file
On 12/28/23 11:12, Alexander Ivanov wrote:
Add a helper to set unused areas in the used bitmap.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 18 ++
block/parallels.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/block/parallels.c b/block/parallels.c
ind
>> >
>> > Given that, an alternative proposal that I think would work
>> > for you would be to add a 'placeholder' memory node definition
>> > in SRAT (so allow 0 size explicitly - might need a new SRAT
>> > entry to avoid backwards compat issues).
>>
>> Putting all the PCI/GI/... complexity aside,
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 04:13:23AM -0500, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 04:13:23 -0500
> From: Xiaoyao Li
> Subject: [PATCH 0/2] i386/cpu: Two minor fixes for
> x86_cpu_enable_xsave_components()
> X-Mailer: git-send-email 2.34.1
>
> The two bugs were introduced when xsa
From: Peng Fan
xen_invalidate_map_cache_entry is not expected to run in a
coroutine. Without this, there is crash:
signo=signo@entry=6, no_tid=no_tid@entry=0) at pthread_kill.c:44
threadid=) at pthread_kill.c:78
at /usr/src/debug/glibc/2.38+git-r0/sysdeps/posix/raise.c:26
fmt=0xf
Hi,
I want to improve the startup speed of Windows VM. On the x86 architecture,
QEMU's Windows11 VM can enable the Fast startup function, but it cannot work on
the ARM architecture. In addition, Windows can also enable the Fast startup
function on the ARM host.
Is there anything missing in QE
I hope this message finds you well. I am reaching out to seek your
expertise regarding a persistent issue I have encountered while working
with QEMU, specifically a hardfault error when emulating the MPS2AN505 with
a Cortex-M33 core.
I have been grappling with this issue for some time and am unsur
Hi,
I want to improve the startup speed of Windows VM. On the x86 architecture,
QEMU's Windows11 VM can enable the Fast startup function, but it cannot work on
the ARM architecture. In addition, Windows can also enable the Fast startup
function on the ARM host.
Is there anything missing in QE
On 12/28/23 11:12, Alexander Ivanov wrote:
For parallels images extensions we need to allocate host clusters
without any connection to BAT. Move host clusters allocation code to
parallels_allocate_host_clusters().
This function can be called not only from coroutines so all the
*_co_* functions w
On 12/28/23 11:12, Alexander Ivanov wrote:
In parallels_check_leak() we change file size but don't correct data_end
field of BDRVParallelsState structure. Fix it.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels.c b/blo
On Tue, 16 Jan 2024 at 14:16, sanjana gogte wrote:
>
> I hope this message finds you well. I am reaching out to seek your expertise
> regarding a persistent issue I have encountered while working with QEMU,
> specifically a hardfault error when emulating the MPS2AN505 with a Cortex-M33
> core.
On 12/28/23 11:12, Alexander Ivanov wrote:
In parallels_check_leak() file can be truncated. In this case the used
bitmap would not comply to the file. Recreate the bitmap after file
truncation.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 8
1 file changed, 8 insertions(+
On 12/28/23 11:12, Alexander Ivanov wrote:
In parallels_check_duplicate() We use a bitmap for duplication detection.
This bitmap is not related to used_bmap field in BDRVParallelsState. Add
a comment about it to avoid confusion.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 5 -
On 12/28/23 11:12, Alexander Ivanov wrote:
All the checks were fixed to work with used bitmap. Create used bitmap in
parallels_open() even if need_check is true.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
Hi Jean,
On 1/16/24 13:53, Jean-Philippe Brucker wrote:
> On Thu, Dec 21, 2023 at 08:45:05AM -0500, Eric Auger wrote:
>> We used to set default page_size_mask to qemu_target_page_mask() but
>> with VFIO assignment it makes more sense to use the actual host page mask
>> instead.
>>
>> So from now o
On 12/28/23 11:12, Alexander Ivanov wrote:
Now we support extensions saving and can let to work with them in
read-write mode.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 4
block/parallels.c | 17 -
2 files changed, 4 insertions(+), 17 deletions(-)
On Tue, 16 Jan 2024 13:20:33 +
Peter Maydell wrote:
> On Tue, 16 Jan 2024 at 13:09, Jonathan Cameron
> wrote:
> >
> > On Mon, 18 Dec 2023 11:32:57 +
> > Peter Maydell wrote:
> >
> > > If FEAT_NV2 redirects a system register access to a memory offset
> > > from VNCR_EL2, that access mi
John Snow writes:
> differentiate between "actively in the process of checking" and
> "checking has completed". This allows us to clean up the types of some
> internal fields such as QAPISchemaObjectType's members field which
> currently uses "None" as a test for determining if check has been run
On Tue, 16 Jan 2024 at 14:50, Jonathan Cameron
wrote:
>
> On Tue, 16 Jan 2024 13:20:33 +
> Peter Maydell wrote:
> > Bisecting to this patch is a bit weird because at this point
> > in the series emulation of FEAT_NV2 should be disabled and
> > the code being added should never be used. You co
From: Samuel Tardieu
Signed-off-by: Samuel Tardieu
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Laurent Vivier
Message-id: 20240109184508.3189599-1-...@rfc1149.net
Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC")
Signed-off-by: Peter Maydell
---
hw/timer/trace-events | 2 +-
1
From: Inès Varhol
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Message-id: 20240109194438.70934-4-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
tests/qtest/stm32l4x5_
From: Inès Varhol
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Message-id: 20240109160658.311932-3-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
include/hw/arm/stm
In arm_pamax(), we need to cope with the virt board calling this
function on a CPU object which has been inited but not realize.
We used to do propagation of feature-flag implications (such as
"V7VE implies LPAE") at realize, so we have some code in arm_pamax()
which manually checks for both V7VE a
Improve the 'highmem' option docs to note that by default we assume
that a 32-bit kernel on an LPAE-capable CPU has LPAE enabled, and
what the consequences are.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Message-id: 20240109170834.1387457-1-peter.mayd...@linar
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
Message-id: 20240110234232.4116804-6-nabiheste...@google.com
Signed-off-by: Peter Maydell
Reviewed-by: Peter Maydell
---
include/hw/arm/npcm7xx.h |
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
Message-id: 20240110234232.4116804-3-nabiheste...@google.com
[PMM: moved some changes incorrectly in previous
From: Gavin Shan
It's found that some of the CPU type names in the array of valid
CPU types are invalid because their corresponding classes aren't
registered, as reported by Peter Maydell.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cor
We don't currently document the syntax of .hx files anywhere
except in a few comments at the top of individual .hx files.
We don't even have somewhere in the developer docs where we
could do this.
Add a new files docs/devel/docs.rst which can be a place to
document how our docs build process works
From: Inès Varhol
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates
more than 32 event/interrupt requests and thus uses more registers
than STM32F4xx EXTI which generates 23 event/interrupt requests.
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inè
From: Inès Varhol
The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
device will be implemented, its output GPIOs will be connected to the
SYSCFG input GPIOs.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Arnaud Minier
Signed-off-by: In
mu-arm.git
tags/pull-target-arm-20240116
for you to fetch changes up to 7ec39730a9cc443c752d4cad2bf1c00467551ef5:
load_elf: fix iterator's type for elf file processing (2024-01-15 17:14:22
+)
target-arm queue:
* docs/devel
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
Message-id: 20240110234232.4116804-7-nabiheste...@googl
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.
From: Inès Varhol
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Message-id: 20240109194438.70934-2-ines.var...@telecom-paris.fr
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/system/arm/b-l475e-iot01a.rst | 2 +-
include/hw/misc/stm32
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP N
From: Anastasia Belova
j is used while loading an ELF file to byteswap segments'
data. If data is larger than 2GB an overflow may happen.
So j should be elf_word.
This commit fixes a minor bug: it's unlikely anybody is trying to
load ELF files with 2GB+ segments for wrong-endianness targets,
but
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Added relevant trace-events
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
Message-id: 20240110234232.4116804-11-nabiheste...@google.com
Signed-off-by: Peter Maydell
Reviewed-by: Peter Maydell
From: Inès Varhol
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Message-id: 20240109160658.311932-4-ines.var...@telecom-paris.fr
Signed-off-by: Peter Maydell
---
tests/qtest/stm32l4x5_exti-test.c | 524
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estef
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication wit
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