[PATCH] accel/tcg: Include missing headers to 'tb-jmp-cache.h'

Due to missing headers, when including "tb-jmp-cache.h" we might get: accel/tcg/tb-jmp-cache.h:21:21: error: field ‘rcu’ has incomplete type 21 | struct rcu_head rcu; | ^~~ accel/tcg/tb-jmp-cache.h:24:9: error: unknown type name ‘vaddr’ 24 | va

Re: Re: [PULL 0/6] Firmware/edk2 20231213 patches

On Thu, Jan 11, 2024 at 04:02:38PM +, Peter Maydell wrote: > On Thu, 11 Jan 2024 at 15:52, Peter Maydell wrote: > > > > On Thu, 11 Jan 2024 at 14:01, Gerd Hoffmann wrote: > > > > > > Ping. > > > > > > As expected this missed the 8.2 boat. Now the devel tree is open again > > > and people are

[PATCH v2] block/blklogwrites: Protect mutable driver state with a mutex.

During the review of a fix for a concurrency issue in blklogwrites, it was found that the driver needs an additional fix when enabling multiqueue, which is a new feature introduced in QEMU 9.0, as the driver state may be read and written by multiple threads at the same time, which was not the case

[PATCH 0/2] ppc: Rename power5+ and power7+ for the new QOM naming rules

We can get rid of the "power5+" / "power7+" hack in qom/object.c by using CPU aliases for those names instead (first patch). I think in the long run, we should get rid of the names with a "+" in it completely, so the second patch suggests to deprecate those, but I'd also be fine if we keep the ali

[PATCH 2/2] docs/about: Deprecate the old "power5+" and "power7+" CPU names

For consistency we should drop the names with a "+" in it in the long run. Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 9 + 1 file changed, 9 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 2e15040246..7fdd2239b4 100644 --- a/docs/ab

[PATCH 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules

The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and some few special characters"). For the "power5+" and "power7+" CPU names, there is currently a hack in type_name_is_valid() to still allow them for compatibility reasons. Howeve

[PULL 10/17] gitlab: fix s390x tag for avocado-system-centos

From: Nicholas Piggin The 390x tag should be s390x. Signed-off-by: Nicholas Piggin Message-ID: <20240107170119.8-2-npig...@gmail.com> Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 2 +- 1 file changed, 1 ins

[PULL 14/17] scripts/checkpatch: Support codespell checking

From: Zhao Liu Add two spelling check options (--codespell and --codespellfile) to enhance spelling check through dictionary, which copied the Linux kernel's implementation in checkpatch.pl. This check uses the dictionary at "/usr/share/codespell/dictionary.txt" by default, if there is no dictio

[PULL 07/17] net: handle QIOTask completion to report useful error message

From: Daniel P. Berrangé The network stream backend uses the async QIO socket APIs for listening and connecting sockets. It does not check the task object completion status, however, instead just looking at whether the socket FD is -1 or not. By checking the task completion, we can set a useful

[PULL 08/17] qtest: ensure netdev-socket tests have non-overlapping names

From: Daniel P. Berrangé When naming glib tests if the name of one test is a substring of the name of another test, it is not possible to use the '-p /the/name' option to run a single test. Signed-off-by: "Daniel P. Berrangé" Message-ID: <20240104162942.211458-7-berra...@redhat.com> Reviewed-by

[PULL 00/17] Misc patches (qtests, s390x, m68k, gitlab-ci)

Hi Peter! The following changes since commit 34eac35f893664eb8545b98142e23d9954722766: Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +) are available in the Git repository at: https://gitlab.com/thuth/qemu.git tags/pul

[PULL 16/17] tests/tcg/s390x: Test LOAD ADDRESS EXTENDED

From: Ilya Leoshkevich Add a small test to prevent regressions. Userspace runs in primary mode, so LAE should always set the access register to 0. Signed-off-by: Ilya Leoshkevich Message-ID: <20240111092328.929421-3-...@linux.ibm.com> Reviewed-by: Thomas Huth Signed-off-by: Thomas Huth --- t

[PULL 02/17] qtest: use correct boolean type for failover property

From: Daniel P. Berrangé QMP device_add does not historically validate the parameter types. At some point it will likely change to enforce correct types, to match behaviour of -device. The failover property is expected to be a boolean in JSON. Signed-off-by: "Daniel P. Berrangé" Message-ID: <20

[PULL 01/17] q800: move dp8393x_prom memory region to Q800MachineState

From: Mark Cave-Ayland There is no need to dynamically allocate the memory region from the heap. Signed-off-by: Mark Cave-Ayland Message-ID: <20231227210212.245106-1-mark.cave-ayl...@ilande.co.uk> Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed

[PULL 05/17] Revert "tests/qtest/netdev-socket: Raise connection timeout to 120 seconds"

From: Daniel P. Berrangé This reverts commit 0daaf2761f6d268ffaa2d01d450e202e127452b1. The test was not timing out because of slow execution. It was timing out due to a race condition leading to the client QEMU attempting (and fatally failing) to connect before the server QEMU was listening. Si

[PULL 06/17] net: add explicit info about connecting/listening state

From: Daniel P. Berrangé When running 'info network', if the stream backend is still in the process of connecting, or waiting for an incoming connection, no information is displayed. There is also no way to distinguish whether the server is still in the process of setting up the listener socket,

[PULL 11/17] target/s390x/kvm/pv: Provide some more useful information if decryption fails

It's a common scenario to copy guest images from one host to another to run the guest on the other machine. This (of course) does not work with "secure execution" guests since they are encrypted with one certain host key. However, if you still (accidentally) do it, you only get a very user-unfriend

[PULL 04/17] Revert "osdep: add getloadavg"

From: Daniel P. Berrangé This reverts commit dc864d3a3777424187280e50c9bfb84dced54f12. This functionality is not required after the previous revert Signed-off-by: "Daniel P. Berrangé" Message-ID: <20240104162942.211458-3-berra...@redhat.com> Reviewed-by: Stefan Hajnoczi Signed-off-by: Thomas

[PULL 15/17] target/s390x: Fix LAE setting a wrong access register

From: Ilya Leoshkevich LAE should set the access register corresponding to the first operand, instead, it always modifies access register 1. Co-developed-by: Ido Plat Cc: qemu-sta...@nongnu.org Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions") Reviewed-by: David Hildenbr

[PULL 09/17] tests/qtest/virtio-ccw: Fix device presence checking

From: Samuel Tardieu An apparent copy-paste error tests for the presence of the virtio-rng-ccw device in order to perform tests on the virtio-scsi-ccw device. Signed-off-by: Samuel Tardieu Message-ID: <20240106130121.1244993-1-...@rfc1149.net> Fixes: 65331bf5d1 ("tests/qtest: Check for virtio-c

[PULL 03/17] Revert "netdev: set timeout depending on loadavg"

From: Daniel P. Berrangé This reverts commit cadfc7293977ecadc2d6c48d7cffc553ed2f85f1. The test was not timing out because of slow execution. It was timing out due to a race condition leading to the client QEMU attempting (and fatally failing) to connect before the server QEMU was listening. Si

[PULL 13/17] hw/s390x/ccw: Replace dirname() with g_path_get_dirname()

From: Zhao Liu As commit 3e015d815b3f ("use g_path_get_basename instead of basename") said, g_path_get_dirname() should be preferred over dirname() since the former is a portable utility function that has the advantage of not modifying the string argument. Replace dirname() with g_path_get_dirna

[PULL 12/17] hw/s390x/ccw: Replace basename() with g_path_get_basename()

From: Zhao Liu g_path_get_basename() is a portable utility function that has the advantage of not modifying the string argument, so it should be preferred over basename(). And also to avoid potential compile breakage with the Musl C library similar to [1], replace basename() with g_path_get_base

[PULL 17/17] .gitlab-ci.d/buildtest.yml: Work around htags bug when environment is large

From: Peter Maydell Sometimes the CI "pages" job fails with a message like this from htags: $ htags -anT --tree-view=filetree -m qemu_init -t "Welcome to the QEMU sourcecode" htags: Negative exec line limit = -371 This is due to a bug in hflags where if the environment is too large it falls ov

Re: [PULL 13/13] tests/avocado: remove skips from replay_kernel

On 08/01/2024 16.13, Alex Bennée wrote: With the latest fixes for #2010 and #2013 these tests look pretty stable now. Of course the only way to be really sure is to run it in the CI infrastructure and see what breaks. Acked-by: Pavel Dovgalyuk Signed-off-by: Alex Bennée Message-Id: <2023121109

Re: [PATCH 03/12] tests/plugin: add test plugin for inline operations

On 1/11/24 19:57, Philippe Mathieu-Daudé wrote: Hi Pierrick, On 11/1/24 15:23, Pierrick Bouvier wrote: For now, it simply performs instruction, bb and mem count, and ensure that inline vs callback versions have the same result. Later, we'll extend it when new inline operations are added. Use e

Re: [PATCH 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules

On 1/11/24 17:46, Thomas Huth wrote: The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and some few special characters"). For the "power5+" and "power7+" CPU names, there is currently a hack in type_name_is_valid() to still allow

Re: [PATCH 2/2] docs/about: Deprecate the old "power5+" and "power7+" CPU names

On 1/11/24 17:46, Thomas Huth wrote: For consistency we should drop the names with a "+" in it in the long run. Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 9 + 1 file changed, 9 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 2e

[PATCH v3] qemu-img: Fix Column Width and Improve Formatting in snapshot list

When running the command `qemu-img snapshot -l SNAPSHOT` the output of VM_CLOCK (measures the offset between host and VM clock) cannot to accommodate values in the order of thousands (4-digit). This line [1] hints on the problem. Additionally, the column width for the VM_CLOCK field was reduced fr

Possible race condition in aspeed ast2600 smp boot on TCG QEMU

We’ve noticed inconsistent behavior when running a large number of aspeed ast2600 executions, that seems to be tied to a race condition in the smp boot when executing on TCG-QEMU, and were wondering what a good mediation strategy might be. The problem first shows up as part of SMP boot. On a run t

Re: [PATCH 3/5] hw/s390x: Rename cpu_class_init() to include 'sclp'

On 11/01/2024 13.02, Philippe Mathieu-Daudé wrote: cpu_class_init() is specific to s390x SCLP, so rename it as sclp_cpu_class_init() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé --- hw/s390x/sclpcpu.c | 4 ++-- 1 file changed, 2 insertions(

Re: [RFC PATCH v3 00/30] migration: File based migration with multifd and fixed-ram

Peter Xu writes: > On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote: >> Hi, >> >> In this v3: >> >> Added support for the "file:/dev/fdset/" syntax to receive multiple >> file descriptors. This allows the management layer to open the >> migration file beforehand and pass the file d

Re: [RFC PATCH v3 04/30] io: fsync before closing a file channel

Peter Xu writes: > On Mon, Nov 27, 2023 at 05:25:46PM -0300, Fabiano Rosas wrote: >> Make sure the data is flushed to disk before closing file >> channels. This will ensure data is on disk at the end of a migration >> to file. > > Looks reasonable, but just two (possibly naive) questions: > > (1)

Re: [RFC PATCH v3 05/30] migration/qemu-file: add utility methods for working with seekable channels

Peter Xu writes: > On Mon, Nov 27, 2023 at 05:25:47PM -0300, Fabiano Rosas wrote: >> From: Nikolay Borisov >> >> Add utility methods that will be needed when implementing 'fixed-ram' >> migration capability. >> >> qemu_file_is_seekable >> qemu_put_buffer_at >> qemu_get_buffer_at >> qemu_set_of

Re: Goldfish TTY enhancement

> On Jan 10, 2024, at 8:01 AM, Philippe Mathieu-Daudé wrote: > > IIUC Goldfish virtual HW is maintained externally by Google > https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > > I suppose the spec needs to be updated before the change can be

[PATCH 0/6] Move memory listener register to vhost_vdpa_init

Current memory operations like pinning may take a lot of time at the destination. Currently they are done after the source of the migration is stopped, and before the workload is resumed at the destination. This is a period where neigher traffic can flow, nor the VM workload can continue (downtim

[PATCH 2/6] vdpa: reorder vhost_vdpa_set_backend_cap

It will be used directly by vhost_vdpa_init. Signed-off-by: Eugenio Pérez --- hw/virtio/vhost-vdpa.c | 60 +- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c index ddae494ca8..33ae285f87 10064

[PATCH 1/6] vdpa: check for iova tree initialized at net_client_start

To map the guest memory while it is migrating we need to create the iova_tree, as long as the destination uses x-svq=on. Checking to not override it. The function vhost_vdpa_net_client_stop clear it if the device is stopped. If the guest starts the device again, the iova tree is recreated by vhost

[PATCH 3/6] vdpa: set backend capabilities at vhost_vdpa_init

The backend does not reset them until the vdpa file descriptor is closed so there is no harm in doing it only once. This allows the destination of a live migration to premap memory in batches, using VHOST_BACKEND_F_IOTLB_BATCH. Signed-off-by: Eugenio Pérez --- hw/virtio/vhost-vdpa.c | 7 ++-

[PATCH 6/6] vdpa: move memory listener register to vhost_vdpa_init

Current memory operations like pinning may take a lot of time at the destination. Currently they are done after the source of the migration is stopped, and before the workload is resumed at the destination. This is a period where neigher traffic can flow, nor the VM workload can continue (downtim

[PATCH 5/6] vdpa: reorder listener assignment

Since commit f6fe3e333f ("vdpa: move memory listener to vhost_vdpa_shared") this piece of code repeatedly assign shared->listener members. This was not a problem as it was not used until device start. However next patches move the listener registration to this vhost_vdpa_init function. When the

[PATCH 4/6] vdpa: add listener_registered

Check if the listener has been registered or not, so it needs to be registered again at start. Signed-off-by: Eugenio Pérez --- include/hw/virtio/vhost-vdpa.h | 6 ++ hw/virtio/vhost-vdpa.c | 7 ++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/virtio/

[PATCH 1/1] SMBIOS type 8 should use T8_BASE.

--- hw/smbios/smbios.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 2a90601ac5..7dda84b284 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -591,6 +591,7 @@ bool smbios_skip_table(uint8_t type, bool required_table)

[PATCH 0/1] smbios_build_type_8_table should use T8_BASE.

It should use T8_BASE instead of T0_BASE. Felix Wu (1): SMBIOS type 8 should use T8_BASE. hw/smbios/smbios.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.43.0.275.g3460e3d667-goog

[PATCH] MAINTAINERS: Update Raphael Norwitz email

I will be leaving Nutanix so updating my email in MAINTAINERS to my personal email for now. Signed-off-by: Raphael Norwitz --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 00ec1f7eca..d7bb52bfd1 100644 --- a/MAINTAINERS +++ b/MAI

Re: [PATCH 4/5] target/i386: Rename tcg_cpu_FOO() to include 'x86'

11.01.2024 15:02, Philippe Mathieu-Daudé : The tcg_cpu_FOO() names are x86 specific, so rename them as x86_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Reviewed-by: Michael Tokarev Wow, that's a large list of recipients.. Signed-off-by: Philippe Mathieu-Daudé --

Re: Possible race condition in aspeed ast2600 smp boot on TCG QEMU

Sort of resolved: We were able to find a good-enough workaround. In case anyone else is running into this, here's what we did: By dropping to the uboot console and running the command ``` mw.l 0x1e6e2188 0xbabecafe ``` The magic number is set in the SCU regardless of how the race goes, and the 2

RE: [PATCH v2 5/9] Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 3/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 2/9] Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 7/9] Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 4/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 6/9] Hexagon (target/hexagon) Make generators object oriented - gen_op_regs

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 9/9] Hexagon (target/hexagon) Remove dead functions from hex_common.py

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

RE: [PATCH v2 8/9] Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute

> -Original Message- > From: Taylor Simpson > Sent: Sunday, December 10, 2023 4:07 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Matheus Bernardino (QUIC) > ; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng; ltaylorsim

[PATCH 1/2] migration/rdma: define htonll/ntohll only if not predefined

Solaris has #defines for htonll and ntohll which cause syntax errors when compiling code that attempts to (re)define these functions.. Signed-off-by: Nick Briggs --- migration/rdma.c | 4 1 file changed, 4 insertions(+) diff --git a/migration/rdma.c b/migration/rdma.c index 94c0f871f0..a35

[PATCH 2/2] qga: Solaris has net/if_arp.h and netinet/if_ether.h but not ETHER_ADDR_LEN

Solaris has net/if_arp.h and netinet/if_ether.h rather than net/ethernet.h, but does not define ETHER_ADDR_LEN, instead providing ETHERADDRL. Signed-off-by: Nick Briggs --- qga/commands-posix.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qga/commands-posix.c b/qga/com

Re: [PATCH] system/watchpoint: Move TCG specific code to accel/tcg/

On 1/12/24 03:20, Philippe Mathieu-Daudé wrote: Keep system/watchpoint.c accelerator-agnostic by moving TCG specific code to accel/tcg/watchpoint.c. Update meson. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/watchpoint.c | 143 + system/watchpoin

Re: [PATCH] cpus: Restrict 'start-powered-off' property to system emulation

On 1/12/24 03:18, Philippe Mathieu-Daudé wrote: Since the CPUState::start-powered-off property is irrelevant to user emulation, restrict it to system emulation. Signed-off-by: Philippe Mathieu-Daudé --- cpu-target.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) Reviewed-by: R

Re: [PULL 15/21] linux-user/riscv: Add vdso

Hi Richard, Alistair On 10/30/23 14:17, Richard Henderson wrote: > diff --git a/linux-user/riscv/Makefile.vdso b/linux-user/riscv/Makefile.vdso > new file mode 100644 > index 00..2c257dbfda > --- /dev/null > +++ b/linux-user/riscv/Makefile.vdso > @@ -0,0 +1,15 @@ > +include $(BUILD_DIR)/te

Re: [PATCH] accel/tcg: Include missing headers to 'tb-jmp-cache.h'

On 1/12/24 03:24, Philippe Mathieu-Daudé wrote: Due to missing headers, when including "tb-jmp-cache.h" we might get: accel/tcg/tb-jmp-cache.h:21:21: error: field ‘rcu’ has incomplete type 21 | struct rcu_head rcu; | ^~~ accel/tcg/tb-jmp-cache.h:24:9:

Re: [PATCH 01/12] plugins: implement inline operation with cpu_index offset

On 1/12/24 01:23, Pierrick Bouvier wrote: Instead of working on a fixed memory location, allow to index it based on cpu_index and a given offset (ptr + cpu_index * offset). Current semantic is not modified as we use a 0 offset, thus inline operation still targets always the same memory location.

Re: [PATCH 02/12] plugins: add inline operation per vcpu

On 1/12/24 01:23, Pierrick Bouvier wrote: Extends API with three new functions: qemu_plugin_register_vcpu_{tb, insn, mem}_exec_inline_per_vcpu(). Compared to non per_vcpu versions, ptr is now a base, and current cpu_index and an offset are used to compute memory location on which operation happe

Re: [PATCH 04/12] tests/plugin/inline: migrate to new per_vcpu API

On 1/12/24 01:23, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- tests/plugin/inline.c | 17 - 1 file changed, 17 deletions(-) Was this supposed to be together with patch 6? r~ diff --git a/tests/plugin/inline.c b/tests/plugin/inline.c index 6114ebca545..ae5

Re: [PATCH 05/12] tests/plugin/mem: fix race condition with callbacks

On 1/12/24 01:23, Pierrick Bouvier wrote: Introduce a lock so global count is correct. This was found by comparing with new inline per_vcpu inline op. Signed-off-by: Pierrick Bouvier --- tests/plugin/mem.c | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Richard Henderson r~

Re: [PATCH 07/12] tests/plugin/insn: migrate to new per_vcpu API

On 1/12/24 01:23, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- tests/plugin/insn.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson @@ -195,6 +200,7 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,

Re: [PATCH 08/12] tests/plugin/bb: migrate to new per_vcpu API

On 1/12/24 01:23, Pierrick Bouvier wrote: Since we need a fixed offset between count memory location, we now need a contiguous array of CPUCount (instead of array of pointers). Signed-off-by: Pierrick Bouvier --- tests/plugin/bb.c | 54 +++ 1 file c

Re: [PATCH 11/19] qapi/schema: fix QAPISchemaArrayType.check's call to resolve_type

On Thu, Jan 11, 2024 at 4:33 AM Markus Armbruster wrote: > > John Snow writes: > > > On Thu, Nov 23, 2023, 8:03 AM Markus Armbruster wrote: > > > >> John Snow writes: > >> > >> > On Wed, Nov 22, 2023 at 7:59 AM Markus Armbruster > >> > wrote: > >> >> > >> >> John Snow writes: > >> >> > >> >>

Re: [PATCH v2 2/9] hw/hppa/machine: Disable default devices with --nodefaults option

On 1/9/24 17:01, Richard Henderson wrote: On 1/9/24 22:16, Helge Deller wrote: On 1/9/24 10:57, Richard Henderson wrote: On 1/8/24 00:22, del...@kernel.org wrote: From: Helge Deller Add support for the qemu --nodefaults option, which will disable the following default devices: - lsi53c895a S

Re: [PATCH v2 1/2] target/riscv: Add infrastructure for 'B' MISA extension

On Fri, Jan 12, 2024 at 3:38 AM Rob Bradford wrote: > > Add the infrastructure for the 'B' extension which is the union of the > Zba, Zbb and Zbs instructions. > > Signed-off-by: Rob Bradford > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Ali

Re: [PATCH v2 2/2] target/riscv: Add step to validate 'B' extension

On Fri, Jan 12, 2024 at 2:17 AM Rob Bradford wrote: > > If the B extension is enabled warn if the user has disabled any of the > required extensions that are part of the 'B' extension. Conversely > enable the extensions that make up the 'B' extension if it is enabled. > > Signed-off-by: Rob Bradfo

Re: [PATCH 1/5] accel: Rename accel_init_ops_interfaces() to include 'system'

On Thu, Jan 11, 2024 at 10:05 PM Philippe Mathieu-Daudé wrote: > > accel_init_ops_interfaces() is system specific, so > rename it as accel_system_init_ops_interfaces() to > ease navigating the code. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > acce

Re: [PATCH 5/5] target/riscv: Rename tcg_cpu_FOO() to include 'riscv'

On Thu, Jan 11, 2024 at 11:05 PM Philippe Mathieu-Daudé wrote: > > The tcg_cpu_FOO() names are riscv specific, so rename > them as riscv_tcg_cpu_FOO() (as other names in this file) > to ease navigating the code. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair

Re: [PATCH v2 qemu] hw/cxl/device: read from register values in mdev_reg_read()

On Thu, Jan 11, 2024 at 02:59:05PM +, Jonathan Cameron wrote: > From: Hyeonggon Yoo <42.hye...@gmail.com> > > In the current mdev_reg_read() implementation, it consistently returns > that the Media Status is Ready (01b). This was fine until commit > 25a52959f99d ("hw/cxl: Add support for devic

Re: [PATCH v2 24/43] target/riscv: Move misa_mxl_max to class

On Thu, Jan 4, 2024 at 3:44 AM Alex Bennée wrote: > > From: Akihiko Odaki > > misa_mxl_max is common for all instances of a RISC-V CPU class so they > are better put into class. > > Signed-off-by: Akihiko Odaki > Message-Id: <20231213-riscv-v7-3-a760156a3...@daynix.com> > Signed-off-by: Alex Ben

Re: [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once

On Thu, Jan 4, 2024 at 5:04 AM Alex Bennée wrote: > > From: Akihiko Odaki > > misa_mxl_max is now a class member and initialized only once for each > class. This also moves the initialization of gdb_core_xml_file which > will be referenced before realization in the future. > > Signed-off-by: Akih

Re: [PATCH v2 23/43] target/riscv: Remove misa_mxl validation

On Tue, Jan 9, 2024 at 1:43 AM Alex Bennée wrote: > > Alex Bennée writes: > > > From: Akihiko Odaki > > > > It is initialized with a simple assignment and there is little room for > > error. In fact, the validation is even more complex. > > > > Signed-off-by: Akihiko Odaki > > Acked-by: LIU Zhi

Re: [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC

On Wed, Jan 10, 2024 at 5:47 AM Inès Varhol wrote: > > The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO > device will be implemented, its output GPIOs will be connected to the > SYSCFG input GPIOs. > > Tested-by: Philippe Mathieu-Daudé > Reviewed-by: Philippe Mathieu-Daudé >

Re: [PATCH v4 10/17] target/riscv: create finalize_features() for KVM

On Sat, Jan 6, 2024 at 10:09 AM Daniel Henrique Barboza wrote: > > To turn cbom_blocksize and cboz_blocksize into class properties we need > KVM specific changes. > > KVM is creating its own version of these options with a customized > setter() that prevents users from picking an invalid value dur

Re: [PATCH v4 12/17] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]

On Sat, Jan 6, 2024 at 9:09 AM Daniel Henrique Barboza wrote: > > Do the same we did with 'cbom_blocksize' in the previous patch. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 38 +- > 1 file

Re: [RFC PATCH v3 04/30] io: fsync before closing a file channel

On Thu, Jan 11, 2024 at 03:46:02PM -0300, Fabiano Rosas wrote: > > (1) Does this apply to all io channel users, or only migration? > > All file channel users. I meant the whole idea of flushing on close, on whether there will be iochannel users that will prefer not do so? It's a matter of where

Re: [PATCH v2 0/2] target/riscv: Add support for 'B' extension

On Fri, Jan 12, 2024 at 2:17 AM Rob Bradford wrote: > > Add support for the new (fast track) 'B' extension [1] this extension > uses the misa.B bit to indicate that the Zba, Zbb and Zbs extensions are > present. > > Since this extension is not yet frozen it is exposed via the 'x-b' cpu > option. T

Re: [PATCH v4 15/17] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]

On Sat, Jan 6, 2024 at 9:09 AM Daniel Henrique Barboza wrote: > > Keep all class properties in riscv_cpu_properties[]. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 69 +- > 1 file ch

Re: [PATCH v4 16/17] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]

On Sat, Jan 6, 2024 at 9:07 AM Daniel Henrique Barboza wrote: > > Keep all class properties in riscv_cpu_properties[]. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 68 -- > 1 file ch

Re: [PATCH v4 17/17] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]

On Sat, Jan 6, 2024 at 9:09 AM Daniel Henrique Barboza wrote: > > Keep all class properties in riscv_cpu_properties[]. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 110 +++-- > 1 file ch

Re: [PATCH] hw/core: Handle cpu_model_from_type() returning NULL value

Hi Phil, On 1/11/24 18:21, Philippe Mathieu-Daudé wrote: On 11/1/24 08:30, Gavin Shan wrote: On 1/11/24 16:47, Philippe Mathieu-Daudé wrote: Per cpu_model_from_type() docstring (added in commit 445946f4dd):    * Returns: CPU model name or NULL if the CPU class doesn't exist We must check the

[PATCH] vhost-user.rst: Fix vring address description

There is no "size" field in vring address structure. Remove it. Fixes: 5fc0e00291 ("Add vhost-user protocol documentation") Signed-off-by: Andrey Ignatov --- docs/interop/vhost-user.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/interop/vhost-user.rst b/docs/i

Re: [PATCH v4 00/17] target/riscv: deprecate riscv_cpu_options[]

On Sat, Jan 6, 2024 at 9:07 AM Daniel Henrique Barboza wrote: > > Hi, > > This new version contains changes due to a rebase with current > riscv-to-apply.next, after "[PATCH v13 00/26] riscv: RVA22 profiles > support" was queued. > > Most notable change is a new patch (12) that was added to handle

Re: [PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off

On Wed, Jan 10, 2024 at 2:03 PM Himanshu Chauhan wrote: > > When sdtrig is turned off by "sdtrig=false" option, raise > and illegal instruction exception on any read/write to > sdtrig CSRs. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/csr.c | 20 > 1 file changed

Re: [PATCH 1/2] target/riscv: Export sdtrig as an extension and ISA string

On Wed, Jan 10, 2024 at 2:03 PM Himanshu Chauhan wrote: > > This patch makes the debug trigger (sdtrig) capability > as an extension and exports it as an ISA string. The sdtrig > extension may or may not be implemented in a system. The > -cpu rv64,sdtrig= > option can be used to dynamicaly

Re: [PATCH v2 38/43] plugins: add an API to read registers

On 1/3/24 21:33, Alex Bennée wrote: We can only request a list of registers once the vCPU has been initialised so the user needs to use either call the get function on vCPU initialisation or during the translation phase. We don't expose the reg number to the plugin instead hiding it behind an op

Re: [PATCH 04/12] tests/plugin/inline: migrate to new per_vcpu API

On 1/12/24 02:10, Richard Henderson wrote: On 1/12/24 01:23, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- tests/plugin/inline.c | 17 - 1 file changed, 17 deletions(-) Was this supposed to be together with patch 6? My goal was to have a version that stil

Re: [PATCH 0/2] Export debug triggers as an extension

On Thu, Jan 11, 2024 at 5:20 AM Daniel Henrique Barboza wrote: > > Himanshu, > > We spoke offline but let's make everyone aware: > > - 'sdtrig' should be marked with 'x-' and be an experimental extension since > the spec isn't yet frozen; > > - Alvin sent a patch to the ML adding the 'mcontext' CS

[PATCH 1/4] target/xtensa: add translation for wsr.mpucfg

Although MPUCFG is not writable, the opcode wsr.mpucfg is defined and it just does nothing. Define wsr.mpucfg as nop. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index

[PATCH 3/4] tests/tcg/xtensa: tidy test linker script

Drop MEMORY clause and related size definitions and output section region specifications. Drop .rodata output section as the tests don't use it. Add DATA_SEGMENT_ALIGN/DATA_SEGMENT_END around .data and .bss to let the linker make an RW segment for data. Reserve 1M for stack instead of almost 128M.

[PATCH 4/4] tests/tcg/xtensa: fix SR test for configs with MPU

- atomctl is available not only in the presence of s32c1i, but also with the exclusive access option - cacheadrdis SR has the same number as cacheattr, mpuenb SR has the same number as rasid and mpucfg SR has the same number as dtlbcfg, add MPU case to the tests of these SR numbers Signed-of

[PATCH 0/4] target/xtensa: provide configuration with MPU

Hello, this series adds xtensa core 'sample_controller32' with 32 foreground entry MPU, adds missing translation for the 'wsr.mpucfg' opcode and makes xtensa/tcg/tests work with the new core. Max Filippov (4): target/xtensa: add translation for wsr.mpucfg target/xtensa: import sample_controll

Re: [PATCH 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules

On 1/11/24 22:16, Thomas Huth wrote: The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and some few special characters"). For the "power5+" and "power7+" CPU names, there is currently a hack in type_name_is_valid() to still al

Re: [PATCH v2 2/9] hw/hppa/machine: Disable default devices with --nodefaults option

On 11/01/2024 23.28, Helge Deller wrote: On 1/9/24 17:01, Richard Henderson wrote: On 1/9/24 22:16, Helge Deller wrote: On 1/9/24 10:57, Richard Henderson wrote: On 1/8/24 00:22, del...@kernel.org wrote: From: Helge Deller Add support for the qemu --nodefaults option, which will disable the

Re: [PATCH 1/2] target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules

On 12/01/2024 05.57, Harsh Prateek Bora wrote: On 1/11/24 22:16, Thomas Huth wrote: The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and some few special characters"). For the "power5+" and "power7+" CPU names, there is curre

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