On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> When backend supports the VHOST_BACKEND_F_DESC_ASID feature
> and all the data vqs can support one or more descriptor group
> to host SVQ vrings and descriptors, we assign them a different
> ASID than where its buffers reside in guest memory add
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Generalize duplicated condition check for the last vq of vdpa
> device to a common function.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/vhost-vdpa.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 delet
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Subsequent patches attempt to release VhostVDPAShared resources,
> for example iova tree to free and memory listener to unregister,
> in vdpa_dev_cleanup(). Instead of checking against the vq index,
> which is not always available in all of the
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> So that it can be freed from vhost_vdpa_cleanup on
> the last deref. The next few patches will try to
> make iova tree life cycle not depend on memory
> listener, and there's possiblity to keep iova tree
> around when memory mapping is not chang
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Will be used in next patches.
>
> Signed-off-by: Si-Wei Liu
> ---
> include/hw/virtio/vhost-vdpa.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/hw/virtio/vhost-vdpa.h b/include/hw/virtio/vhost-vdpa.h
> index 7b8d3bf..
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> svq_switching indicates the case where SVQ mode change
> is on going. Positive (1) means switching from the
> normal passthrough mode to SVQ mode, and negative (-1)
> meaning switch SVQ back to the passthrough; zero (0)
> indicates that there's
On 11/01/2024 08.37, gaosong wrote:
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/
So why is it NOTFORMERG
Hi Gavin,
On 11/1/24 08:30, Gavin Shan wrote:
Hi Phil,
On 1/11/24 16:47, Philippe Mathieu-Daudé wrote:
Per cpu_model_from_type() docstring (added in commit 445946f4dd):
* Returns: CPU model name or NULL if the CPU class doesn't exist
We must check the return value in order to avoid surpri
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> This patch series contain several enhancements to SVQ live migration downtime
> for vDPA-net hardware device, specifically on mlx5_vdpa. Currently it is based
> off of Eugenio's RFC v2 .load_setup series [1] to utilize the shared facility
> and
On 11/1/24 03:29, gaosong wrote:
Hi,
在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道:
From: Tianrui Zhao
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> The descriptor group for SVQ ASID allows the guest memory mapping
> to retain across SVQ switching, same as how isolated CVQ can do
> with a different ASID than the guest GPA space. Introduce an
> evaluation function to judge whether to flush or
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> So that the free of iova tree struct can be safely deferred to
> until the last vq referencing it goes away.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/vhost-vdpa.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --gi
On 11/01/2024 08.25, gaosong wrote:
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Today memory listener is unregistered in vhost_vdpa_reset_status
> unconditionally, due to which all the maps will be flushed away
> from the iotlb. However, map flush is not always needed, and
> doing it from performance hot path may have inneg
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 05:31:28PM +0800, Xiaoyao Li wrote:
> Date: Wed, 10 Jan 2024 17:31:28 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
>
On Fri, Dec 8, 2023 at 2:52 AM Si-Wei Liu wrote:
>
> Leverage the IOTLB_PERSIST and DESC_ASID features to achieve
> a slightly light weight reset path, without resorting to
> suspend and resume. Not as best but it offers significant
> time saving too, which should somehow play its role in live
> m
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 07:52:38PM +0800, Xiaoyao Li wrote:
> Date: Wed, 10 Jan 2024 19:52:38 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 03/16] i386/cpu: Consolidate the use of topo_info in
> cpu_x86_cpuid()
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
>
On 10/01/2024 00.22, Ilya Leoshkevich wrote:
Add a small test to prevent regressions. Userspace runs in primary
mode, so LAE should always set the access register to 0.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/lae.c | 25 ++
On Mon, Nov 27, 2023 at 05:25:46PM -0300, Fabiano Rosas wrote:
> Make sure the data is flushed to disk before closing file
> channels. This will ensure data is on disk at the end of a migration
> to file.
Looks reasonable, but just two (possibly naive) questions:
(1) Does this apply to all io cha
在 2024/1/11 下午4:20, Thomas Huth 写道:
On 11/01/2024 08.37, gaosong wrote:
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@l
On 05/01/2024 09.38, Zhao Liu wrote:
From: Zhao Liu
Add two spelling check options (--codespell and --codespellfile) to
enhance spelling check through dictionary, which copied the Linux
kernel's implementation in checkpatch.pl.
This check uses the dictionary at "/usr/share/codespell/dictionary
Hi Xiaoyao,
On Thu, Jan 11, 2024 at 11:19:34AM +0800, Xiaoyao Li wrote:
> Date: Thu, 11 Jan 2024 11:19:34 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with
> specific topology level
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
On 11/01/2024 09.50, gaosong wrote:
在 2024/1/11 下午4:20, Thomas Huth 写道:
On 11/01/2024 08.37, gaosong wrote:
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/2
On Thu, 2024-01-11 at 09:37 +0100, Thomas Huth wrote:
> On 10/01/2024 00.22, Ilya Leoshkevich wrote:
> > Add a small test to prevent regressions. Userspace runs in primary
> > mode, so LAE should always set the access register to 0.
> >
> > Signed-off-by: Ilya Leoshkevich
> > ---
> > tests/tcg/
Hi Xiaoyao,
On Thu, Jan 11, 2024 at 01:53:53PM +0800, Xiaoyao Li wrote:
> > -cores_per_pkg = topo_info.cores_per_die * topo_info.dies_per_pkg;
> > +cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die
> > *
> > +topo_info.dies_per_pkg;
>
> Nit. mayb
Hi Xiaoyao,
On Thu, Jan 11, 2024 at 02:04:53PM +0800, Xiaoyao Li wrote:
> Date: Thu, 11 Jan 2024 14:04:53 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
> > Linux kernel (from v6.
v1: https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg01596.html
v1 -> v2: Fix building the test with clang (Thomas).
Hi,
Ido has noticed that LAE sets a wrong access register and proposed a
fix. This series fixes the issue and adds a test.
Best regards,
Ilya
Ilya Leoshkevich (2):
ta
Add a small test to prevent regressions. Userspace runs in primary
mode, so LAE should always set the access register to 0.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/lae.c | 31 +++
2 files changed, 32 insert
John Snow writes:
> On Wed, Nov 22, 2023, 9:02 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Differentiate between "actively in the process of checking" and
>> > "checking has completed". This allows us to clean up the types of some
>> > internal fields such as QAPISchemaObjectType
LAE should set the access register corresponding to the first operand,
instead, it always modifies access register 1.
Co-developed-by: Ido Plat
Cc: qemu-sta...@nongnu.org
Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions")
Reviewed-by: David Hildenbrand
Signed-off-by: Ilya
On 11/1/24 08:10, Thomas Huth wrote:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/
So why is it NOTFORMERGE ? Don't we want to test KVM-only builds
John Snow writes:
> On Thu, Nov 23, 2023, 8:03 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > On Wed, Nov 22, 2023 at 7:59 AM Markus Armbruster
>> > wrote:
>> >>
>> >> John Snow writes:
>> >>
>> >> > There's more conditionals in here than we can reasonably pack into a
>> >> > ter
ping
On 10/1/24 20:53, Philippe Mathieu-Daudé wrote:
The "aarch64" property is added to ARMCPU when the
ARM_FEATURE_AARCH64 feature is available. Rather than
checking whether the QOM property is present, directly
check the feature.
Suggested-by: Markus Armbruster
Signed-off-by: Philippe Mathieu-Daud
On 1/10/24 21:28, Matthew Rosato wrote:
On 1/10/24 1:30 PM, Cédric Le Goater wrote:
On 9/12/23 13:41, Thomas Huth wrote:
From: Janosch Frank
Bound APQNs have to be reset before tearing down the secure config via
s390_machine_unprotect(). Otherwise the Ultravisor will return a error
code.
So
On Thu, 11 Jan 2024 09:39:18 +,
Philippe Mathieu-Daudé wrote:
>
> On 10/1/24 20:53, Philippe Mathieu-Daudé wrote:
> > The "aarch64" property is added to ARMCPU when the
> > ARM_FEATURE_AARCH64 feature is available. Rather than
> > checking whether the QOM property is present, directly
> > che
在 2024/1/11 下午5:04, Thomas Huth 写道:
On 11/01/2024 09.50, gaosong wrote:
在 2024/1/11 下午4:20, Thomas Huth 写道:
On 11/01/2024 08.37, gaosong wrote:
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
On Mon, Nov 27, 2023 at 05:25:47PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Add utility methods that will be needed when implementing 'fixed-ram'
> migration capability.
>
> qemu_file_is_seekable
> qemu_put_buffer_at
> qemu_get_buffer_at
> qemu_set_offset
> qemu_get_offset
>
> Si
On 11/01/2024 06:22, Philippe Mathieu-Daudé wrote:
On 9/1/24 22:53, Mark Cave-Ayland wrote:
On 08/01/2024 23:06, Philippe Mathieu-Daudé wrote:
On 8/1/24 20:20, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned
On 11/1/24 10:47, Marc Zyngier wrote:
On Thu, 11 Jan 2024 09:39:18 +,
Philippe Mathieu-Daudé wrote:
On 10/1/24 20:53, Philippe Mathieu-Daudé wrote:
The "aarch64" property is added to ARMCPU when the
ARM_FEATURE_AARCH64 feature is available. Rather than
checking whether the QOM property is
Am 11.01.24 um 10:43 schrieb Cédric Le Goater:
[...]
On a side note, I am also seeing :
Michael?
[ 73.989688] [ cut here ]
[ 73.989696] unexpected non zero alert.mask 0x20
[ 73.989748] WARNING: CPU: 9 PID: 4503 at arch/s390/kvm/interrupt.c:3214
kvm_s390_gi
Whilst 128k is more than enough for a typical Declaration ROM, a C compiler
configured to produce an unstripped debug binary can generate a ROM image that
exceeds this limit. Increase the maximum size to 1Mb to help make life easier
for developers.
Signed-off-by: Mark Cave-Ayland
---
include/hw/
Declaration ROM binary images can be any arbitrary size, however if a host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(!(iotlb & ~TARGET_PAGE_MASK))" check in tlb_set_page_full().
Ensure that the host ROM memory region is aligned to qemu_target_page_size()
This series introduces a new nubus-virtio-mmio device which can be plugged into
the q800 machine to enable a 68k Classic MacOS guest to access virtio devices
such as virtio-9p-device (host filesharing), virtio-gpu (extended framebuffer
support) and virtio-tablet-device (absolute positioning).
Once
The nubus-virtio-mmio device is a Nubus card that contains a set of 32
virtio-mmio
devices and a goldfish PIC similar to the m68k virt machine that can be plugged
into the m68k q800 machine.
There are currently a number of drivers under development that can be used in
conjunction with this device
On Mon, Nov 27, 2023 at 05:25:48PM -0300, Fabiano Rosas wrote:
> Add a new migration capability 'fixed-ram'.
>
> The core of the feature is to ensure that each RAM page has a specific
> offset in the resulting migration stream. The reasons why we'd want
> such behavior are:
>
> - The resulting f
On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote:
> Hi,
>
> In this v3:
>
> Added support for the "file:/dev/fdset/" syntax to receive multiple
> file descriptors. This allows the management layer to open the
> migration file beforehand and pass the file descriptors to QEMU. We
> nee
From: Samuel Tardieu
Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending
When interpreting CPU dumps where FEAT_NV and FEAT_NV2 are in use,
it's helpful to include the values of HCR_EL2.{NV,NV1,NV2} in the CPU
dump format, as a way of distinguishing when we are in EL1 as part of
executing guest-EL2 and when we are just in normal EL1.
Add the bits to the end of the log
repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240111
for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362:
target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09
14:4
Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for
the Neoverse N2 and Neoverse V1 CPUs.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu.c | 5 -
target/arm/tcg/cpu64.c
From: Inès Varhol
This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC
as well as a dedicated documentation file.
The implementation is derived from the Netduino Plus 2 machine.
There are no peripherals implemented yet, only memory regions.
Tested-by: Philippe Mathieu-Daudé
Rev
Mark up the cpreginfo structs for the GIC CPU registers to indicate
the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ
in the Arm ARM.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
hw/intc/arm_gicv3_cpuif.c | 11 +++
1 file cha
From: Philippe Mathieu-Daudé
QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 20240104141159.53883-1-phi...@linaro.org
Signed-off-by: Peter Mayde
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets below 0x100; all of these
registers are redirected to memory regardless of the value of
HCR_EL2.NV1.
Signed-off-by: Peter Mayde
FEAT_NV and FEAT_NV2 will allow EL1 to attempt to access cpregs that
only exist at EL2. This means we're going to want to run their
accessfns when the CPU is at EL1. In almost all cases, the behaviour
we want is "the accessfn returns OK if at EL1".
Mostly the accessfn already does the right thing;
FEAT_NV requires (per I_JKLJK) that when HCR_EL2.{NV,NV1} is {1,1} the
unprivileged-access instructions LDTR, STTR etc behave as normal
loads and stores. Implement the check that handles this.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/tcg
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the
Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2
support to FEAT_NV for the latter two CPU types.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
docs/system/arm/emulat
When HCR_EL2.{NV,NV1} is {1,1} we must trap five extra registers to
EL2: VBAR_EL1, ELR_EL1, SPSR_EL1, SCXTNUM_EL1 and TFSR_EL1.
Implement these traps.
This trap does not apply when FEAT_NV2 is implemented and enabled;
include the check that HCR_EL2.NV2 is 0 here, to save us having
to come back and
We already print various lines of information when we take an
exception, including the ELR and (if relevant) the FAR. Now
that FEAT_NV means that we might report something other than
the old PSTATE to the guest as the SPSR, it's worth logging
this as well.
Signed-off-by: Peter Maydell
Reviewed-by
FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,1} the handling
of some of the page table attribute bits changes for the EL1&0
translation regime:
* for block and page descriptors:
- bit [54] holds PXN, not UXN
- bit [53] is RES0, and the effective value of UXN is 0
- bit [6], AP[1], is t
If FEAT_NV2 redirects a system register access to a memory offset
from VNCR_EL2, that access might fault. In this case we need to
report the correct syndrome information:
* Data Abort, from same-EL
* no ISS information
* the VNCR bit (bit 13) is set
and the exception must be taken to EL2.
Sav
When FEAT_NV is turned on via the HCR_EL2.NV bit, ERET instructions
are trapped, with the same syndrome information as for the existing
FEAT_FGT fine-grained trap (in the pseudocode this is handled in
AArch64.CheckForEretTrap()).
Rename the DisasContext and tbflag bits to reflect that they are
no
For FEAT_NV2, a new system register VNCR_EL2 holds the base
address of the memory which nested-guest system register
accesses are redirected to. Implement this register.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/cpu.h| 3 +++
target/
From: Nikita Ostrenkov
Signed-off-by: Nikita Ostrenkov
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20231219105510.4907-1-n.ostren...@gmail.com
[PMM: fixed stray whitespace]
Signed-off-by: Peter Maydell
---
hw/arm/fsl-imx6.c | 3 +++
hw/arm/Kconfig| 1 +
2 files changed, 4 insertions(+
FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,0} and an exception
is taken from EL1 to EL1 then the reported EL in SPSR_EL1.M should be
EL2, not EL1. Implement this behaviour.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/helper.c | 6 ++
The TBFLAG_A64 TB flag bits go in flags2, which for AArch64 guests
we know is 64 bits. However at the moment we use FIELD_EX32() and
FIELD_DP32() to read and write these bits, which only works for
bits 0 to 31. Since we're about to add a flag that uses bit 32,
switch to FIELD_EX64() and FIELD_DP64(
Currently the code in target/arm/helper.c mostly checks the PAN bits
in env->pstate or env->uncached_cpsr directly when it wants to know
if PAN is enabled, because in most callsites we know whether we are
in AArch64 or AArch32. We do have an arm_pan_enabled() function, but
we only use it in a few p
The HCR_EL2.TSC trap for trapping EL1 execution of SMC instructions
has a behaviour change for FEAT_NV when EL3 is not implemented:
* in older architecture versions TSC was required to have no
effect (i.e. the SMC insn UNDEFs)
* with FEAT_NV, when HCR_EL2.NV == 1 the trap must apply
(i.e.
The hypervisor can deliver (virtual) LPIs to a guest by setting up a
list register to have an intid which is an LPI. The GIC has to treat
these a little differently to standard interrupt IDs, because LPIs
have no Active state, and so the guest will only EOI them, it will
not also deactivate them.
For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled
even when the PSTATE.PAN bit is set. Implement this by having
arm_pan_enabled() return false in this situation.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/helper.c | 3 +++
With FEAT_NV2, the condition for when SPSR_EL1.M should report that
an exception was taken from EL2 changes.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/helper.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff
FEAT_NV2 requires that when HCR_EL2.{NV,NV2} == 0b11 then accesses by
EL1 to certain system registers are redirected to RAM. The full list
of affected registers is in the table in rule R_CSRPQ in the Arm ARM.
The registers may be normally accessible at EL1 (like ACTLR_EL1), or
normally UNDEF at EL
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This covers all the remaining offsets at 0x200 and
above, except for the GIC ICH_* registers.
(Note that because we don't implement FEAT_SPE, FEAT_TRF,
F
From: Samuel Tardieu
Update the number of priority bits for a number of existing
SoCs according to their technical documentation:
- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
Message-id: 20240106181503.1746200
FEAT_NV requires that when HCR_EL2.NV is set reads of the CurrentEL
register from EL1 always report EL2 rather than the real EL.
Implement this.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/tcg/translate-a64.c | 9 +++--
1 file changed,
The FEAT_NV HCR_EL2.AT bit enables trapping of some address
translation instructions from EL1 to EL2. Implement this behaviour.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/helper.c | 21 +++--
1 file changed, 15 insertions(
The alias registers like SCTLR_EL12 only exist when HCR_EL2.E2H
is 1; they should UNDEF otherwise. We weren't implementing this.
Add an intercept of the accessfn for these aliases, and implement
the UNDEF check.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
For FEAT_NV, accesses to system registers and instructions from EL1
which would normally UNDEF there but which work in EL2 need to
instead be trapped to EL2. Detect this both for "we know this will
UNDEF at translate time" and "we found this UNDEFs at runtime", and
make the affected registers trap
FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the
feature is enabled, allow these bits to be written, and flush the
TLBs for the bits which affect page table interpretation.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/cpu
From: Inès Varhol
This patch adds a new STM32L4x5 SoC, it is necessary to add support for
the B-L475E-IOT01A board.
The implementation is derived from the STM32F405 SoC.
The implementation contains no peripherals, only memory regions are
implemented.
Tested-by: Philippe Mathieu-Daudé
Reviewed-b
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets 0x100 to 0x160.
Many (but not all) of the registers in this range have _EL12 aliases,
and the slot in memory is shared between
From: Samuel Tardieu
A SoC will not have a direct access to the NVIC embedded in its ARM
core. By aliasing the "num-prio-bits" property similarly to what is
done for the "num-irq" one, a SoC can easily configure it on its
armv7m instance.
Signed-off-by: Samuel Tardieu
Reviewed-by: Peter Maydell
In handle_sys() we don't do the check for whether the register is
marked as needing an FPU/SVE/SME access check until after we've
handled the special cases covered by ARM_CP_SPECIAL_MASK. This is
conceptually the wrong way around, because if for example we happen
to implement an FPU-access-checked
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets 0x168 to 0x1f8.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/helper.c
Under FEAT_NV2, when HCR_EL2.{NV,NV2} == 0b11 at EL1, accesses to the
registers SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 and TFSR_EL2 (which
would UNDEF without FEAT_NV or FEAT_NV2) should instead access the
equivalent EL1 registers SPSR_EL1, ELR_EL1, ESR_EL1, FAR_EL1 and
TFSR_EL1.
Because there are on
For FEAT_VHE, we define a set of register aliases, so that for instance:
* the SCTLR_EL1 either accesses the real SCTLR_EL1, or (if E2H is 1)
SCTLR_EL2
* a new SCTLR_EL12 register accesses SCTLR_EL1 if E2H is 1
However when we create the 'new_reg' cpreg struct for the SCTLR_EL12
register, we
The CTR_EL0 register has some bits which allow the implementation to
tell the guest that it does not need to do cache maintenance for
data-to-instruction coherence and instruction-to-data coherence.
QEMU doesn't emulate caches and so our cache maintenance insns are
all NOPs.
We already have some m
FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the
feature is enabled, allow this bit to be written in HCR_EL2.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Tested-by: Miguel Luis
---
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 3 +++
2 files changed
tags/pull-loongarch-20240111
for you to fetch changes up to 428a6ef4396aa910c86e16c1e4409e3927a3698e:
hw/intc/loongarch_extioi: Add vmstate post_load support (2024-01-11 19:22:47
+0800)
pull-loongarc
On 11/1/24 10:51, gaosong wrote:
在 2024/1/11 下午5:04, Thomas Huth 写道:
On 11/01/2024 09.50, gaosong wrote:
在 2024/1/11 下午4:20, Thomas Huth 写道:
On 11/01/2024 08.37, gaosong wrote:
LoongArch no support these cmds or some problems .
- "gva2gpa 0",
- "memsave 0 4096 \"/dev/null\"",
- "x
From: Tianrui Zhao
Implement kvm_arch_get/set_registers interfaces, many regs
can be get/set in the function, such as core regs, csr regs,
fpu regs, mp state, etc.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Change-Id: Ia8fc48fe08b1768853f7729e77d37cdf270031e4
tags/pull-loongarch-20240111
for you to fetch changes up to 428a6ef4396aa910c86e16c1e4409e3927a3698e:
hw/intc/loongarch_extioi: Add vmstate post_load support (2024-01-11 19:22:47
+0800)
pull-loongarc
From: Tianrui Zhao
Implement kvm_arch_handle_exit for loongarch. In this
function, the KVM_EXIT_LOONGARCH_IOCSR is handled,
we read or write the iocsr address space by the addr,
length and is_write argument in kvm_run.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Richard
From: Tianrui Zhao
Use the scripts/update-linux-headers.sh to synchronize linux
headers from linux v6.7.0-rc8. We mainly want to add the
loongarch linux headers and then add the loongarch kvm support
based on it.
Signed-off-by: Tianrui Zhao
Acked-by: Song Gao
Message-Id: <20240105075804.122859
From: Bibo Mao
There are two interface pairs for MemoryRegionOps, read/write and
read_with_attrs/write_with_attrs. The later is better for ipi device
emulation since initial cpu can be parsed from attrs.requester_id.
And requester_id can be overrided for IOCSR_IPI_SEND and mail_send
function whe
From: Tianrui Zhao
Supplement vcpu env initial when vcpu reset, including
init vcpu CSR_CPUID,CSR_TID to cpu->cpu_index. The two
regs will be used in kvm_get/set_csr_ioctl.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-Id: <20240105075804.1228596-4-zhaot
From: Bibo Mao
LoongArch system has iocsr address space, most iocsr registers are
per-board, however some iocsr register spaces banked for percpu such
as ipi mailbox and extioi interrupt status. For banked iocsr space,
each cpu has the same iocsr space, but separate data.
This patch changes iocs
From: Tianrui Zhao
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>
From: Tianrui Zhao
In preparation of supporting KVM in the next commit.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>
[PMD: Split from bigger patch, part 1]
Signed-off-by: Philippe Mathieu-Daudé
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