Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.h | 2 +-
tcg/sparc64/tcg-target.c.inc | 16 ++--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
index ae2910c4ee.
Use "test x,x" when the bit is one of the 4 sign bits.
Use "bt imm,x" otherwise.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-con-set.h | 6 ++--
tcg/i386/tcg-target-con-str.h | 1 +
tcg/i386/tcg-target.c.inc | 54 +++
3 files changed, 53 inserti
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.h | 2 +-
tcg/tci.c| 14 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 609b2f4e4a..a076f401d2 100644
--- a/tc
Signed-off-by: Richard Henderson
Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org>
[PMD: Split from bigger patch, part 1/2]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20231108145244.72421-1-phi...@linaro.org>
---
tcg/arm/tcg-target.c.inc | 32 +--
Merge tcg_out_testi into tcg_out_cmp and adjust the two uses.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 95 ---
2 files changed, 60 insertions(+), 37 deletions(-)
d
Return the x86 condition codes to use after the compare.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-tar
Srivatsa Vaddagiri writes:
> * Philippe Mathieu-Daud? [2024-01-09 14:31:03]:
>
>> Hi Srivatsa,
>>
>> On 9/1/24 10:00, Srivatsa Vaddagiri wrote:
>> > Specify the location of device-tree and its size, as Gunyah requires the
>> > device-tree to be parsed before VM can begin its execution.
>> >
>>
Hello,
Please review the patch-set version 10.
I have incorporated review comments from Cedric.
v10:
- Moved aspeed-apb2opb to hw/misc directory
- Moved scratchpad to lbus files.
- Moved fsi-slave to fsi files.
- Merged opb changes in the aspeed-apb2opb files
- Reduced number of config o
This is a part of patchset where FSI bus is introduced.
The FSI bus is a simple bus where FSI master is attached.
The FSI slave: The slave is the terminal point of the FSI bus for
FSI symbols addressed to it. Slaves can be cascaded off of one
another. The slave's configuration registers appear in
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with some
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI master. CFAM is hanging out of FSI master which is a
bus controller.
The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER c
Added basic qtests for FSI model.
Acked-by: Thomas Huth
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
tests/qtest/aspeed-fsi-test.c | 205 ++
tests/qtest/meson.build | 1 +
2 files changed, 206 insertions(+)
create mode 100644 tests/q
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
The On-Chip
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table and FSI slave registers.
The scratchpad provides a set of non-functional registers. The firmware
is f
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang o
Added maintainer for IBM FSI model
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 00ec1f7eca..79f97a3fb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3569,6 +3569,14 @@ F:
Hello Cedric,
include/hw/fsi/aspeed-apb2opb.h | 34
aspeed-apb2opb is a HW logic bridging the FSI world and Aspeed. It
doesn't belong to the FSI susbsytem. Since we don't have a directory
for platform specific devices, I think the model shoud go under hw/misc/.
Moved it to hw/misc di
Documentation for IBM FSI model.
Signed-off-by: Cédric Le Goater
Signed-off-by: Ninad Palsule
---
docs/specs/fsi.rst | 138 +++
docs/specs/index.rst | 1 +
2 files changed, 139 insertions(+)
create mode 100644 docs/specs/fsi.rst
diff --git a/docs/sp
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication wit
From: Nabih Estefan Diaz
[Changes since v11]
Was running into error syncing into master. It seemed to be related to a
hash problem introduced in patchset 10 (unrelated to the macOS build
issue). carried the patches from v9 (before the syncing problem) and
added the fixes from patchsets 10 and 11
From: Nabih Estefan Diaz
Implemented GMAC IRQ Handling and added relevant trace-events
Change-Id: I7a2d3cd3f493278bcd0cf483233c1e05c37488b7
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/net/npcm_gmac.c | 40
hw/net/trace-events | 1 +
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Change-Id: I2e1dbaecf8be9ec7eab55cb54f7fdeb0715b8275
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estef
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Added relevant trace-events
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
Change-Id: I14c42c628258804030f0583889882842bde0d972
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 2 ++
hw/arm/npcm7xx.c| 2 ++
include/hw/arm/npc
From: Hao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
hw/arm/npcm7xx.c | 36 ++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2 deletion
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/npcm_gmac-test.c | 132 +++
1 file changed, 132 insertions(+)
diff -
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP N
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan
Reviewed-by: Tyrone Ting
---
tests/qtest/meson.build | 1 +
tests/qtest/
From: Hao Wu
This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E]
(mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmm
On Wed, Jan 10, 2024 at 01:08:01PM -0500, Steven Sistare wrote:
> On 1/10/2024 2:09 AM, Peter Xu wrote:
> > On Wed, Dec 13, 2023 at 10:11:31AM -0800, Steve Sistare wrote:
> >> The existing notifiers should only apply to normal mode.
> >>
> >> No functional change.
> >
> > Instead of adding such ch
On Wed, Jan 10, 2024 at 01:08:41PM -0500, Steven Sistare wrote:
> On 1/10/2024 2:18 AM, Peter Xu wrote:
> > On Wed, Dec 13, 2023 at 10:11:32AM -0800, Steve Sistare wrote:
> >> After calling notifiers, check if an error has been reported via
> >> migrate_set_error, and halt the migration.
> >>
> >>
Hi,
在 2024/1/10 下午5:41, Philippe Mathieu-Daudé 写道:
From: Tianrui Zhao
Implement loongarch kvm set vcpu interrupt interface,
when a irq is set in vcpu, we use the KVM_INTERRUPT
ioctl to set intr into kvm.
Signed-off-by: Tianrui Zhao
Signed-off-by: xianglai li
Reviewed-by: Song Gao
Message-I
On Wed, Jan 10, 2024 at 11:42:18AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote:
> >> Hm, it would be better to avoid the extra maintenance task at the start
> >> of every release, no? It also blocks us from doing n-2 even
> >>
On Wed, Jan 10, 2024 at 04:21:12PM +0100, Cédric Le Goater wrote:
> We also have a [feature request] label under gitlab and some issues are
> tagged with it. I wonder how we can consolidate the 3 sources : wiki,
> gitlab, https://www.qemu.org/docs/master/
Thanks for mentioning the gitlab issues!
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Signed-off-by: Si-Wei Liu
It's better to document which version did this commit sync to.
Thanks
> ---
> include/standard-headers/linux/vhost_types.h | 13 +
> linux-headers/linux/vhost.h | 9 +
> 2 file
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Internal API to get the descriptor group index for a specific virtqueue
> through the VHOST_VDPA_GET_VRING_DESC_GROUP ioctl.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
> ---
> net/vhost-vdpa.c | 19 +++
> 1 f
On Thu, Jan 11, 2024 at 3:44 AM Rob Bradford wrote:
>
> Add requirement that 'A' is enabled for all atomic instructions that
> lack the check. This makes the 64-bit versions consistent with the
> 32-bit versions in the same file.
>
> Signed-off-by: Rob Bradford
Reviewed-by: Alistair Francis
Al
On Fri, Dec 8, 2023 at 2:53 AM Si-Wei Liu wrote:
>
> Getting it ahead at initialization time instead of start time allows
> decision making independent of device status, while reducing failure
> possibility in starting device or during migration.
>
> Adding function vhost_vdpa_probe_desc_group() f
It's found that some of the CPU type names in the array of valid
CPU types are invalid because their corresponding classes aren't
registered, as reported by Peter Maydell.
[gshan@gshan build]$ ./qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
The valid mo
On Mon, Jan 8, 2024 at 6:26 PM Liu, Yuan1 wrote:
>
> > -Original Message-
> > From: Fabiano Rosas
> > Sent: Tuesday, January 9, 2024 4:28 AM
> > To: Liu, Yuan1 ; Hao Xiang
> > Cc: Bryan Zhang ; qemu-devel@nongnu.org;
> > marcandre.lur...@redhat.com; pet...@redhat.com; quint...@redhat.com
On Mon, Jan 8, 2024 at 12:39 PM Fabiano Rosas wrote:
>
> Hao Xiang writes:
>
> > From: Juan Quintela
> >
> > We have to enable it by default until we introduce the new code.
> >
> > Signed-off-by: Juan Quintela
> > ---
> > migration/options.c | 15 +++
> > migration/options.h | 1
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "clusters" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the
module level width in APIC ID,
Hi Peter,
On 1/10/24 00:33, Peter Maydell wrote:
On Fri, 5 Jan 2024 at 15:46, Philippe Mathieu-Daudé wrote:
From: Gavin Shan
Set mc->valid_cpu_types so that the user specified CPU type can be
validated in machine_run_board_init(). We needn't to do the check
by ourselves.
Hi; after this ch
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the
On Thu, Jan 11, 2024 at 3:44 AM Rob Bradford wrote:
>
> Add requirement that 'A' is enabled for all atomic instructions that
> lack the check. This makes the 64-bit versions consistent with the
> 32-bit versions in the same file.
>
> Signed-off-by: Rob Bradford
Thanks!
Applied to riscv-to-apply
On Tue, Jan 09, 2024 at 02:46:18PM +0800, pet...@redhat.com wrote:
> From: Peter Xu
>
> Migration docs grow larger and larger. There are plenty of things we can
> do here in the future, but to start that we'd better reorganize the current
> bloated doc files first and properly organize them into
On 9/1/24 22:53, Mark Cave-Ayland wrote:
On 08/01/2024 23:06, Philippe Mathieu-Daudé wrote:
On 8/1/24 20:20, Mark Cave-Ayland wrote:
Declaration ROM binary images can be any arbitrary size, however if a
host ROM
memory region is not aligned to qemu_target_page_size() then we fail the
"assert(
On Mon, Jan 8, 2024 at 12:28 PM Fabiano Rosas wrote:
>
> "Liu, Yuan1" writes:
>
> >> -Original Message-
> >> From: Hao Xiang
> >> Sent: Saturday, January 6, 2024 7:53 AM
> >> To: Fabiano Rosas
> >> Cc: Bryan Zhang ; qemu-devel@nongnu.org;
> >> marcandre.lur...@redhat.com; pet...@redhat.
Per cpu_model_from_type() docstring (added in commit 445946f4dd):
* Returns: CPU model name or NULL if the CPU class doesn't exist
We must check the return value in order to avoid surprises, i.e.:
$ qemu-system-arm -machine virt -cpu cortex-a9
qemu-system-arm: Invalid CPU model: cortex-a9
On 11/1/24 07:47, Philippe Mathieu-Daudé wrote:
Per cpu_model_from_type() docstring (added in commit 445946f4dd):
* Returns: CPU model name or NULL if the CPU class doesn't exist
We must check the return value in order to avoid surprises, i.e.:
$ qemu-system-arm -machine virt -cpu cortex-
On Mon, Nov 27, 2023 at 05:25:44PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> Introduce basic pwritev/preadv support in the generic channel layer.
> Specific implementation will follow for the file channel as this is
> required in order to support migration streams with fixed locatio
On Wed, Jan 10, 2024 at 03:19:05PM -0800, Dan Williams wrote:
> David Hildenbrand wrote:
> > On 09.01.24 17:52, Jonathan Cameron wrote:
> > > On Thu, 4 Jan 2024 10:39:41 -0700
> > > Alex Williamson wrote:
> > >
> > >> On Thu, 4 Jan 2024 16:40:39 +
> > >> Ankit Agrawal wrote:
> > >>
> > >>> H
On Mon, Nov 27, 2023 at 05:25:45PM -0300, Fabiano Rosas wrote:
> From: Nikolay Borisov
>
> The upcoming 'fixed-ram' feature will require qemu to write data to
> (and restore from) specific offsets of the migration file.
>
> Add a minimal implementation of pwritev/preadv and expose them via the
>
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Same as the previous commit, but do it for cvq instead of data vqs.
>
> Signed-off-by: Si-Wei Liu
> ---
> net/vhost-vdpa.c | 21 +
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/net/vhost-vdpa.c b/net/v
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.html#maintainer-controlled-job-variables
Sig
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Add the desc_group field to struct vhost_vdpa, and get it
> populated when the corresponding vq is initialized at
> net_vhost_vdpa_init. If the vq does not have descriptor
> group capability, or it doesn't have a dedicated ASID
> group to host d
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/
So why is it NOTFORMERGE ? Don't we want to test KVM-only builds for
loongarch in the long run?
Th
Hi,
在 2024/1/11 下午3:08, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Full build config to run CI tests on a Loongarch64 host.
Forks might enable this by setting LOONGARCH64_RUNNER_AVAILABLE
in their CI namespace settings, see:
https://www.qemu.org/docs/master/devel/ci.htm
Hi Phil,
On 1/11/24 16:47, Philippe Mathieu-Daudé wrote:
Per cpu_model_from_type() docstring (added in commit 445946f4dd):
* Returns: CPU model name or NULL if the CPU class doesn't exist
We must check the return value in order to avoid surprises, i.e.:
$ qemu-system-arm -machine virt -c
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Make vhost_svq_vring_write_descs able to work with GPA directly
> without going through iova tree for translation. This will be
> needed in the next few patches where the SVQ has dedicated
> address space to host its virtqueues. Instead of havin
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Move it a few lines ahead to make function call easier for those
> before it. No funtional change involved.
Typo for functional.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
> ---
> net/vhost-vdpa.c | 36 ++-
On Fri, Dec 8, 2023 at 2:50 AM Si-Wei Liu wrote:
>
> Since shadow_data is now shared in the parent data struct, it
> just needs to be set only once by the first vq. This change
> will make shadow_data independent of svq enabled state, which
> can be optionally turned off when SVQ descritors and de
On Fri, Dec 8, 2023 at 2:52 AM Si-Wei Liu wrote:
>
> Previous commits had it removed. Now adding it back because
> this function will be needed by next patches.
Need some description to explain why. Because it should not be needed
as we have a "parent" structure now, anything that is common could
Hi,
在 2024/1/11 下午3:10, Thomas Huth 写道:
On 02/01/2024 18.22, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Used to test
https://lore.kernel.org/qemu-devel/20231228084051.3235354-1-zhaotian...@loongson.cn/
So why is it NOTFORMERGE ? Don't we want to test KVM-only bu
201 - 265 of 265 matches
Mail list logo
