Re: [PATCH v7 03/16] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()

On 1/8/2024 4:27 PM, Zhao Liu wrote: From: Zhao Liu In cpu_x86_cpuid(), there are many variables in representing the cpu topology, e.g., topo_info, cs->nr_cores/cs->nr_threads. Please use comma instead of slash. cs->nr_cores/cs->nr_threads looks like one variable. Since the names of cs->n

Re: [PATCH] io: add trace event when cancelling TLS handshake

On 10/1/24 12:16, Daniel P. Berrangé wrote: Signed-off-by: Daniel P. Berrangé --- io/channel-tls.c | 1 + io/trace-events | 1 + 2 files changed, 2 insertions(+) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] chardev: close QIOChannel before unref'ing

Hi On Wed, Jan 10, 2024 at 3:16 PM Daniel P. Berrangé wrote: > > The chardev socket backend will unref the QIOChannel object while > it is still potentially open. When using TLS there could be a > pending TLS handshake taking place. If the channel is left open > then when the TLS handshake callba

Re: [PATCH] target/s390x/kvm/pv: Provide some more useful information if decryption fails

On 09/01/2024 17.51, Cédric Le Goater wrote: On 1/9/24 15:30, Thomas Huth wrote: It's a common scenario to copy guest images from one host to another to run the guest on the other machine. This (of course) does not work with "secure exection" guests since they are encrypted with one certain ho

Re: [PATCH] hw/timer: fix systick trace message

Le 09/01/2024 à 19:45, Samuel Tardieu a écrit : Signed-off-by: Samuel Tardieu Fixes: ff68dacbc786 ("armv7m: Split systick out from NVIC") --- hw/timer/trace-events | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 3eccef838

Re: [PATCH v6 07/11] virtio-gpu: Handle resource blob commands

Le 21/12/2023 à 09:09, Akihiko Odaki a écrit : On 2023/12/19 16:53, Huang Rui wrote: From: Antonio Caggiano Support BLOB resources creation, mapping and unmapping by calling the new stable virglrenderer 0.10 interface. Only enabled when available and via the blob config. E.g. -device virtio

Re: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv

Markus Armbruster writes: > Peter Xu writes: > >> On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote: >>> Hi Fabiano, >>> >>> On 9/1/24 21:21, Fabiano Rosas wrote: >>> > Cédric Le Goater writes: >>> > >>> > > On 1/9/24 18:40, Fabiano Rosas wrote: >>> > > > Cédric Le Goater

Re: [PATCH] block/blklogwrites: Fix a bug when logging "write zeroes" operations.

Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben: > From: Ari Sundholm > > There is a bug in the blklogwrites driver pertaining to logging "write > zeroes" operations, causing log corruption. This can be easily observed > by setting detect-zeroes to something other than "off" for the driver.

Re: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv

Fabiano Rosas writes: > Markus Armbruster writes: > >> Peter Xu writes: >> >>> On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote: Hi Fabiano, On 9/1/24 21:21, Fabiano Rosas wrote: > Cédric Le Goater writes: > > > On 1/9/24 18:40, Fabiano Ros

[PATCH v2] target/s390x/kvm/pv: Provide some more useful information if decryption fails

It's a common scenario to copy guest images from one host to another to run the guest on the other machine. This (of course) does not work with "secure exection" guests since they are encrypted with one certain host key. However, if you still (accidentally) do it, you only get a very user-unfriendl

Re: [External] Re: [QEMU-devel][RFC PATCH 1/1] backends/hostmem: qapi/qom: Add an ObjectOption for memory-backend-* called HostMemType and its arg 'cxlram'

On Tue, 9 Jan 2024 15:55:46 -0800 Hao Xiang wrote: > On Tue, Jan 9, 2024 at 2:13 PM Gregory Price > wrote: > > > > On Tue, Jan 09, 2024 at 01:27:28PM -0800, Hao Xiang wrote: > > > On Tue, Jan 9, 2024 at 11:58 AM Gregory Price > > > wrote: > > > > > > > > If you drop this line: > > > > > >

Re: [PATCH] qga-win: Fix guest-get-fsinfo multi-disks collection

ping ! please review this patch : https://patchew.org/QEMU/20231227071540.4035803-1-peng...@smartx.com/ thanks On Fri, Jan 5, 2024 at 9:47 PM Philippe Mathieu-Daudé wrote: > On 27/12/23 08:15, peng...@smartx.com wrote: > > From: Peng Ji > > > > When a volume has more than one disk, all disks

[PATCH] Fixed '-serial none' usage breaks following '-serial ...' usage

Hello, I have faced an issue in using serial ports when I need to skip a couple of ports in the CLI. For example the ARM machine netduinoplus2 supports up to 7 UARTS. Following case works (the first UART is used to send data in the firmware): qemu-system-arm -machine netduinoplus2 -nographic -ser

Re: [PATCH v3 4/4] [NOT FOR MERGE] tests/qtest/migration: Adapt tests to use older QEMUs

Peter Xu writes: > On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote: >> Hm, it would be better to avoid the extra maintenance task at the start >> of every release, no? It also blocks us from doing n-2 even >> experimentally. > > See my other reply, on whether we can use "n-1" for mi

Re: [PATCH] block/blklogwrites: Fix a bug when logging "write zeroes" operations.

Hi, Kevin! On 1/10/24 15:39, Kevin Wolf wrote: Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben: From: Ari Sundholm There is a bug in the blklogwrites driver pertaining to logging "write zeroes" operations, causing log corruption. This can be easily observed by setting detect-zeroes to s

Re: [PATCH 00/10] docs/migration: Reorganize migration documentations

On 1/10/24 03:37, Peter Xu wrote: On Tue, Jan 09, 2024 at 02:21:26PM +0100, Cédric Le Goater wrote: A few things I'd like to mention alongside, because it's documentation relevant too, and I'd like to collect if there's any comment. I just mostly rewrote two wiki pages completely: https:

Goldfish TTY enhancement

Having recently written a driver for the Goldfish TTY for NetBSD, I found it a bit odd (and a little annoying) that the device has a PUT_CHAR register but not a GET_CHAR register, something particularly useful for early-console or in-kernel debugger use. As it stands, to get a single character

Re: [PATCH v2] target/s390x/kvm/pv: Provide some more useful information if decryption fails

On 10/1/24 15:29, Thomas Huth wrote: It's a common scenario to copy guest images from one host to another to run the guest on the other machine. This (of course) does not work with "secure exection" guests since they are encrypted with one certain "execution" host key. However, if you still (

Re: [RFC/PATCH v1 09/11] gunyah: CPU execution loop

Hi Srivatsa, On 9/1/24 10:00, Srivatsa Vaddagiri wrote: Complete the cpu execution loop. At this time, we recognize exits associated with only MMIO access. Future patches will add support for recognizing other exit reasons, such as PSCI calls made by guest. Signed-off-by: Srivatsa Vaddagiri --

Re: [RFC/PATCH v1 09/11] gunyah: CPU execution loop

Hi Srivatsa, On 9/1/24 10:00, Srivatsa Vaddagiri wrote: Complete the cpu execution loop. At this time, we recognize exits associated with only MMIO access. Future patches will add support for recognizing other exit reasons, such as PSCI calls made by guest. Signed-off-by: Srivatsa Vaddagiri --

Re: Goldfish TTY enhancement

Hi Jason, On 10/1/24 16:24, Jason Thorpe wrote: Having recently written a driver for the Goldfish TTY for NetBSD, I found it a bit odd (and a little annoying) that the device has a PUT_CHAR register but not a GET_CHAR register, something particularly useful for early-console or in-kernel debu

Re: [PATCH v9 00/11] virtio: cleanup vhost-user-generic and reduce c&p + vhost-user-input

On Wed, Jan 10, 2024 at 10:55:11AM +, Alex Bennée wrote: > Alex Bennée writes: > > > A lot of our vhost-user stubs are large chunks of boilerplate that do > > (mostly) the same thing. This series continues the cleanups by > > splitting the vhost-user-base and vhost-user-generic implementation

Re: [PULL 00/65] riscv-to-apply queue

ilable in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240110 > > for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21: > > target/riscv: Ensure mideleg is set

Re: [PULL 0/2] qemu-sparc queue 20240110

ilable in the Git repository at: > > https://github.com/mcayland/qemu.git tags/qemu-sparc-20240110 > > for you to fetch changes up to 995d8348eb3d8ddf24882ed384a5c50eaf3aeae9: > > util/fifo8: Introduce fifo8_peek_buf() (2024-01-10 06:58:50 +) > > --

[PATCH] target/riscv: Check for 'A' extension on all atomic instructions

Add requirement that 'A' is enabled for all atomic instructions that lack the check. This makes the 64-bit versions consistent with the 32-bit versions in the same file. Signed-off-by: Rob Bradford --- target/riscv/insn_trans/trans_rva.c.inc | 11 +++ 1 file changed, 11 insertions(+) di

Re: [PATCH 2/2] tests/tcg/s390x: Test LOAD ADDRESS EXTENDED

On 10/01/2024 00.22, Ilya Leoshkevich wrote: Add a small test to prevent regressions. Userspace runs in primary mode, so LAE should always set the access register to 0. Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/lae.c | 25 ++

Re: [PATCH] block/blklogwrites: Fix a bug when logging "write zeroes" operations.

Am 10.01.2024 um 16:21 hat Ari Sundholm geschrieben: > On 1/10/24 15:39, Kevin Wolf wrote: > > Am 09.01.2024 um 19:46 hat meg...@gmx.com geschrieben: > > > From: Ari Sundholm > > > > > > There is a bug in the blklogwrites driver pertaining to logging "write > > > zeroes" operations, causing log c

Re: [PATCH v2 1/4] hw/cxl: fix build error in cxl_type3_stubs.c

On Tue, Jan 09, 2024 at 05:40:26PM +, Jonathan Cameron wrote: > On Fri, 22 Dec 2023 18:00:48 +0900 > Hyeonggon Yoo <42.hye...@gmail.com> wrote: > > > Fix build errors in cxl_type3_stubs.c due to a the incorrect definition > > of the qmp_cxl_{add,release}_dynamic_capacity functions. > > > > Si

Re: [PATCH V1 1/3] migration: check mode in notifiers

On 1/10/2024 2:09 AM, Peter Xu wrote: > On Wed, Dec 13, 2023 at 10:11:31AM -0800, Steve Sistare wrote: >> The existing notifiers should only apply to normal mode. >> >> No functional change. > > Instead of adding such check in every notifier, why not make CPR a separate > list of notifiers? Just

Re: [PATCH V1 2/3] migration: notifier error reporting

On 1/10/2024 2:18 AM, Peter Xu wrote: > On Wed, Dec 13, 2023 at 10:11:32AM -0800, Steve Sistare wrote: >> After calling notifiers, check if an error has been reported via >> migrate_set_error, and halt the migration. >> >> None of the notifiers call migrate_set_error at this time, so no >> function

Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension

On 1/9/24 14:07, Rob Bradford wrote: Add the infrastructure for the 'B' extension which is the union of the Zba, Zbb and Zbs instructions. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 1 + 3 files ch

Re: [PATCH 2/3] target/riscv: Add step to validate 'B' extension

On 1/9/24 14:07, Rob Bradford wrote: If the B extension is enabled warn if the user has disabled any of the required extensions that are part of the 'B' extension. Conversely enable the extensions that make up the 'B' extension if it is enabled. Signed-off-by: Rob Bradford --- This patch d

Re: [PULL 2/7] s390x: do a subsystem reset before the unprotect on reboot

On 9/12/23 13:41, Thomas Huth wrote: From: Janosch Frank Bound APQNs have to be reset before tearing down the secure config via s390_machine_unprotect(). Otherwise the Ultravisor will return a error code. So let's do a subsystem_reset() which includes a AP reset before the unprotect call. We'l

Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

On 1/9/24 14:07, Rob Bradford wrote: Signed-off-by: Rob Bradford --- target/riscv/tcg/tcg-cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f10871d352..9705daec93 100644 --- a/target/riscv/tcg/tcg-cpu.c

Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type

Rob, Given that you'll need to resend the patches due to the conflict in patch 2, I think it would be nice to mention in this commit message that we're ok with enabling RVB in the 'max' CPU, even though RVB per se is experimental, because it's just an alias for extensions that the CPU already use

Re: [PATCH] target/riscv: Check for 'A' extension on all atomic instructions

On 1/10/24 13:39, Rob Bradford wrote: Add requirement that 'A' is enabled for all atomic instructions that lack the check. This makes the 64-bit versions consistent with the 32-bit versions in the same file. Signed-off-by: Rob Bradford --- Reviewed-by: Daniel Henrique Barboza target/r

Re: [PATCH 0/2] Export debug triggers as an extension

Himanshu, We spoke offline but let's make everyone aware: - 'sdtrig' should be marked with 'x-' and be an experimental extension since the spec isn't yet frozen; - Alvin sent a patch to the ML adding the 'mcontext' CSR for 'sdtrig' some time ago: "[PATCH v2] target/riscv: Implement optional CS

Re: [PATCH 11/19] qapi/schema: fix QAPISchemaArrayType.check's call to resolve_type

On Thu, Nov 23, 2023, 8:03 AM Markus Armbruster wrote: > John Snow writes: > > > On Wed, Nov 22, 2023 at 7:59 AM Markus Armbruster > wrote: > >> > >> John Snow writes: > >> > >> > There's more conditionals in here than we can reasonably pack into a > >> > terse little statement, so break it ap

[PATCH v3 00/14] hw/arm: Prefer arm_feature() over object_property_find()

Since v2 [2]: - Dropped "Simplify checking A64_MTE bit in FEATURE_ID register" - Correct object_property_get_bool() uses - Update ARM_FEATURE_AARCH64 && aa64_mte Since RFC [1]: - Split one patch per feature - Addressed Peter's review comments [1] https://lore.kernel.org/qemu-devel/20231214171447.

[PATCH v3 05/14] hw/arm: Prefer arm_feature(M_SECURITY) over object_property_find()

Both "idau" and "init-svtor" properties are added to ARMCPU when the ARM_FEATURE_M_SECURITY feature is available. Rather than checking whether the QOM properties are present, directly check the feature. Since we are sure the "init-svtor" is present, the object_property_set_uint() can't fail. Inste

[PATCH v3 01/14] hw/arm/armv7m: Introduce cpudev variable in armv7m_realize()

We are going to cast s->cpu as DeviceState multiple times. Add a local 'cpudev' variable to simplify code review, having a single DEVICE(s->cpu) conversion. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/arm

[PATCH v3 06/14] hw/arm: Prefer arm_feature(THUMB_DSP) over object_property_find(dsp)

The "dsp" property is added to ARMCPU when the ARM_FEATURE_THUMB_DSP feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 in

[PATCH v3 04/14] hw/arm/armv7m: Always set 'init-nsvtor' property for Cortex-M CPUs

All CPUs implementing ARM_FEATURE_M have the 'init-nsvtor' property. Since setting the property can not fail, replace object_property_set_uint(..., "init-nsvtor", ..., &error_abort); by: qdev_prop_set_uint32(..., "init-nsvtor", ...). which is a one-to-one replacement. Suggested-by: Peter

[PATCH v3 09/14] hw/arm: Prefer arm_feature(EL2) over object_property_find(has_el2)

The "has_el2" property is added to ARMCPU when the ARM_FEATURE_EL2 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 3 ++- hw/arm/virt.c

[PATCH v3 07/14] hw/arm: Prefer arm_feature(V7) over object_property_find(pmsav7-dregion)

The "pmsav7-dregion" property is added to ARMCPU when the ARM_FEATURE_V7 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 4 ++-- 1 file changed

[PATCH v3 08/14] hw/arm: Prefer arm_feature(EL3) over object_property_find(has_el3)

The "has_el3" property is added to ARMCPU when the ARM_FEATURE_EL3 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 4 ++-- hw/arm/integr

[PATCH v3 11/14] hw/arm: Prefer arm_feature(PMU) over object_property_find(pmu)

The "pmu" property is added to ARMCPU when the ARM_FEATURE_PMU feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(

[PATCH v3 10/14] hw/arm: Prefer arm_feature(CBAR*) over object_property_find(reset-cbar)

The "reset-cbar" property is added to ARMCPU when the ARM_FEATURE_CBAR[_RO] features are available. Rather than checking whether the QOM property is present, directly check the features. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 3 ++- hw/arm/

[PATCH v3 13/14] hw/arm: Prefer arm_feature(AARCH64) over object_property_find(aarch64)

The "aarch64" property is added to ARMCPU when the ARM_FEATURE_AARCH64 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 +- 1 file changed, 1 in

[PATCH v3 02/14] hw/arm/armv7m: Ensure requested CPU type implements ARM_FEATURE_M

ARMV7M container can only accept M-profile CPU types. Check requested type is valid once to allow further simplifications. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7

[PATCH v3 12/14] hw/arm: Prefer arm_feature(GENERIC_TMR) over 'kvm-no-adjvtime' property

First, the "kvm-no-adjvtime" and "kvm-steal-time" are only available when KVM is available, so guard this block within a 'kvm_enabled()' check. Since the "kvm-steal-time" property is always available under KVM, directly set it. Then, the "kvm-no-adjvtime" property is added to ARMCPU when the ARM_F

[PATCH v3 03/14] hw/arm/armv7m: Move code setting 'start-powered-off' property around

Reorganize a bit by first setting properties which are not dependent of CPU features (and can not fail). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8900730e53..b752049add 10

[PATCH v3 14/14] hw/arm: Prefer cpu_isar_feature(aa64_mte) over property_find(tag-memory)

The "tag-memory" property is added to ARMCPU when the A64_MTE bit is set in the feature ID register. Rather than checking whether the QOM property is present, directly check the feature bit. Since when ARM_FEATURE_AARCH64 is disabled the isar_aa64_mte register is invalid, also check for it (see th

Re: [PATCH 12/19] qapi/schema: split "checked" field into "checking" and "checked"

On Wed, Nov 22, 2023, 9:02 AM Markus Armbruster wrote: > John Snow writes: > > > Differentiate between "actively in the process of checking" and > > "checking has completed". This allows us to clean up the types of some > > internal fields such as QAPISchemaObjectType's members field which > > c

Re: [PULL 2/7] s390x: do a subsystem reset before the unprotect on reboot

On 1/10/24 1:30 PM, Cédric Le Goater wrote: > On 9/12/23 13:41, Thomas Huth wrote: >> From: Janosch Frank >> >> Bound APQNs have to be reset before tearing down the secure config via >> s390_machine_unprotect(). Otherwise the Ultravisor will return a error >> code. >> >> So let's do a subsystem_re

[PATCH 2/4] hw/i2c/smbus_slave: Add object path on error prints

The current logging doesn't tell us which specific smbus device is an error state. Signed-off-by: Joe Komlodi --- hw/i2c/smbus_slave.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index 1300c9ec72..e24a1ef472 100644 --- a

[PATCH 0/4] hw/i2c: smbus: Reset fixes

Hi all, This series adds some resets for SMBus and for the I2C core. Along with it, we make SMBus slave error printing a little more helpful. These reset issues were very infrequent, they would maybe occur in 1 out of hundreds of resets in our testing, but the way they happen is pretty straightfo

[PATCH 1/4] hw/i2c: core: Add reset

It's possible for a reset to come in the middle of a transaction, which causes the bus to be in an old state when a new transaction comes in. Signed-off-by: Joe Komlodi --- hw/i2c/core.c| 30 +- include/hw/i2c/i2c.h | 6 +- 2 files changed, 30 insertions(

[PATCH 3/4] hw/i2c: smbus_slave: Reset state on reset

If a reset comes while the SMBus device is not in its idle state, it's possible for it to get confused on valid transactions post-reset. Signed-off-by: Joe Komlodi --- hw/i2c/smbus_slave.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c in

[PATCH 4/4] hw/i2c: smbus: mux: Reset SMBusDevice state on reset

When a reset happens, both the SMBusDevice and PCA954x class do their variable resetting on an enter reset. Because of this, only the PCA954x has its reset called, which can leave the SMBusDevice in a bad state if it was in the middle of a transaction. To fix this we add parent reset functions for

Re: [PATCH 0/4] hw/i2c: smbus: Reset fixes

+cminyard Accidentally typed Corey's email address wrong in the initial send, oops. On Wed, Jan 10, 2024 at 1:26 PM Joe Komlodi wrote: > > Hi all, > > This series adds some resets for SMBus and for the I2C core. Along with > it, we make SMBus slave error printing a little more helpful. > > The

[PULL 3/4] tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-sta...@nongnu.org Fixes: 526cd4ec01f ("tcg

[PULL 4/4] util: fix build with musl libc on ppc64le

From: Natanael Copa Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers instead of the GNU specific PPC_FEATURE2_HAS_ISEL and PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc. Cc: qemu-sta...@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861 Sig

[PULL 0/4] tcg patch queue

The following changes since commit 34eac35f893664eb8545b98142e23d9954722766: Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging (2024-01-10 11:41:56 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tag

[PULL 2/4] tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates

From: Paolo Bonzini In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can operate on a low-byte register and shorten the output by two or three bytes (two if a prefix byte is needed for REX.B). Signed-off-by: Paolo Bonzini Message-Id: <20231228120524.70239-1-pbonz...@re

[PULL 1/4] tcg/i386: convert add/sub of 128 to sub/add of -128

From: Paolo Bonzini Extend the existing conditional that generates INC/DEC, to also swap an ADD for a SUB and vice versa when the immediate is 128. This facilitates using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz. Signed-off-by: Paolo Bonzini Message-Id: <20231228120514.70205-1-pbonz...@redhat.

Re: [PATCH v3 07/33] linux-user/arm: Remove qemu_host_page_size from init_guest_commpage

On 1/8/24 20:38, Pierrick Bouvier wrote: On 1/2/24 05:57, Richard Henderson wrote: Use qemu_real_host_page_size. If the commpage is not within reserved_va, use MAP_FIXED_NOREPLACE. Signed-off-by: Richard Henderson ---   linux-user/elfload.c | 13 -   1 file changed, 8 insertions(+),

[PATCH v3 04/38] tcg/optimize: Split out do_constant_folding_cond1

Handle modifications to the arguments and condition in a single place. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 57 -- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/tcg/optimize.c

[PATCH v3 00/38] tcg: Introduce TCG_COND_TST{EQ,NE}

Expose a pair of comparison operators that map to the "test" comparison that is available on many architectures. Changes for v3: * Make support for TCG_COND_TST* optional (paolo) * Drop riscv, loongarch64 and (unposted) mips backend changes. * Incorporate Paolo's tcg/i386 TEST improvements

[PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported

After having performed other simplifications, lower any remaining test comparisons with AND. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 2 ++ tcg/optimize.c | 60 +++--- tcg/tcg.c | 2 +- 3 files changed, 55 insertions(+), 9 d

[PATCH v3 01/38] tcg: Introduce TCG_COND_TST{EQ,NE}

Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 2 ++ include/tcg/tcg-cond.h | 74 ++ tcg/tcg.c

[PATCH v3 03/38] tcg/optimize: Split out arg_is_const_val

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 38 +++--- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f2d01654c5..73019b9996 100644 --- a/tcg/optimize.c +++ b/tcg/

[PATCH v3 06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE}

Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimi

[PATCH v3 13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..b96633dde1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -506,6 +50

[PATCH v3 09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}

Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247.83234-2-phi...@linaro.org> --- target/alpha/translate.c | 20 ++-- 1 fil

[PATCH v3 05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2

Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/optimize.c | 107 ++--- 1 file changed, 57 insertions(+), 50 deleti

[PATCH v3 16/38] tcg: Add TCGConst argument to tcg_target_const_match

Fill the new argument from any condition within the opcode. Not yet used within any backend. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c| 34 ++-- tcg/aarch64/tcg-target.c.inc | 3 ++- tcg/arm/tcg-ta

[PATCH v3 02/38] tcg: Introduce TCG_TARGET_HAS_tst

Define as 0 for all tcg backends. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h| 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h| 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg

[PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond

Signed-off-by: Richard Henderson --- target/m68k/translate.c | 74 ++--- 1 file changed, 33 insertions(+), 41 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..f30b92f2d4 100644 --- a/target/m68k/translate.c +++ b/ta

[PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel

Using cr0 means we could choose to use rc=1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 68 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/tc

[PATCH v3 10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S}

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 49e6a7b62d..c7daf46de7 100644 --- a/target/alpha/translate.c +++

[PATCH v3 11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 49 +++- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c7daf46de7..c68c2bcd21 100644

[PATCH v3 32/38] tcg/ppc: Tidy up tcg_target_const_match

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 27 --- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b9323baa86..26e0bc31d7 100644 --- a/tcg/pp

[PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-12-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 2/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108145244.72421-2-phi...@linaro.org> --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.in

[PATCH v3 14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}

These are all test-and-compare type instructions. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 62ab2be8b1..ae4e7b27ec 100

[PATCH v3 22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov

Hoist the tcg_cond_to_jcc index outside the function. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc ind

[PATCH v3 30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc

Rename the current tcg_out_bc function to tcg_out_bc_lab, and create a new function that takes an integer displacement + link. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 28 +--- 1 file changed, 17 insertions(+), 1

[PATCH v3 18/38] tcg/aarch64: Generate TBZ, TBNZ

Test the sign bit for LT/GE vs 0, and TSTNE/EQ vs a power of 2. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 100 --- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc

[PATCH v3 33/38] tcg/ppc: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. We can't yet remove the fallback to load constants into a scratch because of tcg_out_cmp2, but that path should not be as frequent. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 5 ++-- tcg/ppc/tcg-target-con-str.

[PATCH v3 08/38] target/alpha: Pass immediate value to gen_bcond_internal()

Simplify gen_bcond() by passing an immediate value. Signed-off-by: Richard Henderson Message-Id: <20231028194522.245170-33-richard.hender...@linaro.org> [PMD: Split from bigger patch, part 1/2] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231108205247.83234-1-phi...@linaro.org> --- targ

[PATCH v3 36/38] tcg/s390x: Add TCG_CT_CONST_CMP

Better constraint for tcg_out_cmp, based on the comparison. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 6 +-- tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.c.inc | 72 +- 3 files changed, 58 insertions(+), 21 deletions

[PATCH v3 26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits

From: Paolo Bonzini Just like when testing against the sign bits, TEST r,r can be used when the immediate is 0xff, 0xff00, 0x, 0x. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 17 + 1

[PATCH v3 17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 5 +-- tcg/aarch64/tcg-target-con-str.h | 1 + tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.c.inc | 56 ++-- 4 files changed, 44 insertions(+), 20 deletions(-) diff --git

[PATCH v3 15/38] target/s390x: Improve general case of disas_jcc

Avoid code duplication by handling 7 of the 14 cases by inverting the test for the other 7 cases. Use TCG_COND_TSTNE for cc in {1,3}. Use (cc - 1) <= 1 for cc in {1,2}. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 82 +--- 1 file changed, 3

[PATCH v3 35/38] tcg/s390x: Split constraint A into J+U

Signed 33-bit == signed 32-bit + unsigned 32-bit. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 8 tcg/s390x/tcg-target-con-str.h | 2 +- tcg/s390x/tcg-target.c.inc | 36 +- 3 files changed, 23 insertions(+), 23 deletions(-)

[PATCH v3 34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.c.inc | 122 --- 2 files changed, 115 insertions(+), 9 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 60ce49e672..04a7aba4d3 100644 --- a/tc

[PATCH v3 37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE}

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 139 + 2 files changed, 97 insertions(+), 44 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 53bed8c8d2..ae448c3a3a 100644 --

[PATCH v3 27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond

Use a non-zero value here (an illegal encoding) as a better condition than is_unsigned_cond for when MOVR/BPR is usable. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++--- 1 file changed, 14 insertions(+), 11 del

[PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX

... and the inverse, CBZ for TSTEQ. Suggested-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 8 1 file changed, 8 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 55225313ad..0c98c48f68 100644 --- a/tcg

[PATCH v3 28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e16b25e309..10fb8a1a0d 100644 --- a/

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