RE: [RESEND RFC v1 2/2] hw/riscv/virt-acpi-build.c: Generate SPCR table

> -Original Message- > From: Daniel Henrique Barboza > Sent: Friday, January 5, 2024 8:27 PM > To: JeeHeng Sia ; qemu-...@nongnu.org; > qemu-devel@nongnu.org; qemu-ri...@nongnu.org > Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com; > peter.mayd...@linaro.org; shannon.zha.

RE: [RESEND RFC v1 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location

> -Original Message- > From: Daniel Henrique Barboza > Sent: Friday, January 5, 2024 8:19 PM > To: JeeHeng Sia ; qemu-...@nongnu.org; > qemu-devel@nongnu.org; qemu-ri...@nongnu.org > Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com; > peter.mayd...@linaro.org; shannon.zha.

RE: [RESEND RFC v1 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location

> -Original Message- > From: Sunil V L > Sent: Monday, January 8, 2024 7:35 PM > To: Daniel Henrique Barboza > Cc: JeeHeng Sia ; qemu-...@nongnu.org; > qemu-devel@nongnu.org; qemu-ri...@nongnu.org; > m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com; > peter.mayd...@linaro.or

Re: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv

Peter Xu writes: > On Wed, Jan 10, 2024 at 07:03:06AM +0100, Markus Armbruster wrote: >> Peter Xu writes: >> >> > On Tue, Jan 09, 2024 at 10:22:31PM +0100, Philippe Mathieu-Daudé wrote: >> >> Hi Fabiano, >> >> >> >> On 9/1/24 21:21, Fabiano Rosas wrote: [...] >> >> > No one wants >> >> > to

Re: [RFC/PATCH v1 07/11] gunyah: Specify device-tree location

* Philippe Mathieu-Daud? [2024-01-09 14:31:03]: > Hi Srivatsa, > > On 9/1/24 10:00, Srivatsa Vaddagiri wrote: > > Specify the location of device-tree and its size, as Gunyah requires the > > device-tree to be parsed before VM can begin its execution. > > > > Signed-off-by: Srivatsa Vaddagiri >

Re: [PATCH 13/19] qapi/schema: fix typing for QAPISchemaVariants.tag_member

On Wed, Jan 10, 2024 at 2:53 AM Markus Armbruster wrote: > > John Snow writes: > > > On Wed, Nov 22, 2023 at 11:02 AM John Snow wrote: > >> > >> On Wed, Nov 22, 2023 at 9:05 AM Markus Armbruster > >> wrote: > >> > > >> > John Snow writes: > >> > > >> > > There are two related changes here: >

Re: [RFC/PATCH v1 07/11] gunyah: Specify device-tree location

* Philippe Mathieu-Daud? [2024-01-09 14:36:12]: > > +#include "qemu/osdep.h" > > +#include "qemu/error-report.h" > > +#include "sysemu/gunyah.h" > > +#include "sysemu/gunyah_int.h" > > +#include "linux-headers/linux/gunyah.h" > I'm getting on macOS: > > In file included from ../../target/arm/gun

Re: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv

On Wed, Jan 10, 2024 at 09:09:51AM +0100, Markus Armbruster wrote: > If an object has state that needs to be migrated only sometimes, and > that part of the state is large enough to bother, we can put it in an > optional subsection, can't we? > > Destination: if present, take it. If absent, initi

Re: [RFC PATCH v3 01/30] io: add and implement QIO_CHANNEL_FEATURE_SEEKABLE for channel file

On Mon, Nov 27, 2023 at 05:25:43PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > Add a generic QIOChannel feature SEEKABLE which would be used by the > qemu_file* apis. For the time being this will be only implemented for > file channels. > > Signed-off-by: Nikolay Borisov > Signed-of

Re: [PATCH v6 07/11] virtio-gpu: Handle resource blob commands

Le 09/01/2024 à 17:50, Pierre-Eric Pelloux-Prayer a écrit : Le 19/12/2023 à 08:53, Huang Rui a écrit : From: Antonio Caggiano Support BLOB resources creation, mapping and unmapping by calling the new stable virglrenderer 0.10 interface. Only enabled when available and via the blob config.

[PULL 00/65] riscv-to-apply queue

v-to-apply-20240110 for you to fetch changes up to 71b76da33a1558bcd59100188f5753737ef6fa21: target/riscv: Ensure mideleg is set correctly on reset (2024-01-10 18:47:47 +1000) RISC-V PR for 9.0 * Make vector whole-register move (v

[PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV

From: LIU Zhiwei If CPU does not implement the Vector extension, it usually means mstatus vs hardwire to zero. So we should not allow write a non-zero value to this field. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20231215023313.1708-1-zhiwei_...@linux.alibaba.com> S

[PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT

From: Sunil V L Add IMSIC structure in MADT when IMSIC is configured. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-7-suni...@ventanamicro.com> Signed-off-by:

[PULL 20/65] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT

From: Sunil V L MMU type information is available via MMU node in RHCT. Add this node in RHCT. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-10-suni...@ventan

[PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32

From: Daniel Henrique Barboza KVM_REG_RISCV_FP_F regs have u32 size according to the API, but by using kvm_riscv_reg_id() in RISCV_FP_F_REG() we're returning u64 sizes when running with TARGET_RISCV64. The most likely reason why no one noticed this is because we're not implementing kvm_cpu_synchr

[PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64

From: Daniel Henrique Barboza KVM_REG_RISCV_FP_D regs are always u64 size. Using kvm_riscv_reg_id() in RISCV_FP_D_REG() ends up encoding the wrong size if we're running with TARGET_RISCV32. Create a new helper that returns a KVM ID with u64 size and use it with RISCV_FP_D_REG(). Reported-by: An

[PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew

From: Max Chou The RISC-V v spec 16.6 section says that the whole vector register move instructions operate as if EEW=SEW. So it should depends on the vsew field of vtype register. Signed-off-by: Max Chou Acked-by: Richard Henderson Message-ID: <20231129170400.21251-3-max.c...@sifive.com> Sign

[PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT

From: Sunil V L With common function to add virtio in DSDT created now, update microvm code also to use it instead of duplicate code. Suggested-by: Andrew Jones Signed-off-by: Sunil V L Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-4-suni...@venta

[PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()

From: Daniel Henrique Barboza kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32 size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64. Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll be in line with the existing kvm_riscv_reg_id_() h

[PULL 23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices

From: Sunil V L Add basic IO controllers and devices like PCI, VirtIO and UART in the ACPI namespace. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-13-suni...@ventanamicro.com> Signed-o

[PULL 22/65] hw/riscv/virt: Update GPEX MMIO related properties

From: Sunil V L Update the GPEX host bridge properties related to MMIO ranges with values set for the virt machine. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-12-suni...@ventanamicro.com>

[PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location

From: Sunil V L RISC-V also needs to create the virtio in DSDT in the same way as ARM. So, instead of duplicating the code, move this function to the device specific file which is common across architectures. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L Reviewed-by: Alistair Francis R

[PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT

From: Sunil V L Add PLIC structures for each socket in the MADT when system is configured with PLIC as the external interrupt controller. Signed-off-by: Haibo Xu Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Acked-by: Mich

[PULL 26/65] target/riscv: Add support for Zacas extension

From: Weiwei Li Add support for amocas.w/d/q instructions which are part of the ratified Zacas extension: https://github.com/riscv/riscv-zacas Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Message-ID: <20231207153842.32

[PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits

From: Daniel Henrique Barboza RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions

[PULL 19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT

From: Sunil V L When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the block size for those extensions need to be communicated via CMO node in RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barbo

[PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public

From: Sunil V L Some macros and static function related to IMSIC are defined in virt.c. They are required in virt-acpi-build.c. So, make them public. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Acked-by: Michael S. Tsi

[PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC

From: Sunil V L Update the RINTC structure in MADT with AIA related fields. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Andrew Jones Acked-by: Michael S. Tsirkin Message-ID: <20231218150247.466427-6-suni...@ventanamicro.com> Signed-o

[PULL 09/65] target/riscv/kvm: change timer regs size to u64

From: Daniel Henrique Barboza KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at this moment we'll return u32 regs if we're running a RISCV32 target. Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it. Reported-by: Andrew Jones Signed-off-by: Daniel Henr

[PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG()

From: Daniel Henrique Barboza Create a RISCV_CONFIG_REG() macro, similar to what other regs use, to hide away some of the boilerplate. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20231208183835.2411523-5-dbarb...@ventanamicro.com> Signed-off-by: Alistair Franc

[PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check

From: LIU Zhiwei According to the specification, the th.dcache.cvall1 can be executed under all priviledges. The specification about xtheadcmo located in, https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PULL 41/65] target/riscv/tcg: handle profile MISA bits

From: Daniel Henrique Barboza The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_ma

[PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier

From: Daniel Henrique Barboza Profiles will need to validate satp_mode during their own finalize methods. This will occur inside riscv_tcg_cpu_finalize_features() for TCG. Given that satp_mode does not have any pre-req from the accelerator finalize() method, it's safe to finalize it earlier. Sig

[PULL 01/65] target/riscv: Add vill check for whole vector register move instructions

From: Max Chou The ratified version of RISC-V V spec section 16.6 says that `The instructions operate as if EEW=SEW`. So the whole vector register move instructions depend on the vtype register that means the whole vector register move instructions should raise an illegal-instruction exception w

[PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32

From: Ivan Klokov The Sv32 page-based virtual-memory scheme described in RISCV privileged spec Section 5.3 supports 34-bit physical addresses for RV32, so the PMP scheme must support addresses wider than XLEN for RV32. However, PMP address register format is still 32 bit wide. Signed-off-by: Iva

[PULL 51/65] target/riscv: add satp_mode profile support

From: Daniel Henrique Barboza 'satp_mode' is a requirement for supervisor profiles like RVA22S64. User-mode/application profiles like RVA22U64 doesn't care. Add 'satp_mode' to the profile description. If a profile requires it, set it during cpu_set_profile(). We'll also check it during finalize(

[PULL 36/65] target/riscv: add rva22u64 profile definition

From: Daniel Henrique Barboza The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient t

[PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions

From: Daniel Henrique Barboza We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver = 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll e

[PULL 33/65] target/riscv: add zicbop extension flag

From: Daniel Henrique Barboza QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block

[PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion

From: Daniel Henrique Barboza Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Ano

[PULL 52/65] target/riscv: add 'parent' in profile description

From: Daniel Henrique Barboza Certain S-mode profiles, like RVA22S64 and RVA23S64, mandate all the mandatory extensions of their respective U-mode profiles. RVA22S64 includes all mandatory extensions of RVA22U64, and the same happens with RVA23 profiles. Add a 'parent' field to allow profiles to

[PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset

From: Alistair Francis Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is enabled. We currently only set them on accesses to mideleg, but they aren't correctly set on reset. Let's ensure they are always the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issue

[PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4

From: Bin Meng Upgrade OpenSBI from v1.3.1 to v1.4 and the pre-built bios images. The v1.4 release includes the following commits: 1a398d9 lib: sbi: Add Zicntr as a HART ISA extension 669089c lib: sbi: Add Zihpm as a HART ISA extension 72b9c8f lib: sbi: Alphabetically sort HART ISA extensions 5

[PULL 48/65] target/riscv: add priv ver restriction to profiles

From: Daniel Henrique Barboza Some profiles, like RVA22S64, has a priv_spec requirement. Make this requirement explicit for all profiles. We'll validate this requirement finalize() time and, in case the user chooses an incompatible priv_spec while activating a profile, a warning will be shown.

[PULL 42/65] target/riscv/tcg: add hash table insert helpers

From: Daniel Henrique Barboza Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-15-d

[PULL 47/65] target/riscv: implement svade

From: Daniel Henrique Barboza 'svade' is a RVA22S64 profile requirement, a profile we're going to add shortly. It is a named feature (i.e. not a formal extension, not defined in riscv,isa DT at this moment) defined in [1] as: "Page-fault exceptions are raised when a page is accessed when A bit i

[PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs

From: Daniel Henrique Barboza Add support for RVV and Vector CSR KVM regs vstart, vl and vtype. Support for vregs[] requires KVM side changes and an extra reg (vlenb) and will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20231218204321.7575

[PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

From: Daniel Henrique Barboza Expose all profile flags for all CPUs when executing query-cpu-model-expansion. This will allow callers to quickly determine if a certain profile is implemented by a given CPU. This includes vendor CPUs - the fact that they don't have profile user flags doesn't mean

[PULL 56/65] linux-headers: Update to Linux v6.7-rc5

From: Daniel Henrique Barboza We'll add a new RISC-V linux-header file, but first let's update all headers. Headers for 'asm-loongarch' were added in this update. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20231218204321.75757-2-dbarb...@ventanamicro.com> S

[PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()

From: Daniel Henrique Barboza Linux RISC-V vector documentation (Document/arch/riscv/vector.rst) mandates a prctl() in order to allow an userspace thread to use the Vector extension from the host. This is something to be done in realize() time, after init(), when we already decided whether we're

[PULL 32/65] target/riscv: add rv64i CPU

From: Daniel Henrique Barboza We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to de

[PULL 64/65] target/riscv: Don't adjust vscause for exceptions

From: Alistair Francis We have been incorrectly adjusting both the interrupt and exception cause when using the hypervisor extension and trapping to VS-mode. This patch changes the conditional to ensure we only adjust the cause for interrupts and not exceptions. Resolves: https://gitlab.com/qemu

[PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU

From: Daniel Henrique Barboza We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by

[PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC

From: Yong-Xuan Wang The interrupts-extended property of PLIC only has 2 * hart number fields when KVM enabled, copy 4 * hart number fields to fdt will expose some uninitialized value. In this patch, I also refactor the code about the setting of interrupts-extended property of PLIC for improved

[PULL 21/65] hw/pci-host/gpex: Define properties for MMIO ranges

From: Sunil V L ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of making these values machine specific, create properties for the GPEX host bridge with default value 0. During initialization, the firmw

[PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions

From: Rob Bradford Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20231207153842.32401-3-rbradf...@rivosinc.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 9 + 1 file changed, 9 insertions(+) diff --git a/disas/r

[PULL 57/65] linux-headers: riscv: add ptrace.h

From: Daniel Henrique Barboza KVM vector support for RISC-V requires the linux-header ptrace.h. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-ID: <20231218204321.75757-3-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- linux-headers/asm-riscv/ptrace.

[PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit()

From: Daniel Henrique Barboza Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit. The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check the first CPU of a given hart array, not any given CPU. Create a helper to retrieve the info for any given CPU, not the fir

[PULL 63/65] target/riscv: Assert that the CSR numbers will be correct

From: Alistair Francis The CSRs will always be between either CSR_MHPMCOUNTER3 and CSR_MHPMCOUNTER31 or CSR_MHPMCOUNTER3H and CSR_MHPMCOUNTER31H. So although ctr_index can't be negative, Coverity doesn't know this and it isn't obvious to human readers either. Let's add an assert to ensure that C

[PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit()

From: Daniel Henrique Barboza We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Franc

[PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket

From: Yong-Xuan Wang The emulated AIA within the Linux kernel restores the HART index of the IMSICs according to the configured AIA settings. During this process, the group setting is used only when the machine partitions harts into groups. It's unnecessary to set the group configuration if the m

[PULL 06/65] target/riscv/cpu.c: fix machine IDs getters

From: Daniel Henrique Barboza mvendorid is an uint32 property, mimpid/marchid are uint64 properties. But their getters are returning bools. The reason this went under the radar for this long is because we have no code using the getters. The problem can be seem via the 'qom-get' API though. Launc

[PULL 44/65] target/riscv/tcg: validate profiles during finalize

From: Daniel Henrique Barboza Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensi

[PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions

From: Bin Meng Currently, the documentation outlines the process for building the S-mode U-Boot image using `make menuconfig` and manual actions within the menuconfig UI. However, this approach is fragile due to Kconfig options potentially changing across different releases. For example, CONFIG_O

[PULL 53/65] target/riscv: add RVA22S64 profile

From: Daniel Henrique Barboza The RVA22S64 profile consists of the following: - all mandatory extensions of RVA22U64; - priv spec v1.12.0; - satp mode sv39; - Ssccptr, a cache related named feature that we're assuming always enable since we don't implement a cache; - Other named features alrea

[PULL 34/65] target/riscv/tcg: add 'zic64b' support

From: Daniel Henrique Barboza zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications

Re: [RFC PATCH v3 03/30] io: implement io_pwritev/preadv for QIOChannelFile

On Mon, Nov 27, 2023 at 05:25:45PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > The upcoming 'fixed-ram' feature will require qemu to write data to > (and restore from) specific offsets of the migration file. > > Add a minimal implementation of pwritev/preadv and expose them via the >

[PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location

From: Sunil V L RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid code duplication by moving the code in arm and riscv to a device specific file. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis R

[PULL 54/65] target/riscv: add rva22s64 cpu

From: Daniel Henrique Barboza Add a new profile CPU 'rva22s64' to work as an alias of -cpu rv64i,rva22s64 Like the existing rva22u64 CPU already does with the RVA22U64 profile. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <202312

Re: [RFC PATCH v3 04/30] io: fsync before closing a file channel

On Mon, Nov 27, 2023 at 05:25:46PM -0300, Fabiano Rosas wrote: > Make sure the data is flushed to disk before closing file > channels. This will ensure data is on disk at the end of a migration > to file. > > Signed-off-by: Fabiano Rosas > --- > io/channel-file.c | 5 + > 1 file changed, 5 i

[PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0

From: Ivan Klokov This patch changes behavior on writing RW=01 to pmpcfg with MML=0. RWX filed is form of collective WARL with the combination of pmpcfg.RW=01 remains reserved for future standard use. According to definition of WARL writing the CSR has no other side effect. But current implement

[PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT

From: Sunil V L Add APLIC structures for each socket in the MADT when system is configured with APLIC as the external wired interrupt controller. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin M

[PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable

From: Daniel Henrique Barboza KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support

[PULL 38/65] target/riscv/tcg: add user flag for profile support

From: Daniel Henrique Barboza The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first pro

Re: [RFC PATCH v3 02/30] io: Add generic pwritev/preadv interface

On Mon, Nov 27, 2023 at 05:25:44PM -0300, Fabiano Rosas wrote: > From: Nikolay Borisov > > Introduce basic pwritev/preadv support in the generic channel layer. > Specific implementation will follow for the file channel as this is > required in order to support migration streams with fixed locatio

Re: [PATCH 1/2] target/s390x: Fix LAE setting a wrong access register

On 10.01.24 00:22, Ilya Leoshkevich wrote: LAE should set the access register corresponding to the first operand, instead, it always modifies access register 1. Co-developed-by: Ido Plat Cc: qemu-sta...@nongnu.org Fixes: a1c7610a6879 ("target-s390x: implement LAY and LAEY instructions") Signed-

[PULL 46/65] target/riscv: add 'rva22u64' CPU

From: Daniel Henrique Barboza This CPU was suggested by Alistair [1] and others during the profile design discussions. It consists of the bare 'rv64i' CPU with rva22u64 enabled by default, like an alias of '-cpu rv64i,rva22u64=true'. Users now have an even easier way of consuming this user-mode

[PULL 39/65] target/riscv/tcg: add MISA user options hash

From: Daniel Henrique Barboza We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne

[PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks

From: Daniel Henrique Barboza Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's h

[PULL 28/65] docs/system/riscv: document acpi parameter of virt machine

From: Heinrich Schuchardt Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI table generation. Add it to the documentation. Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI") Signed-off-by: Heinrich Schuchardt Reviewed-by: Daniel Henrique Barboza Reviewed-b

Re: [PATCH v4 8/9] target/loongarch: Implement set vcpu intr for kvm

Hi Tianrui, On 5/1/24 08:58, Tianrui Zhao wrote: Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao Signed-off-by: xianglai li Reviewed-by: Song Gao --- target/loongarch/cpu.c

RE: [RESEND RFC v1 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location

> -Original Message- > From: JeeHeng Sia > Sent: Wednesday, January 10, 2024 4:02 PM > To: Daniel Henrique Barboza ; qemu-...@nongnu.org; > qemu-devel@nongnu.org; qemu- > ri...@nongnu.org > Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com; > peter.mayd...@linaro.org; shanno

Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4]

On 1/8/2024 4:27 PM, Zhao Liu wrote: From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be calculated by pow2ceil() or by using

[PATCH v4 8/9b] target/loongarch: Implement set vcpu intr for kvm

From: Tianrui Zhao Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao Signed-off-by: xianglai li Reviewed-by: Song Gao Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn>

[PATCH v4 8/9a] target/loongarch: Restrict TCG-specific code

From: Tianrui Zhao In preparation of supporting KVM in the next commit. Signed-off-by: Tianrui Zhao Signed-off-by: xianglai li Reviewed-by: Song Gao Message-ID: <20240105075804.1228596-9-zhaotian...@loongson.cn> [PMD: Split from bigger patch, part 1] Signed-off-by: Philippe Mathieu-Daudé ---

Re: [PATCH v4 0/9] Add loongarch kvm accel support

Hi Song, On 10/1/24 03:46, gaosong wrote: 在 2024/1/5 下午3:57, Tianrui Zhao 写道: This series add loongarch kvm support, mainly implement some interfaces used by kvm, such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt, etc. Tianrui Zhao (9):    linux-headers: Syn

[PATCH] qemu-img: Fix Column Width and Improve Formatting in snapshot list

From: Abhiram Tilak When running the command `qemu-img snapshot -l SNAPSHOT` the output of VM_CLOCK (measures the offset between host and VM clock) cannot to accommodate values in the order of thousands (4-digit). This line [1] hints on the problem. Additionally, the column width for the VM_CLOC

Re: [PATCH v4 0/9] Add loongarch kvm accel support

在 2024/1/10 下午5:42, Philippe Mathieu-Daudé 写道: Hi Song, On 10/1/24 03:46, gaosong wrote: 在 2024/1/5 下午3:57, Tianrui Zhao 写道: This series add loongarch kvm support, mainly implement some interfaces used by kvm, such as kvm_arch_get/set_regs, kvm_arch_handle_exit, kvm_loongarch_set_interrupt,

Re: [PATCH] kvm: limit the maximum CPUID.0xA.edx[0..4] to 3

Anyone has suggestion? When the host kernel before this commit 2e8cd7a3b828 ("kvm: x86: limit the maximum number of vPMU fixed counters to 3") on icelake microarchitecture and newer, execute cpuid in the Guest: Architecture Performance Monitoring Features (0xa/edx): number of fixed counters

[PATCH v3 2/2] target/riscv: support new isa extension detection devicetree properties

From: Conor Dooley A few months ago I submitted a patch to various lists, deprecating "riscv,isa" with a lengthy commit message [0] that is now commit aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux kernel tree. Primarily, the goal was to replace "riscv,isa" with a new set o

[PATCH v3 0/2] riscv: support new isa extension detection devicetree properties

From: Conor Dooley Making it a series to keep the standalone change to riscv_isa_string() that Drew reported separate. Changes in v3: - g_free() isa_extensions too - use misa_mxl_max rather than the compile target for the base isa - add a new patch changing riscv_isa_string() to do the same - dr

[PATCH v3 1/2] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS

From: Conor Dooley A cpu may not have the same xlen as the compile time target, and misa_mxl_max is the source of truth for what the hart supports. Reported-by: Andrew Jones Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/ Signed-off-by: Conor Dooley --- Perhaps

Re: [PATCH v3 3/4] ci: Add a migration compatibility test job

On 09/01/2024 21.58, Fabiano Rosas wrote: Cédric Le Goater writes: On 1/5/24 19:04, Fabiano Rosas wrote: The migration tests have support for being passed two QEMU binaries to test migration compatibility. Add a CI job that builds the lastest release of QEMU and another job that uses that ve

Re: [PATCH v9 00/11] virtio: cleanup vhost-user-generic and reduce c&p + vhost-user-input

Alex Bennée writes: > A lot of our vhost-user stubs are large chunks of boilerplate that do > (mostly) the same thing. This series continues the cleanups by > splitting the vhost-user-base and vhost-user-generic implementations. > After adding a new vq_size property the rng, gpio and i2c vhost-us

[PATCH] io: add trace event when cancelling TLS handshake

Signed-off-by: Daniel P. Berrangé --- io/channel-tls.c | 1 + io/trace-events | 1 + 2 files changed, 2 insertions(+) diff --git a/io/channel-tls.c b/io/channel-tls.c index 58fe1aceee..1d9c9c72bf 100644 --- a/io/channel-tls.c +++ b/io/channel-tls.c @@ -381,6 +381,7 @@ static int qio_channel_tls

[PATCH] chardev: close QIOChannel before unref'ing

The chardev socket backend will unref the QIOChannel object while it is still potentially open. When using TLS there could be a pending TLS handshake taking place. If the channel is left open then when the TLS handshake callback runs, it can end up accessing free'd memory in the tcp_chr_tls_handsha

Re: [PATCH] kvm: limit the maximum CPUID.0xA.edx[0..4] to 3

> Anyone has suggestion? > > When the host kernel before this commit 2e8cd7a3b828 ("kvm: x86: limit the > maximum number of vPMU > fixed counters to 3") on icelake microarchitecture and newer, execute cpuid > in the Guest: > > Architecture Performance Monitoring Features (0xa/edx): > number o

Re: [PATCH v2 01/14] target/arm/cpu: Simplify checking A64_MTE bit in FEATURE_ID register

On Wed, 10 Jan 2024 at 06:01, Richard Henderson wrote: > > On 1/10/24 05:09, Philippe Mathieu-Daudé wrote: > > cpu_isar_feature(aa64_mte, cpu) is testing a AArch64-only ID > > register. The ARM_FEATURE_AARCH64 check is redundant. > > > > Signed-off-by: Philippe Mathieu-Daudé > > --- > > target/

Re: [PATCH v3 1/2] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS

On Wed, Jan 10, 2024 at 10:25:36AM +, Conor Dooley wrote: > From: Conor Dooley > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > Reported-by: Andrew Jones > Link: > https://lore.kernel.org/qemu-riscv/2

Re: [PATCH v3 2/2] target/riscv: support new isa extension detection devicetree properties

On Wed, Jan 10, 2024 at 10:25:37AM +, Conor Dooley wrote: > From: Conor Dooley > > A few months ago I submitted a patch to various lists, deprecating > "riscv,isa" with a lengthy commit message [0] that is now commit > aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux > ke

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