The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit operating system using PAE
to access memory a
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne need to check for user choice f
We'll add a new bare CPU type that won't have any default priv_ver. This
means that the CPU will default to priv_ver = 0, i.e. 1.10.0.
At the same we'll allow these CPUs to enable extensions at will, but
then, if the extension has a priv_ver newer than 1.10, we'll end up
disabling it. Users will t
Profiles will need to validate satp_mode during their own finalize
methods. This will occur inside riscv_tcg_cpu_finalize_features() for
TCG. Given that satp_mode does not have any pre-req from the accelerator
finalize() method, it's safe to finalize it earlier.
Signed-off-by: Daniel Henrique Barb
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.
Now that we're setting prof
Our current logic in get/setters of MISA and multi-letter extensions
works because we have only 2 CPU types, generic and vendor, and by using
"!generic" we're implying that we're talking about vendor CPUs. When adding
a third CPU type this logic will break so let's handle it beforehand.
In set_mis
Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit.
The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check
the first CPU of a given hart array, not any given CPU.
Create a helper to retrieve the info for any given CPU, not the first
CPU of the hart array. The he
We want to add a new CPU type for bare CPUs that will inherit specific
traits of the 2 existing types:
- it will allow for extensions to be enabled/disabled, like generic
CPUs;
- it will NOT inherit defaults, like vendor CPUs.
We can make this conditions met by adding an explicit type for the
Expose all profile flags for all CPUs when executing
query-cpu-model-expansion. This will allow callers to quickly determine
if a certain profile is implemented by a given CPU. This includes vendor
CPUs - the fact that they don't have profile user flags doesn't mean
that they don't implement the pr
Add a new profile CPU 'rva22s64' to work as an alias of
-cpu rv64i,rva22s64
Like the existing rva22u64 CPU already does with the RVA22U64 profile.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 8
2 files ch
Uh, I missed this one, my apologies! Let me have a quick look...
Commit message style nitpick:
qmp: Add command to retrieve eBPF blob
or
qmp: New command to retrieve eBPF blob
It's a title, not a sentence.
Andrew Melnychenko writes:
> Now, the binary objects may be retrieved by id.
Maksim Davydov writes:
> Thanks for reviewing
> Sorry for replying late
>
> On 12/1/23 12:49, Markus Armbruster wrote:
>> I apologize for the lateness of my review.
>>
>> Maksim Davydov writes:
>>
>>> To control that creating new machine type doesn't affect the previous
>>> types (their compat_p
Maksim Davydov writes:
> On 12/1/23 12:51, Markus Armbruster wrote:
>> Review, anyone?
>
> Only Vladimir
To be clear: I'm soliciting a second review.
[...]
On Mon, Dec 18, 2023 at 7:21 PM Daniel P. Berrangé
wrote:
> On Thu, Dec 07, 2023 at 12:37:41AM +0800, Hyman Huang wrote:
> > v2:
> > - Simplify the design by reusing the LUKS driver to implement
> > the generic Luks encryption, thank Daniel for the insightful
> > advice.
> > - rebase on maste
On Mon, Dec 18, 2023 at 2:54 PM Markus Armbruster wrote:
> Uh, I missed this one, my apologies! Let me have a quick look...
>
> Commit message style nitpick:
>
> qmp: Add command to retrieve eBPF blob
>
> or
>
> qmp: New command to retrieve eBPF blob
>
> It's a title, not a sentence.
>
>
On Mon, Dec 18, 2023 at 03:24:57PM +0200, Yuri Benditovich wrote:
> On Mon, Dec 18, 2023 at 2:54 PM Markus Armbruster wrote:
> > > +#
> > > +# Currently, there is a possible eBPF for receive-side scaling (RSS).
> > > +#
> > > +##
> > > +
> > > +##
> > > +# @EbpfObject:
> > > +#
> > > +# An eBPF EL
Hi Dehan,
Thanks for your patch
Please see my comment below
On Fri, Nov 24, 2023 at 5:40 AM Dehan Meng wrote:
> The Route information of the Linux VM needs to be used
> by administrators and users when debugging network problems
> and troubleshooting.
>
> Signed-off-by: Dehan Meng
> ---
> qga
Xiaoyao Li writes:
> On 12/1/2023 7:00 PM, Markus Armbruster wrote:
>> Xiaoyao Li writes:
>>
>>> From: Isaku Yamahata
>>>
>>> Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
>>> can be provided for TDX attestation.
>>>
>>> So far they were hard coded as 0. Now allow us
Sam Li writes:
> Markus Armbruster 于2023年11月30日周四 09:40写道：
>>
>> Sam Li writes:
[...]
>> > +##
>> > +# @Qcow2ZoneHostManaged:
>> > +#
>> > +# The host-managed zone model. It only allows sequential writes.
>> > +#
>> > +# @size: Total number of bytes within zones
>> > +#
>> > +# @capacity: Th
Akihiko Odaki writes:
> On 2023/12/11 15:51, Markus Armbruster wrote:
>> Akihiko Odaki writes:
>>
>>> The HotplugHandler of the machine will be used when the parent bus does
>>> not exist, but the machine may not have one. Report an error in such a
>>> case instead of aborting.
>>>
>>> Fixes: 7
On Mon, Dec 18, 2023 at 7:16 PM Daniel P. Berrangé
wrote:
> On Thu, Dec 07, 2023 at 12:37:44AM +0800, Hyman Huang wrote:
> > By enhancing the LUKS driver, it is possible to enable
> > the detachable LUKS header and, as a result, achieve
> > general encryption for any disk format that QEMU has
> >
On Mon, 18 Dec 2023 at 02:36, Philipp Hahn wrote:
> Am 15.12.23 um 16:21 schrieb Stefan Hajnoczi:
> >> Am 05.12.23 um 15:44 schrieb Stefan Hajnoczi:
> >>> On Tue, 5 Dec 2023 at 04:53, Philipp Hahn wrote:
> >> My main problem currently is cloning the MAC address: As our product is
> >> an operatin
On Mon, Dec 18, 2023 at 7:19 PM Daniel P. Berrangé
wrote:
> On Thu, Dec 07, 2023 at 12:37:45AM +0800, Hyman Huang wrote:
> > Provide the "detached-mode" option for detached LUKS header
> > formatting.
> >
> > To format the LUKS header on the pre-creating disk, example
> > as follows:
> >
> > 1. a
On Mon, Dec 18, 2023 at 10:15:34PM +0800, Yong Huang wrote:
> On Mon, Dec 18, 2023 at 7:16 PM Daniel P. Berrangé
> wrote:
> > > @@ -903,6 +928,17 @@ block_crypto_child_perms(BlockDriverState *bs,
> > BdrvChild *c,
> > >
> > > BlockCrypto *crypto = bs->opaque;
> > >
> > > +if (role == (ro
On Mon, Dec 18, 2023 at 01:41:38PM +0100, Fiona Ebner wrote:
> Am 14.12.23 um 20:53 schrieb Stefan Hajnoczi:
> >
> > I will still try the other approach that Hanna and Paolo have suggested.
> > It seems more palatable. I will send a v2.
> >
>
> FYI, what I already tried downstream (for VirtIO SC
On Thu, Dec 14, 2023 at 09:39:02PM +0100, Paolo Bonzini wrote:
> Il gio 14 dic 2023, 21:12 Stefan Hajnoczi ha scritto:
>
> > Since the fd may be bypassed until ->io_poll_end() returns, we must poll
> > one last time to check if an event snuck in right at the end without
> > making the fd readable
On Thu, 14 Dec 2023 at 21:15, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> - Created qtest to check initialization of registers in GMAC Module.
> - Implemented test into Build File.
>
> Signed-off-by: Nabih Estefan
> Reviewed-by: Tyrone Ting
> ---
> tests/qtest/meson.build |
On Thu, 14 Dec 2023 at 21:15, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> - Implemeted classes for GMAC Receive and Transmit Descriptors
> - Implemented Masks for said descriptors
>
> Signed-off-by: Nabih Estefan
> Reviewed-by: Tyrone Ting
> static const uint32_t npcm_gmac_cold_r
On Thu, 14 Dec 2023 at 21:15, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> - General GMAC Register handling
> - GMAC IRQ Handling
> - Added traces in some methods for debugging
> - Lots of declarations for accessing information on GMAC Descriptors
> (npcm_gmac.h file)
>
> NOTE: With cod
On Thu, 14 Dec 2023 at 21:15, Nabih Estefan wrote:
>
> From: Nabih Estefan Diaz
>
> - Add PCS Register check to npcm_gmac-test
>
> Signed-off-by: Nabih Estefan
> Reviewed-by: Tyrone Ting
> ---
> @@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data)
> #define CHECK_REG32(regno
On 12/18/2023 12:14 AM, Peter Xu wrote:
> On Wed, Dec 13, 2023 at 10:35:33AM -0500, Steven Sistare wrote:
>> Hi Peter, all have RB's, with all i's dotted and t's crossed - steve
>
> Yes this seems to be more migration related so maybe good candidate for a
> pull from migration submodule.
>
> But
On Mon, Dec 18, 2023 at 1:41 PM Fiona Ebner wrote:
> I think it's because of nested drains, because when additionally
> checking that the drain count is zero and only executing the loop then,
> that issue doesn't seem to manifest
But isn't virtio_scsi_drained_end only run if bus->drain_count == 0
On Thu, 14 Dec 2023 at 15:23, ~inesvarhol wrote:
>
> This patch adds a new STM32L4x5 SoC, it is necessary to add support for
> the B-L475E-IOT01A board.
> The implementation is derived from the STM32F405 SoC and NetduinoPlus2
> board.
> The implementation contains no peripherals, only memory regio
On Fri, 15 Dec 2023 at 12:05, Max Filippov wrote:
>
> r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register
> by the guest. The host uses 3 bits of the index for ITLB indexing and 4
> bits for DTLB, but there's only 7 entries in the ITLB array and 10 in
> the DTLB array, so a ma
Hi Alistair,
Thanks for providing some feedback - responses below:
On Mon, 2023-12-18 at 12:54 +1000, Alistair Francis wrote:
> On Fri, Dec 8, 2023 at 1:40 AM Rob Bradford
> wrote:
> >
> > From: Weiwei Li
> >
> > Add support for amocas.w/d/q instructions which are part of the
> > ratified
> >
Add a 'current_lun' check for a null value
to avoid null pointer dereferencing
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 4eb8606560 (esp: store lun coming from the MESSAGE OUT phase)
Signed-off-by: Alexandra Diupina
---
hw/scsi/esp.c | 5 +
1 file changed, 5 i
This series primarily enables external interrupt controllers (AIA and PLIC)
in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and
MMU related information.
Below ECRs for these changes are approved by ASWG and will be
available in next ACPI spec release.
1) MADT (AIA) -
https
RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Andrew
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/risc
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: A
RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Andrew
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 35 +++
1 file changed, 35 in
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize
With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.
Suggested-by: Andrew Jones
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/i386/acpi-microvm.c | 15 ++-
1 file changed, 2
Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.
Suggested-by: Igor Mammedov
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt.c | 47 -
inclu
Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 79 ++
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 36 +
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Acked-by: Michael S. Tsirkin
---
hw/riscv/virt-acpi-build.c | 43 ++
1 file chang
Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu
Signed-off-by: Sunil V L
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Acked-by: Michael S. Tsirkin
--
On Fri, 15 Dec 2023 at 15:16, Jean-Philippe Brucker
wrote:
>
> MDCR_EL2.HPMN allows an hypervisor to limit the number of PMU counters
> available to EL1 and EL0 (to keep the others to itself). QEMU already
> implements this split correctly, except for PMCR_EL0.N reads: the number
> of counters rea
On Sat, 16 Dec 2023 at 13:34, Nikita Ostrenkov wrote:
>
> Signed-off-by: Nikita Ostrenkov
> ---
> hw/misc/imx7_snvs.c | 93 ++---
> hw/misc/trace-events| 4 +-
> include/hw/misc/imx7_snvs.h | 7 ++-
> 3 files changed, 94 insertions(+), 10 deletio
Am 05.12.2023 um 19:20 hat Stefan Hajnoczi geschrieben:
> The bdrv_co_lock() and bdrv_co_unlock() functions are already no-ops.
> Remove them.
>
> Signed-off-by: Stefan Hajnoczi
Reviewed-by: Kevin Wolf
Am 05.12.2023 um 19:19 hat Stefan Hajnoczi geschrieben:
> Since the removal of AioContext locking, the correctness of the code
> relies on running requests from a single AioContext at any given time.
>
> Add assertions that verify that callbacks are invoked in the correct
> AioContext.
>
> Signed
Am 05.12.2023 um 19:20 hat Stefan Hajnoczi geschrieben:
> Now that the AioContext lock no longer exists, AIO_WAIT_WHILE() and
> AIO_WAIT_WHILE_UNLOCKED() are equivalent.
>
> A future patch will get rid of AIO_WAIT_WHILE_UNLOCKED().
>
> Signed-off-by: Stefan Hajnoczi
> Reviewed-by: Eric Blake
R
Am 05.12.2023 um 19:20 hat Stefan Hajnoczi geschrieben:
> The AioContext lock no longer has any effect. Remove it.
>
> Signed-off-by: Stefan Hajnoczi
> Reviewed-by: Eric Blake
Reviewed-by: Kevin Wolf
Am 05.12.2023 um 19:20 hat Stefan Hajnoczi geschrieben:
> Delete these functions because nothing calls these functions anymore.
>
> I introduced these APIs in commit 98563fc3ec44 ("aio: add
> aio_context_acquire() and aio_context_release()") in 2014. It's with a
> sigh of relief that I delete thes
On Mon, 18 Dec 2023 at 15:57, Peter Maydell wrote:
>
> On Mon, 4 Dec 2023 at 00:28, Sergey Kambalin wrote:
> >
> > Pre setup for BCM2838 introduction
> >
> > Signed-off-by: Sergey Kambalin
> > ---
>
> Reviewed-by: Peter Maydell
Whoops, I meant to send this as a reply to the v4 patch.
-- PMM
On Mon, 4 Dec 2023 at 00:28, Sergey Kambalin wrote:
>
> Pre setup for BCM2838 introduction
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 8 Dec 2023 at 02:40, Sergey Kambalin wrote:
>
> Pre-setup for BCM2838 introduction
>
> Signed-off-by: Sergey Kambalin
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 8 Dec 2023 at 02:32, Sergey Kambalin wrote:
>
> Pre setup for BCM2838 introduction
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 8 Dec 2023 at 02:36, Sergey Kambalin wrote:
>
> Pre-setup for raspberry pi 4 introduction
>
> Signed-off-by: Sergey Kambalin
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 100 +++
> hw/arm/bcm2838_peripherals.c | 72 +++
> hw/arm/meson.build | 2 +
> include/hw/ar
strerrorname_np is non-portable and breaks building with musl libc.
Use strerror(errno) instead, like we do other places.
Cc: qemu-sta...@nongnu.org
Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error
msg)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2041
B
On Fri, 8 Dec 2023 at 02:32, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 167 +++
> hw/arm/trace-events | 2 +
> include/hw/arm/bcm2838.h | 2 +
> include/hw/arm/bcm2838_peripher
On Fri, 8 Dec 2023 at 02:39, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 4 +-
> hw/gpio/bcm2838_gpio.c | 152 +++
> hw/gpio/meson.build | 5 +-
> include/hw/arm/bcm2838_periph
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/gpio/bcm2838_gpio.c | 192 -
> 1 file changed, 189 insertions(+), 3 deletions(-)
> static uint64_t bcm2838_gpio_read(void *opaque, hwaddr offset, unsigned s
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/gpio/bcm2838_gpio.c | 59 +++---
> include/hw/gpio/bcm2838_gpio.h | 5 +++
> 2 files changed, 60 insertions(+), 4 deletions(-)
>
> diff --git a/hw/gpio/bcm2838_g
On Fri, 8 Dec 2023 at 02:37, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 140 +++
> include/hw/arm/bcm2838_peripherals.h | 9 ++
> 2 files changed, 149 insertions(+)
> @@ -42,6 +73,115 @@ static void bcm2838
On Fri, 8 Dec 2023 at 02:33, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/bcm2838_peripherals.c b/hw/arm/bcm2838_peripherals.c
> index c147b6e453..196fb890a2 100644
>
On Mon, 4 Dec 2023 at 00:27, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi Alistair,
Thanks for the lightning fast reply!
Could you please tell who should bump those numbers and to what values?
Do you think I could submit this patch series for the review?
Thanks
пн, 18 дек. 2023 г. в 06:11, Alistair Francis :
> On Sat, Dec 16, 2023 at 11:52 PM Alexey Baturo
> wrot
On 12/18/23 13:22, Natanael Copa wrote:
strerrorname_np is non-portable and breaks building with musl libc.
Use strerror(errno) instead, like we do other places.
Cc: qemu-sta...@nongnu.org
Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error
msg)
Resolves: https:/
On Mon, 18 Dec 2023 at 17:22, Daniel Henrique Barboza
wrote:
>
>
>
> On 12/18/23 13:22, Natanael Copa wrote:
> > strerrorname_np is non-portable and breaks building with musl libc.
> >
> > Use strerror(errno) instead, like we do other places.
> >
> > Cc: qemu-sta...@nongnu.org
> > Fixes: commit 08
On 12/18/23 14:53, Peter Maydell wrote:
On Mon, 18 Dec 2023 at 17:22, Daniel Henrique Barboza
wrote:
On 12/18/23 13:22, Natanael Copa wrote:
strerrorname_np is non-portable and breaks building with musl libc.
Use strerror(errno) instead, like we do other places.
Cc: qemu-sta...@nongnu.
On Mon, Dec 11, 2023 at 11:44 AM Fabiano Rosas wrote:
>
> Hao Xiang writes:
>
> > Intel DSA offloading is an optional feature that turns on if
> > proper hardware and software stack is available. To turn on
> > DSA offloading in multifd live migration:
> >
> > multifd-dsa-accel="[dsa_dev_path1] ]
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
are able to relocate their SuperI/O functions. Add a convenience function for
implementing this in the VIA south bridges.
This convenience function relies on previous simplifications in exec/ioport
which avoids some dupl
This series implements relocation of the SuperI/O functions of the VIA south
bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t
branch [1] which is an extension of bringing the VIA south bridges to the PC
machine [2]. This branch is able to run some real-world X86 BIOSes in t
portio_list_add_1() creates a MemoryRegionPortioList instance which holds a
MemoryRegion `mr` and an array of MemoryRegionPortio elements named `ports`.
Each element in the array gets assigned the same value for its .base attribute.
The same value also ends up as the .addr attribute of `mr` due to
ParallelState::portio_list isn't used inside ParallelState context but only
inside ISAParallelState context, so more it there.
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel-isa.h | 2 ++
include/hw/char/parallel.h | 2 --
hw/char/parallel.c | 2 +-
3 files changed,
Implement isa_fdc_set_{enabled,iobase} in order to implement relocation and
toggling of SuperI/O functions in the VIA south bridges without breaking
encapsulation.
Signed-off-by: Bernhard Beschow
---
include/hw/block/fdc.h | 3 +++
hw/block/fdc-isa.c | 14 ++
2 files changed, 17
FDCtrl::iomem isn't used inside FDCtrl context but only inside FDCtrlSysBus
context, so more it there.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-internal.h | 2 --
hw/block/fdc-sysbus.c | 6 --
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/block/fdc-internal.h b/
FDCtrl::portio_list isn't used inside FDCtrl context but only inside
FDCtrlISABus context, so more it there.
Signed-off-by: Bernhard Beschow
---
hw/block/fdc-internal.h | 2 --
hw/block/fdc-isa.c | 4 +++-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/block/fdc-internal.
The VIA south bridges are able to relocate and toggle (enable or disable) their
SuperI/O functions. So far this is hardcoded such that all functions are always
enabled and are located at fixed addresses.
Some PC BIOSes seem to probe for I/O occupancy before activating such a function
and issue an
This is a preparation for implementing relocation and toggling of SuperI/O
functions in the VT8231 device model. Upon reset, all SuperI/O functions will be
deactivated, so in case if no -bios is given, let the machine configure those
functions the same way pegasos2.rom would do. For now the meantim
Some SuperI/O devices such as the VIA south bridges or the PC87312 controller
allow to enable or disable their SuperI/O functions. Add a convenience function
for implementing this in the VIA south bridges.
The naming of the functions is inspired by its memory_region_set_enabled()
pendant.
Signed-
SerialState::io isn't used within TYPE_SERIAL directly. Push it to its users to
make them the owner of the MemoryRegion.
Signed-off-by: Bernhard Beschow
---
include/hw/char/serial.h | 2 +-
hw/char/serial-isa.c | 7 +--
hw/char/serial-pci-multi.c | 7 ---
hw/char/serial-pci.c
Implement isa_serial_set_{enabled,iobase} in order to implement relocation and
toggling of SuperI/O functions in the VIA south bridges without breaking
encapsulation.
Signed-off-by: Bernhard Beschow
---
include/hw/char/serial.h | 2 ++
hw/char/serial-isa.c | 14 ++
2 files chang
Implement isa_parallel_set_{enabled,iobase} in order to implement relocation and
toggling of SuperI/O functions in the VIA south bridges without breaking
encapsulation.
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel-isa.h | 3 +++
hw/char/parallel-isa.c | 14 ++
Am 18. Dezember 2023 10:54:56 UTC schrieb BALATON Zoltan :
>On Sun, 17 Dec 2023, Bernhard Beschow wrote:
>> Am 17. Dezember 2023 15:47:33 UTC schrieb BALATON Zoltan
>> :
>>> On Sun, 17 Dec 2023, Bernhard Beschow wrote:
Exposing the internal header allows for exposing struct FDCtrlISABus wh
On Sun, Dec 17, 2023 at 7:11 PM Wang, Lei wrote:
>
> On 11/14/2023 13:40, Hao Xiang wrote:> * Create a dedicated thread for DSA
> task
> completion.
> > * DSA completion thread runs a loop and poll for completed tasks.
> > * Start and stop DSA completion thread during DSA device start stop.
> >
>
Hi. I wanted to follow up with information to test/reproduce this BUG/issue.
Steps to reproduce:
1. Use the following options with QEMU (configured with OVMF):
-S -smp 2,maxcpus=260,sockets=2,cores=65,threads=2
2. Start QEMU and when QEMU reaches the paused state (due to -S),
issue t
Add support for RVV and Vector CSR KVM regs vstart, vl and vtype.
Support for vregs[] requires KVM side changes and an extra reg (vlenb)
and will be added later.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/kvm/kvm-cpu.c | 74 +++
Linux RISC-V vector documentation (Document/arch/riscv/vector.rst)
mandates a prctl() in order to allow an userspace thread to use the
Vector extension from the host.
This is something to be done in realize() time, after init(), when we
already decided whether we're using RVV or not. We don't have
KVM vector support for RISC-V requires the linux-header ptrace.h.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
linux-headers/asm-riscv/ptrace.h | 132 +++
scripts/update-linux-headers.sh | 3 +
2 files changed, 135 insertions(+)
create mo
Hi,
This version was rebased on top of Alistair's riscv-to-apply.next. A
small tweak was needed in patch 4 due to changes in the branch.
I took the chance to update linux-headers to 6.7-rc5, although the
differences from the rc3 headers from v1 were minimal.
All patches acked.
Changes from v1:
We'll add a new RISC-V linux-header file, but first let's update all
headers.
Headers for 'asm-loongarch' were added in this update.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
include/standard-headers/drm/drm_fourcc.h | 2 +
include/standard-headers/linux/pci_r
On 12/18/23 13:22, Natanael Copa wrote:
strerrorname_np is non-portable and breaks building with musl libc.
Use strerror(errno) instead, like we do other places.
Cc: qemu-sta...@nongnu.org
Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error
msg)
Resolves: https:/
On 12/18/23 06:05, Yong-Xuan Wang wrote:
The interrupts-extended property of PLIC only has 2 * hart number
fields when KVM enabled, copy 4 * hart number fields to fdt will
expose some uninitialized value.
In this patch, I also refactor the code about the setting of
interrupts-extended propert
18.12.2023 20:20, Daniel Henrique Barboza wrote:
On 12/18/23 13:22, Natanael Copa wrote:
strerrorname_np is non-portable and breaks building with musl libc.
Use strerror(errno) instead, like we do other places.
Cc: qemu-sta...@nongnu.org
Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve
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