FYI, these patches still need RB:
migration: propagate suspended runstate
tests/qtest: precopy migration with suspend
tests/qtest: postcopy migration with suspend
This has RB, but the interaction between vm_start and vm_prepare_start
changed, so needs another look.
cpus: stop vm in suspe
On Wed, Nov 29, 2023 at 11:17:49PM +0800, Hyman Huang wrote:
> Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
>
> SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> Organization of State Commercial Administration of China (OSCCA)
> as an authorized cryptographic algorit
On Wed, Dec 06, 2023 at 07:20:14PM +0200, Maxim Levitsky wrote:
> On Tue, 2023-12-05 at 16:28 -0600, Michael Roth wrote:
> > Commit 7191f24c7fcf ("accel/kvm/kvm-all: Handle register access errors")
> > added error checking for KVM_SET_SREGS/KVM_SET_SREGS2. In doing so, it
> > exposed a long-running
Hi Steve,
On 6/12/23 18:23, Steve Sistare wrote:
Currently, a vm in the suspended state is not completely stopped. The VCPUs
have been paused, but the cpu clock still runs, and runstate notifiers for
the transition to stopped have not been called. This causes problems for
live migration. Stal
On Wed, Dec 06, 2023 at 10:37:33AM -0600, Madhavan T. Venkataraman wrote:
>
>
> On 11/30/23 05:33, Peter Zijlstra wrote:
> > On Wed, Nov 29, 2023 at 03:07:15PM -0600, Madhavan T. Venkataraman wrote:
> >
> >> Kernel Lockdown
> >> ---
> >>
> >> But, we must provide at least some securi
On 12/6/2023 1:45 PM, Philippe Mathieu-Daudé wrote:
> Hi Steve,
>
> On 6/12/23 18:23, Steve Sistare wrote:
>> Currently, a vm in the suspended state is not completely stopped. The VCPUs
>> have been paused, but the cpu clock still runs, and runstate notifiers for
>> the transition to stopped have
On 12/6/23 16:58, Michael Roth wrote:
Commit 7191f24c7fcf ("accel/kvm/kvm-all: Handle register access errors")
added error checking for KVM_SET_SREGS/KVM_SET_SREGS2. In doing so, it
exposed a long-running bug in current KVM support for SEV-ES where the
kernel assumes that MSR_EFER_LMA will be set
On 6/12/23 20:19, Steven Sistare wrote:
On 12/6/2023 1:45 PM, Philippe Mathieu-Daudé wrote:
Hi Steve,
On 6/12/23 18:23, Steve Sistare wrote:
Currently, a vm in the suspended state is not completely stopped. The VCPUs
have been paused, but the cpu clock still runs, and runstate notifiers for
t
On 6/12/23 21:48, Philippe Mathieu-Daudé wrote:
On 6/12/23 20:19, Steven Sistare wrote:
On 12/6/2023 1:45 PM, Philippe Mathieu-Daudé wrote:
Hi Steve,
On 6/12/23 18:23, Steve Sistare wrote:
Currently, a vm in the suspended state is not completely stopped.
The VCPUs
have been paused, but the c
From: Potin Lai
Add pca9543 2-channel i2c-mux switch support.
Signed-off-by: Potin Lai
Reviewed-by: Patrick Venture
Message-Id: <20231113063156.2264941-1-potin.lai...@gmail.com>
Signed-off-by: Corey Minyard
---
hw/i2c/i2c_mux_pca954x.c | 12
include/hw/i2c/i2c_mux_pca954
From: Titus Rwantare
Reviewed-by: Patrick Venture
Reviewed-by: Chris Rauer
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
Message-Id: <20220106173814.3580141-1-vent...@google.com>
Signed-off-by: Corey Minyard
---
hw/sensor/adm1272.c| 27 ++-
tests/qtest/ad
From: Corey Minyard
Some minor I2C changes. One has been sitting in my queue forgotten for
a while, but still needs to go in. The other is fairly recent. Both
are for BMC related stuff.
These are available at:
https://github.com/cminyard/qemu.git i2c-for-release-2023-12-06
and signed by me
Hello,
Thank you for the review and suggestions on V6.
The suggestions and changes requested from V6 are addressed in V7.
Updates in Version 7 of this series are:
There are no major changes done in revision 7 from revision 6.
1. The property "parent-obj-name" is removed from nest pervasive chi
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 0
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet cont
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-specific registers. All nest
chiplets ha
On 12/1/23 00:55, Sebastian Ott wrote:
On Tue, 28 Nov 2023, Shaoqin Huang wrote:
+static void kvm_arm_pmu_filter_init(CPUState *cs)
+{
+ static bool pmu_filter_init = false;
+ struct kvm_pmu_event_filter filter;
+ struct kvm_device_attr attr = {
+ .group = KVM_ARM_VCPU_PM
Hi Gavin,
On 12/1/23 13:37, Gavin Shan wrote:
Hi Shaoqin,
On 11/29/23 14:08, Shaoqin Huang wrote:
The KVM_ARM_VCPU_PMU_V3_FILTER provide the ability to let the VMM decide
which PMU events are provided to the guest. Add a new option
`pmu-filter` as -accel sub-option to set the PMU Event Filteri
On Thu, Dec 7, 2023 at 1:41 AM Daniel P. Berrangé
wrote:
> On Wed, Nov 29, 2023 at 11:17:49PM +0800, Hyman Huang wrote:
> > Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
> >
> > SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> > Organization of State Commercial Admi
On 11/18/2023 5:18 AM, Isaku Yamahata wrote:
On Wed, Nov 15, 2023 at 02:14:27AM -0500,
Xiaoyao Li wrote:
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's se
On 11/15/2023 6:54 PM, Daniel P. Berrangé wrote:
+static int tdx_ioctl_internal(void *state, enum tdx_ioctl_level level, int
cmd_id,
+__u32 flags, void *data)
+{
+struct kvm_tdx_cmd tdx_cmd;
Add ' = {}' to initialize to all-zeros, avoiding the explicit
memset call
On 12/1/2023 7:02 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation Service.
Add property "quote-generation-socket" to tdx-guest, whihc is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On re
On 12/7/23 03:43, Chalapathi V wrote:
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet-
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