On 28/11/23 12:46 pm, Markus Armbruster wrote:
Your commit message is all in one line. You need to format it like
migration: Plug memory leak
'channel' and 'addr' in qmp_migrate() are not auto-freed.
migrate_uri_parse() allocates memory which is returned to 'channel',
whi
Signed-off-by: Gerd Hoffmann
---
pc-bios/bios-256k.bin | Bin 262144 -> 262144 bytes
pc-bios/bios-microvm.bin | Bin 131072 -> 131072 bytes
pc-bios/bios.bin | Bin 131072 -> 131072 bytes
pc-bios/vgabios-ati.bin | Bin 39424 -> 39424 bytes
pc-bios/vg
re/seabios-20231128-pull-request
for you to fetch changes up to eb0ce1346eca79f066e571dc5845f99f9ec730c3:
seabios: update binaries to 1.16.3 release (2023-11-28 08:49:26 +0100)
seabios: update to 1.16.3 release
This adds one bugfi
git shortlog 1e1da7a96300..rel-1.16.3
-
Gerd Hoffmann (1):
limit address space used for pci devices.
Signed-off-by: Gerd Hoffmann
---
roms/seabios | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/roms/seabios b/roms/seabios
index 1e1d
Shiyuan Gao via writes:
> From: Gao Shiyuan
>
> No remove QemuOptsList from *_config_groups, so no need to
> traverse from the beginning every time.
>
> No functional changes.
>
> Signed-off-by: Gao Shiyuan
> ---
> include/qemu/config-file.h | 3 +++
> util/qemu-config.c | 18
On 2023/11/18 21:10, Akihiko Odaki wrote:
Hi,
We are planning to add PCIe SR-IOV support to the virtio-net driver
for Windows ("NetKVM")[1], and we want a SR-IOV feature for virtio-net
emulation code in QEMU to test it. I expect there are other people
interested in such a feature, consideri
28.11.2023 11:17, Gerd Hoffmann :
seabios: update to 1.16.3 release
Gerd, please also push this tag to seabios master git branch.
Thanks,
/mjt
On 28/11/23 08:07, Cédric Le Goater wrote:
On 11/28/23 02:47, Nicholas Piggin wrote:
On Tue Nov 28, 2023 at 2:37 AM AEST, Cédric Le Goater wrote:
I'm not sure, I don't think it's necessary if your minimal patch works.
I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
thi
John Snow writes:
> With strict typing enabled, these runtime statements aren't necessary
> anymore.
>
> Signed-off-by: John Snow
> ---
> scripts/qapi/schema.py | 23 ---
> 1 file changed, 23 deletions(-)
>
> diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py
> ind
On Tue, Nov 28, 2023 at 11:54:34AM +0300, Michael Tokarev wrote:
> 28.11.2023 11:17, Gerd Hoffmann :
>
> > seabios: update to 1.16.3 release
>
> Gerd, please also push this tag to seabios master git branch.
Can't push to master branch right now (the tag is in the repo though),
trying to sort thi
On 27/11/23 00:12, Gavin Shan wrote:
The 'host' CPU model isn't available until KVM or HVF is enabled.
For example, the following error messages are seen when the guest
is started with option '-cpu cortex-a8' on tcg after the next commit
is applied to check the CPU type in machine_run_board_init(
On 27/11/23 00:12, Gavin Shan wrote:
Set mc->valid_cpu_types so that the user specified CPU type can
be validated in machine_run_board_init(). We needn't to do it by
ourselves.
Signed-off-by: Gavin Shan
Reviewed-by: Richard Henderson
---
hw/arm/bananapi_m2u.c | 12 ++--
hw/arm/cub
On 2023/11/28 17:47, Yui Washizu wrote:
On 2023/11/18 21:10, Akihiko Odaki wrote:
Hi,
We are planning to add PCIe SR-IOV support to the virtio-net driver
for Windows ("NetKVM")[1], and we want a SR-IOV feature for virtio-net
emulation code in QEMU to test it. I expect there are other people
Hi Gavin,
On 27/11/23 00:12, Gavin Shan wrote:
The logic, to check if the specified CPU type is supported in
machine_run_board_init(), is independent enough. Factor it out into
helper is_cpu_type_supported(). machine_run_board_init() looks a bit
clean with this. Since we're here, @machine_class
Hi Gavin,
On 27/11/23 00:12, Gavin Shan wrote:
QEMU will be terminated if the specified CPU type isn't supported
in machine_run_board_init(). The list of supported CPU type names
is tracked by mc->valid_cpu_types.
The error handling can be used to propagate error messages, to be
consistent how
Hi Gavin,
On 27/11/23 00:12, Gavin Shan wrote:
The names of supported CPU models instead of CPU types should be
printed when the user specified CPU type isn't supported, to be
consistent with the output from '-cpu ?'.
Correct the error messages to print CPU model names instead of CPU
type names
Het Gala writes:
> On 28/11/23 12:46 pm, Markus Armbruster wrote:
>> Your commit message is all in one line. You need to format it like
>>
>> migration: Plug memory leak
>>
>> 'channel' and 'addr' in qmp_migrate() are not auto-freed.
>> migrate_uri_parse() allocates memory which
On 27/11/23 15:56, Zhao Liu wrote:
From: Zhao Liu
Remove unused header (qemu/module.h and sysemu/cpus.h) in core.c,
and reorder the remaining header files (except qemu/osdep.h) in
alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/cpu/core.c | 7 +++
On 27/11/23 15:56, Zhao Liu wrote:
From: Zhao Liu
Remove unused header (qemu/module.h and qemu/cutils.h) in cluster.c,
and reorder the remaining header files (except qemu/osdep.h) in
alphabetical order.
Tested by "./configure" and then "make".
Signed-off-by: Zhao Liu
---
hw/cpu/cluster.c |
On 27/11/23 12:37, Daniel Henrique Barboza wrote:
Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit.
The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check
the first CPU of a given hart array, not any given CPU.
Create a helper to retrieve the info for any gi
On Mon, 27 Nov 2023 at 19:44, Jai Arora wrote:
>
> To remove DPRINTF macros and use tracepoints
> for logging.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1827
>
> Signed-off-by: Jai Arora
> ---
> accel/kvm/kvm-all.c| 32 ++--
> accel/kvm/trace-eve
This makes easier to build an error path in next patches. No functional
change.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 57a8043cd4..449c3794b2 100
So the vDPA backend knows when a migration incoming starts. NicState
argument is needed so we can get the dma address space.
Signed-off-by: Eugenio Pérez
---
RFC v2:
* Solve git conflict with .set_steering_ebpf
* Fix x-svq=on use case which did not allocated iova_tree.
---
include/net/net.h |
There was only one call. This way we can make the begin and end of the
batch symmetrical.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index bf977187
The backend does not reset them until the vdpa file descriptor is closed
so there is no harm in doing it only once.
This allows the destination of a live migration to premap memory in
batches, using VHOST_BACKEND_F_IOTLB_BATCH.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 50 ++
To map the guest memory while it is migrating we need to create the
iova_tree, as long as the destination uses x-svq=on. Checking to not
override it.
The function vhost_vdpa_net_client_stop clear it if the device is
stopped. If the guest starts the device again, the iova tree is
recreated by vhost
Current memory operations like pinning may take a lot of time at the
destination. Currently they are done after the source of the migration is
stopped, and before the workload is resumed at the destination. This is a
period where neigher traffic can flow, nor the VM workload can continue
(downtim
Callers can use this function to setup the incoming migration thread.
This thread is able to map the guest memory while the migration is
ongoing, without blocking QMP or other important tasks. While this
allows the destination QEMU not to block, it expands the mapping time
during migration instead
Prefer early return so it is easier to merge
vhost_vdpa_listener_begin_batch here and make iotlb baches begin and end
symmetrical.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio
Next commits will set DRIVER and ACKNOWLEDGE flags repeatedly in the
case of a migration destination. Let's save ioctls with this.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
inde
So we can call out vhost_vdpa_dma_end_batch out of the listener
callbacks.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index a533fc5bc7..57a8043cd4 100644
--
This way VirtIONet can detect when the incoming migration starts.
While registering in the backend (nc->peer) seems more logical, we need
nic dma address space, and we cannot get it from the backend.
Signed-off-by: Eugenio Pérez
---
This could be done in vhost_vdpa or VirtIODevice struct, but fu
Hi
On Mon, Nov 27, 2023 at 2:52 PM Fiona Ebner wrote:
>
> Am 27.11.23 um 10:15 schrieb Marc-André Lureau:
> >
> > It seems like a bug in tigervnc then. For some reason, the compressed
> > data doesn't trigger Z_STREAM_END on the decompression side. Have you
> > investigated or reported an issue t
Hi,
On 20/7/21 21:54, Richard Henderson wrote:
Trigger breakpoints before beginning translation of a TB
that would begin with a BP. Thus we never generate code
for the BP at all.
Single-step instructions within a page containing a BP so
that we are sure to check each insn for the BP as above.
Hi,
On 6/11/19 00:41, Beata Michalska wrote:
ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVADP. Both specify conceptual points in a memory system where all writes
that are to reach them are conside
On Tue, 28 Nov 2023 at 11:24, Philippe Mathieu-Daudé wrote:
>
> Hi,
>
> On 6/11/19 00:41, Beata Michalska wrote:
> > ARMv8.2 introduced support for Data Cache Clean instructions
> > to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
> > - DV CVADP. Both specify conceptual
On 28/11/23 3:29 pm, Markus Armbruster wrote:
Het Gala writes:
On 28/11/23 12:46 pm, Markus Armbruster wrote:
Your commit message is all in one line. You need to format it like
migration: Plug memory leak
'channel' and 'addr' in qmp_migrate() are not auto-freed.
migrat
On 28/11/23 12:34, Peter Maydell wrote:
On Tue, 28 Nov 2023 at 11:24, Philippe Mathieu-Daudé wrote:
Hi,
On 6/11/19 00:41, Beata Michalska wrote:
ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVAD
On Fri, 10 Nov 2023 15:26:40 -0800
Davidlohr Bueso wrote:
> Two functions were reported to have dead code, remove the bogus
> branches altogether, as well as a misplaced qemu_log call.
>
> Reported-by: Peter Maydell
> Signed-off-by: Davidlohr Bueso
LGTM.
Michael, if you want to pick this up d
John Snow writes:
> This is not a clear win, but I was confused and I couldn't help myself.
>
> Before:
>
> lookup_entity(self, name: str, typ: Optional[type] = None
> ) -> Optional[QAPISchemaEntity]: ...
>
> lookup_type(self, name: str) -> Optional[QAPISchemaType]: ...
>
> resolve_
Het Gala writes:
> On 28/11/23 3:29 pm, Markus Armbruster wrote:
>> Het Gala writes:
>>
>>> On 28/11/23 12:46 pm, Markus Armbruster wrote:
Your commit message is all in one line. You need to format it like
migration: Plug memory leak
'channel' and 'addr' in
On Tue, 28 Nov 2023, Cédric Le Goater wrote:
On 11/28/23 02:47, Nicholas Piggin wrote:
On Tue Nov 28, 2023 at 2:37 AM AEST, Cédric Le Goater wrote:
I'm not sure, I don't think it's necessary if your minimal patch works.
I'll do a PR for 8.2 for SLOF and Skiboot updates, so happy to include
t
On Tue, 28 Nov 2023 09:27:28 +0900
Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> On Tue, Nov 28, 2023 at 2:53 AM Davidlohr Bueso wrote:
> >
> > On Mon, 27 Nov 2023, Hyeonggon Yoo wrote:
> >
> > >commit 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background
> > >completion") enables notify
On 11/28/23 02:32, BALATON Zoltan wrote:
The machine uses a modified U-Boot under GPL license but the sources
of it are lost with only a binary available so it cannot be included
in QEMU. Allow running without the firmware image which can be used
when calling a boot loader directly and thus simpl
On Sun, 26 Nov 2023, BALATON Zoltan wrote:
Philippe,
Could this be merged for 8.2 as it fixes USB on the amigaone machine?
This would be useful as usb-storage is the simplest way to share data
with the host with these machines.
Philippe, do you have some time to look at this now for 8.2 please
On 01/09/2023 07:01, LIU Zhiwei wrote:
When memory region is ram, the lower TARGET_PAGE_BITS is not the
physical section number. Instead, its value is always 0.
Add comment and assert to make it clear.
Signed-off-by: LIU Zhiwei
---
accel/tcg/cputlb.c | 11 +++
include/exec/cpu
On 27/11/23 14:49, Zhao Liu wrote:
From: Zhao Liu
From s390_possible_cpu_arch_ids() in hw/s390x/s390-virtio-ccw.c, the
"core-id" is the index of possible_cpus->cpus[], so it should only be
less than possible_cpus->len, which is equal to ms->smp.max_cpus.
Fix the wrong "core-id" 112, because i
On 23/11/23 22:15, Samuel Tardieu wrote:
This file is the only one involved in the compilation process which
still uses the /bin/bash path.
Signed-off-by: Samuel Tardieu
---
target/hexagon/idef-parser/prepare | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Patch queued, thanks!
Phil
On 27/11/23 20:22, Philippe Mathieu-Daudé wrote:
Hi Gihun,
On 27/11/23 03:54, Gihun Nam wrote:
The current implementation initializes the stack pointer of AVR devices
to 0. Although older AVR devices used to be like that, newer ones set
it to RAMEND.
Resolves: https://gitlab.com/qemu-project/q
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On 11/22/2023 11:21 AM, Peter Xu wrote:
> On Wed, Nov 22, 2023 at 09:38:06AM +, Daniel P. Berrangé wrote:
>> On Mon, Nov 20, 2023 at 04:44:50PM -0500, Peter Xu wrote:
>>> On Mon, Nov 20, 2023 at 03:55:54PM -0500, Steven Sistare wrote:
If we drop force, then all calls to vm_stop will comple
Hi Zoltan,
On 28/11/23 13:47, BALATON Zoltan wrote:
On Sun, 26 Nov 2023, BALATON Zoltan wrote:
Philippe,
Could this be merged for 8.2 as it fixes USB on the amigaone machine?
This would be useful as usb-storage is the simplest way to share data
with the host with these machines.
Philippe, do
From: Gihun Nam
The current implementation initializes the stack pointer of AVR devices
to 0. Although older AVR devices used to be like that, newer ones set
it to RAMEND.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525
Signed-off-by: Gihun Nam
Reviewed-by: Philippe Mathieu-Daudé
From: Samuel Tardieu
This file is the only one involved in the compilation process which
still uses the /bin/bash path.
Signed-off-by: Samuel Tardieu
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Message-ID: <20231123211506.636533-1-...@rfc1149.net>
Signed-off-by: Philippe
The following changes since commit e867b01cd6658a64c16052117dbb18093a2f9772:
Merge tag 'qga-pull-2023-11-25' of https://github.com/kostyanf14/qemu into
staging (2023-11-27 08:59:00 -0500)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/misc-nex
From: BALATON Zoltan
This device is part of a superio/ISA bridge chip and IRQs from it are
routed to an ISA interrupt. Use via_isa_set_irq() function to implement
this in a vt82c686-uhci-pci specific irq handler.
This reverts commit 422a6e8075752bc5342afd3eace23a4990dd7d98.
Signed-off-by: BALAT
From: BALATON Zoltan
The VIA integrated south bridge chips combine several functions and
allow routing their interrupts to any of the ISA IRQs also allowing
multiple sources to share the same ISA IRQ. E.g. pegasos2 firmware
configures everything to use IRQ 9 but amigaone routes them to
separate I
From: Zhao Liu
>From s390_possible_cpu_arch_ids() in hw/s390x/s390-virtio-ccw.c, the
"core-id" is the index of possible_cpus->cpus[], so it should only be
less than possible_cpus->len, which is equal to ms->smp.max_cpus.
Fix the wrong "core-id" 112, because it isn't less than maxcpus (36) in
-sm
From: BALATON Zoltan
This device is a function of VIA south bridge and should allow setting
interrupt routing within that chip. This is implemented in
via_isa_set_irq().
Fixes: eb604411a78b82c468e2b8d81a9401eb8b9c7658
Signed-off-by: BALATON Zoltan
Message-ID:
<5329840e4be6dd8ae143d07cbfe61d8d2
From: BALATON Zoltan
The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in
VT8231) that are meant to be connected to PCI IRQ lines and allow
routing PCI interrupts to the ISA PIC. Route these in
via_isa_set_irq() to make it possible to share them with internal
functions that can also be
Am 26.06.23 um 14:29 schrieb Michael S. Tsirkin:
> From: Suravee Suthikulpanit
>
> Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
> supported since QEMU 7.0, default to use SMBIOS 3.0 for newer
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
Missed in commit 2d56be5a29 ("target: Declare
FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See
it for more details.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-qom.h | 3 +++
target/arm/cpu.h | 2 --
2 files changed, 3 insertio
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
The ARM_CPU_IRQ/FIQ definitions are meant for the ARM CPU
QOM model. Move them to "cpu-qom.h" so any QOM code can
use them.
Signed-off-by: Philippe Mathieu-Daudé
---
Or do these definitions belong to cpu-defs.h?
I think they belong with the qom
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
To allow GTIMER_* definitions to be used by non-ARM specific
hardware models, move them to a new target agnostic "cpu-defs.h"
header.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-defs.h | 19 +++
target/arm/cpu.h
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
bcm2836_realize() is called by
- bcm2836_class_init() which sets:
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7")
- bcm2837_class_init() which sets:
bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53")
Both Cortex-A7 / A53 have the ARM_F
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
All ARM CPUs have the 'start-powered-off' property since commit
5de164304a ("arm: Allow secondary KVM CPUs to be booted via PSCI").
Note: since commit c1b701587e ("target/arm: Move start-powered-off
property to generic CPUState"), all CPUs for all
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
The 'mp-affinity' property is present since commit 15a21fe028
("target-arm: Add mp-affinity property for ARM CPU class").
Use it and remove a /* TODO */ comment. Since all ARM CPUs
have this property, use &error_abort, because this call can
not fai
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
The ARMCPU type is forward declared as a pointer to all hw/ files.
Its declaration is restricted to target/arm/ files. By using a
pointer in BCM283XState instead of embedding the whole CPU state,
we don't need to include "cpu.h" which is target-spe
The following changes since commit e867b01cd6658a64c16052117dbb18093a2f9772:
Merge tag 'qga-pull-2023-11-25' of https://github.com/kostyanf14/qemu into
staging (2023-11-27 08:59:00 -0500)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to
From: Andrey Drobyshev
The machine type is being detected based on "-M help" output, and we're
searching for the line ending with " (default)". However, in downstream
one of the machine types s marked as deprecated might become the
default, in which case this logic breaks as the line would now e
From: BALATON Zoltan
Return default value in legacy mode for BAR4 when unset. This can't be
set in reset method because BARs are cleared on reset so we return it
instead when BARs are read in legacy mode. This fixes UDMA on amigaone
with AmigaOS.
Signed-off-by: BALATON Zoltan
Message-ID: <20231
From: Fam Zheng
If the text description file is larger than DESC_SIZE, we force the last
byte in the buffer to be 0 and write it out.
This results in a corruption.
Try to allocate a big buffer in this case.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1923
Signed-off-by: Fam Zheng
The vhost-user-blk export implement AioContext switches in its drain
implementation. This means that on drain_begin, it detaches the server
from its AioContext and on drain_end, attaches it again and schedules
the server->co_trip coroutine in the updated AioContext.
However, nothing guarantees tha
On Tue, 2023-11-28 at 01:20 +, Volodymyr Babchuk wrote:
> Hi David,
>
> Thank you for the review
>
> David Woodhouse writes:
>
> > [[S/MIME Signed Part:Undecided]]
> > On Fri, 2023-11-24 at 23:24 +, Volodymyr Babchuk wrote:
> > > Xen PV devices in QEMU can be created in two ways: either
On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> Am 26.06.23 um 14:29 schrieb Michael S. Tsirkin:
> > From: Suravee Suthikulpanit
> >
> > Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> > (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is no
On Tue, 28 Nov 2023, Philippe Mathieu-Daudé wrote:
On 28/11/23 13:47, BALATON Zoltan wrote:
On Sun, 26 Nov 2023, BALATON Zoltan wrote:
Philippe,
Could this be merged for 8.2 as it fixes USB on the amigaone machine?
This would be useful as usb-storage is the simplest way to share data
with the
On 11/27/23 18:13, Chalapathi V wrote:
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet
binutils 2.39 shows some warnings when building pvh.img
/usr/bin/ld: warning: pvh.o: missing .note.GNU-stack section implies executable
stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in a future
version of the linker
/usr/bin/ld: warning: pvh.img has a LOAD segment wit
> On Nov 1, 2023, at 9:16 AM, Mattias Nissler wrote:
>
> Wire up support for DMA for the case where the vfio-user client does not
> provide mmap()-able file descriptors, but DMA requests must be performed
> via the VFIO-user protocol. This installs an indirect memory region,
> which already wo
> On Nov 1, 2023, at 9:16 AM, Mattias Nissler wrote:
>
> PCI config space is little-endian, so on a big-endian host we need to
> perform byte swaps for values as they are passed to and received from
> the generic PCI config space access machinery.
>
> Signed-off-by: Mattias Nissler
Reviewed
Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
>> we received some reports about the new default causing issues for
>> certain guest OSes [0][1]. Namely, for Juniper vSRX, where boot fails
>> and Microsoft Windows, where querying an U
(Cc'ing Ariadne, libucontext maintainer)
On 21/1/21 19:53, Peter Maydell wrote:
On Tue, 5 Jan 2021 at 02:25, Joelle van Dyne wrote:
This introduces support for building for iOS hosts. When the correct Xcode
toolchain is used, iOS host will be detected automatically.
* block: disable features
Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
SM4 (GBT.32907-2016) is a cryptographic standard issued by the
Organization of State Commercial Administration of China (OSCCA)
as an authorized cryptographic algorithms for the use within China.
Use the crypto-sm4 meson build option fo
On Mon, 18 Sep 2023 18:02:34 +0200
Philippe Mathieu-Daudé wrote:
> APIC state is created under a certain condition,
> use the same condition to realize it.
> Having a NULL APIC state is a bug: use assert().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/i386/cpu-sysemu.c | 9 +++-
On Mon, 18 Sep 2023 18:02:35 +0200
Philippe Mathieu-Daudé wrote:
> QOM objects shouldn't access each other internals fields
> except using the QOM API.
>
> Declare the 'cpu' and 'base-addr' properties, set them
> using object_property_set_link() and qdev_prop_set_uint32()
> respectively.
>
> Si
On Mon, Nov 27 2023, Peter Maydell wrote:
> There is no architectural requirement that SME implies SVE, but
> our implementation currently assumes it. (FEAT_SME_FA64 does
> imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
> you quickly run into an assert when the guest tries to w
[Cross-posted to KVM, Rust-VMM, QEMU, and libvirt lists)
Hi, the CFP for the "Virt & IaaS" DevRoom is out[+].
Something new this year is a new talk-submission system: so you need to
create a new account, even if you've had an account with the older
talk-submission system. Details in the "Submit
On Mon, 18 Sep 2023 18:02:36 +0200
Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
> ---
> target/i386/kvm/kvm-cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
> index 723737
On 11/26/23 09:56, Paolo Bonzini wrote:
Il sab 25 nov 2023, 13:23 Petr Cvek mailto:petrcve...@gmail.com>>
ha scritto:
GCC defines __i386__ for i386 and i486, which both lack RDTSC instruction.
The i386 seems to be impossible to distinguish, but i486 can be identified
by checking
Hi Hyman,
On 28/11/23 16:24, Hyman Huang wrote:
Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
SM4 (GBT.32907-2016) is a cryptographic standard issued by the
Organization of State Commercial Administration of China (OSCCA)
as an authorized cryptographic algorithms for the use with
On Mon, 18 Sep 2023 18:02:37 +0200
Philippe Mathieu-Daudé wrote:
> QDev instance is expected to be in an unknown state until full
> object realization. Thus we shouldn't call DeviceReset() on an
> unrealized instance. Move the cpu_reset() call from *before*
> the parent realize() handler (effecti
On Tue, Nov 28, 2023 at 03:53:21PM +0100, Fiona Ebner wrote:
> Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> > On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> >> we received some reports about the new default causing issues for
> >> certain guest OSes [0][1]. Namely, for Juniper
On Tue, Nov 28, 2023 at 11:00:29AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 28, 2023 at 03:53:21PM +0100, Fiona Ebner wrote:
> > Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> > > On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> > >> we received some reports about the new de
On Mon, 18 Sep 2023 18:02:38 +0200
Philippe Mathieu-Daudé wrote:
> qemu_init_vcpu() is called in each ${target}_cpu_realize() before
> the call to parent_realize(), which is cpu_common_realizefn().
> Call it once there.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/core/cpu-common.c
On Tue, Nov 28, 2023 at 04:57:20PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Hyman,
>
> On 28/11/23 16:24, Hyman Huang wrote:
> > Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
> >
> > SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> > Organization of State Commercia
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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On Tue, 21 Nov 2023 at 12:35, Kevin Wolf wrote:
>
> Kevin Wolf (2):
> qdev: Fix crash in array property getter
> string-output-visitor: Support lists for non-integer types
>
> hw/core/qdev-properties.c| 33 ++---
> qapi/string-output-visitor.c | 24
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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On 28/11/23 15:02, Richard Henderson wrote:
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
To allow GTIMER_* definitions to be used by non-ARM specific
hardware models, move them to a new target agnostic "cpu-defs.h"
header.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-defs.h |
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