One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the TOD value to a SCOM address.
This implemen
The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a
per-core register. Add the necessary SMT helpers.
The TFMR can only drive the timebase state machine via thread 0 of the
core, which is almost certainly not right, but it is enough for skiboot
and other proprietary firmware.
S
The ChipTOD (for Time-Of-Day) is a chip pervasive facility that keeps a
time of day clock, and can synchronise that clock to other chips, and
can synchronize that clock to the timebase facility in each core.
This model implements basic status and error registers, and XXX
emulation of chiptod regi
>From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB
and accessed with mftb instruction. The problem is that TB is the name
of the 64-bit register, and 32-bit implementations can only read the
lower half with one instruction, so 268 has also been called TBL and
it does only read T
This implements the core timebase state machine, which is the core side
of the time-of-day system in POWER processors. This facility is operated
by control fields in the TFMR register, which also contains status
fields.
The core timebase interacts with the chiptod hardware, primarily to
receive TO
On Fri Nov 24, 2023 at 4:39 PM AEST, Nicholas Piggin wrote:
> The ChipTOD (for Time-Of-Day) is a chip pervasive facility that keeps a
> time of day clock, and can synchronise that clock to other chips, and
> can synchronize that clock to the timebase facility in each core.
>
> This model implements
On 11/24/23 07:39, Nicholas Piggin wrote:
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
target/ppc/helper_regs.c | 31 +
On 11/24/23 07:39, Nicholas Piggin wrote:
From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB
and accessed with mftb instruction. The problem is that TB is the name
of the 64-bit register, and 32-bit implementations can only read the
lower half with one instruction, so 268 has
On 11/24/23 07:39, Nicholas Piggin wrote:
The ChipTOD (for Time-Of-Day) is a chip pervasive facility that keeps a
time of day clock, and can synchronise that clock to other chips, and
can synchronize that clock to the timebase facility in each core.
This model implements basic status and error r
On 11/24/23 07:39, Nicholas Piggin wrote:
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs
On 11/24/23 07:39, Nicholas Piggin wrote:
The ChipTOD (for Time-Of-Day) is a chip pervasive facility that keeps a
time of day clock, and can synchronise that clock to other chips, and
can synchronize that clock to the timebase facility in each core.
This model implements basic status and error r
On 11/24/23 07:39, Nicholas Piggin wrote:
One of the functions of the ChipTOD is to transfer TOD to the Core
(aka PC - Pervasive Core) timebase facility.
The ChipTOD can be programmed with a target address to send the TOD
value to. The hardware implementation seems to perform this by
sending the
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